GB2094583A - Binary signal processing circuit - Google Patents

Abstract

The circuit in accordance with the invention has for its object to determine whether a binary signal is subjected to fluctuations or not. A product circuit (16) is provided two inputs of which receive the binary signal and the inversion of the binary signal, one being applied directly and the other via a first low-pass filter (15). The product circuit (16) is of such a structure that its output signal is equal to zero only then when the two input signals each correspond to one of the two states of the binary signal. If the binary signal fluctuates then the output signal of the first low-pass filter (15) assumes a value which is located between the two binary levels, and consequently in this case the output signal in the product circuit (16) differs, at least temporarily, from zero. Via a second low-pass filter (19) the output signal of the product circuit is applied to a threshold value circuit (20) the switching state of which indicates whether the signal to be processed fluctuates (often) or not. <IMAGE>

Description

SPECIFICATION Binary signal processing circuit The invention relates to a binary signal processing circuit. A circuit of this type is suitable for use in receivers for a transmission system in which in addition to the audio signal an (identification) signal is transmitted with a predetermined frequency and in which the signal receiver comprises an evaluation circuit which is responsive to this identification signal and indicates either the absence or the presence of the identification signal by means of a binary signal.

In, for example, radio broadcasttransmission a (19 kHz) pilot signal whose presence characterises a stereo transmitter is transmitted in addition to the audio signal. Traffic information transmitters broadcast also a 57 kHz identification signal. At present two identification signals which characterise a stereo transmission or a dual sound transmission are emitted during television transmissions in the Federal Republic of Germany.

In all these cases evalution circuits are required which respond when an identification signal is transmitted. In the event of good reception such evaluation circuits produce a stationary binary output signal which is in a first state when the identification signal is present and in a second state when the identification signal is absent. However, when the reception is significantly disturbed - for example by noise - the yes/no statement supplied by the binary output signal of the evaluation circuit becomes incorrect, which becomes manifest in that the binary output signal of the evaluation circuit continuously reciprocates between its two possible states.

The present invention has for an object to provide a circuit which can be responsive to binary output signal fluctuations of the above-mentioned type.

The invention provides a binary signal processing circuit of the type described in the opening paragraph in which the binary signal and the inversion of the binary signal are respectively applied, one directly and the other via a first low-pass filter to two inputs of a product circuit the output signal of which is equal to zero only when the two input signals each correspond to one of the two states of the binary signal, the output signal of the product circuit being applied to a threshold value circuit via a second low-pass filter.

When the binary signal does not fluctuate a signal which corresponds with one binary state is successively present at the output of the first low-pass filter and at one input of the product circuit, and a signal which corresponds to the other state of the binary signal is present at the other input of the product circuit, so that the output signal of the product circuit is zero. As a result thereof the output signal of the second low-pass filter is also equal to zero. When, however, the binary signal continuously reciprocates between its two possible states the output signal of the first low-pass filter assumes a value which corresponds to the instantaneous average value of the binary input signal and whose level is located between the logic levels of the binary signal.

At the other input the level of the binary signal continuously reciprocates between the two possible states of the binary signal. In that event the product circuit produces a signal which differs from zero, which is smoothed by the second low-pass filter and which is then applied to the threshold value switch, for example, a Schmitt trigger, which is triggered above a predetermined threshold value of the output signal of the second low-pass filter and the output signal of which consequently indicates whether the binary output signal fluctuates or not.

The product circuit may be, for example, an analog multiplier circuit when one of the two binary states of the signal to be processed corresponds to the signal value zero. The product circuit may comprise the series arrangement of a current source which produces a current which corresponds to the output signal of the first low-pass filter, and a switch which is controlled by the binary signal or its inversion, the current being applied to the input of the second low-pass filter through the series arrangement.

An essential feature of the product circuit is that its output signal is zero when the signals at its two outputs each correspond to one of the two states of the binary signals, and that its output signal differs from zero when a signal which is located between zero and one is present at its input which is connected to the output of the first low-pass filter and when at its other signal inputthe binary signal reciprocates between its two possible states.

In a processing circuit which is intended for a receiver having an evaluation circuit for responding to at least one identification frequency the input of which receives a square-wave signal having the identification frequency and whose binary output signal characterises either the absence or the presence of the identification frequency, the squarewave signal and the output signal from the product circuit may be superposed on each other with opposite polarities and the result being applied to the input of the second low-pass filter. The upper limit frequency of the second low-pass filter must then be below the identification frequency.

This structure is provided preferably for receivers for receiving two identification signals the evaluation circuit of which produces a binary signal whose two states correspond to the two identification signals. In the case of a good reception and the presence of one of the identification frequencies the output signal of the product circuit is zero for the reasons described in the foregoing, so that to the input of the second low-pass filter only the square-wave signal of, for example the positive polarity is applied which results in a certain level at the output of the second low-pass filter.If one of the two identification frequencies is present but the reception is not of a sufficient quality then there is produced at the output of the product circuit a signal which differs from zero and which because of its polarity which is opposite to the polarity of the square-wave signal is subtracted from this square-wave signal, so that the level at the output of the second low-pass filter also changes. A still more significant change is obtained when an identification frequency and consequently a square-wave signal is not present. The threshold value switch may be dimensions / such that it always responds when no identification frequency broadcast or when an identification fi equency is indeed broadcast but the reception is disturbed.This arrangement can also be used when only one single identification frequency must be detected by the evaluation circuit.

The second low-pass filter may comprise an RCnetwork the capacitor of which is charged by the square-wave signal and discharged by the output signal of the product circuit. The highest voltage across the capacitor is obtained when an identification frequency is present and good reception is ensured, as then the capacitor is only charged by the square-wave signal but not discharged. In the case of an undisturbed reception the capacitor is then partly discharged by the product circuit output signal which then differs from zero, so that the capacitor voltage is then lower than in the case of an undisturbed reception.In the absence of an identification frequency no square-wave signal for charging the capacitor is available, so that the capacitor voltage is then zero volt It should here be noted that DE-AS 2559860 discloses a receiver circuit in which a capacitor is likewise charged and discharged bytwo signals of opposite polarities and in which the capacitor voltage is applied to a threshold value switch in the form of a Schmitt trigger. With this circuit the coincidence between synchronising pulses and line flyback pulses and consequently the tuning to a television transmitter must be ascertained.

The invention will now be further described by way of example with reference to the accompanying drawings in which: Figure 1 shows a basic circuit diagram of a television receiver incorporating a circuit in accordance with the invention, Figure 2 is a block schematic circuit diagram of a circuit in accordance with the invention and Figure 3 shows the construction of portions of the said circuit.

In the receivershown in Figure 1 the highfrequency signal received by an aerial 1 is amplified in the high frequency portion 2 and mixed with an oscillator frequency. The intermediate frequency then formed is amplified and demodulated in an intermediate frequency portion 3. The resulting video signal is further processed in the circuit 4 and applied to the picture tube 5.

A sound-frequency stage 6 which is coupled to the intermediate frequency stage selects the sound intermediate frequency signal by means of filtering, which signal is demodulated in a demodulator portion 7. With mono transmissions the demodulator portion 7 produces a mono-signal at its outputs 71 and 72. In transmissions in accordance with the stereo/dual-sound method (cf. Rundfunk Technische Mitteilungen, Volume 23,1979 (No. 1, pages lotto 13) ) there are available at one output line half the sum signal of the channels "left" and "right" and at the other output line there are present the signal for the right-hand channel (stereo) ortwo different sound signals (sound A and sound B), respectively.

The two outputs 71 and 72 of the demodulator portion 7 are connected to the inputs of a dematrixing and change-over device 8, which supplies two loudspeakers 9 and 10. The dematrixing and change-over device 8 is so controlled by a logic circuit 13 that a total of four receiving modes are possible: mono reception (for mono and stereo transmissions); stereo reception; sound A or sound B. To this end the logic circuit 13 combine binary signals M and K which characterise the presence or the absence of the identification frequency with signals U and V which can be preset by the user, so that the user may choose in the event of stereo transmissions between mono and stereo reception, respectively and in two-sound transmissions between sound A and sound B.Further details thereof are comprised in the prior German Application P 30 36 973.4 and possibly in subsequent applications with the same priority as the above-mentioned application.

In two-sound/stereo transmissions the sound signal comprises in addition to the audio signal to be transmitted, which is available on the conductors 71 and 72, a pilot signal of 54.6875 kHz (3.5 times the line frequency), on which in dual sound transmissions an identification signal of 274.1 Hz (1/57 of the line frequency) and in stereo transmissions an identification signal of 117.5 Hz (1/133 of the line frequency) is amplitude modulated (modulation depth 50%). This pilot signal is selected in a circuit 11 by means of filtering, is demodulated and the demodulation product is converted into a square-wave signal. In stereo and in two-sound transmissions this results at the output of the circuit 11 in square-wave signals R having the transmitted identification frequency.

An evaluation circuit 12 produces the binary signal K which indicates a difference between the two identification frequencies (for example K = 0 for stereo transmissions and K = 1 for dual-sound transmissions). The circuit 12 may, for example, comprise a period measuring device in which the period of the square-wave signal R at its input is compared with a predetermined interval lying between the periods of the two identification frequencies. If the period is the longer a stereo transmission is involved; if the period is shorter a two-sound transmission is involved.However, when the reception is considerably disturbed, the zero transitions of the squarewave signals derived from the identification frequency fluctuate, so that the circuit 12 can no longer "distinguish" whether a stereo or a dual-sound transmission is involved; the output signal Kthen continuously reciprocates between zero and one. A further possible implementation is described in the application P 31 09 129 which was filed at the same day and bears the title "Schaltungsanordnung zum Detektieren jeweils eines von zwei Kennsignalen".

The same effects are then produced.

The square-wave signal R and the output signal K of the evaluation circuit 12 are furthermore applied to a circuit 14, which produces the binary output signal M. The binary output signal M changes to its first state (for example M = 0) when no identification frequency is available or when an identification fre quency is indeed available but the reception is how ever disturbed to such an extent that an unambigu ous distinction is no longer possible and as a result of which the binary signal K is not constant in the time, and assumes its second state (M = 1) when an identification signal is available and a perfect recep tion is ensured. The circuit 14, which is the subject of the present invention is shown in Figure 2 in a block schematic circuit diagram.

Via a low-pass filter 15 having a time constant between 100 and 400 ms the output signal K from the evaluation circuit 12 is applied to one input of a product circuit 16. The output signal of the low-pass filter 15 corresponds to the input signal, that is to say it is either "0" or "1", when the signal K is constant with time. If the signal K continuously reciprocates between the two logic levels a signal which is located between these two logic levels is obtained at the output of the low-pass filter 15. The low-pass filter 15 may, for example, comprise the parallel arrangement of a resistor and a capacitor which is chargeable by means of a current source which can be switched on and off by the signal K.

In addition, the signal K is applied to a second input of the product circuit 16 via a NOT-circuit 17.

The product circuit 16 may be in the form of an analog multiplier circuit where one of the two logic levels of the signal K corresponds to the signal value 0. In the stationary case, this is to say when K and K, respectively is constant, the output signal of the product circuit and of the multiplying stage, respectively is zero. If in contrast therewith the signal K is not stationary, that is to say it reciprocates between 0 and 1, the output signal of the low-pass filter 15 differs from zero, while the output signal of the NOTcircuit 17 reciprocates between zero and a finite value, so that the output of the product circuit 16 deviates from zero, at least in the moments in which K corresponds to a value different from zero.

At point 18 the square-wave signal with identification frequency produced by circuit 11 whose average value as a function of time has a (for example positive) polarity which is the opposite of the polarity of the average value as a function of time of the output signal of the product circuit 16 is superposed on the output signal of the product circuit 16. The difference is applied to a threshold value switch 20, for example a Schmitttrigger, via a low-pass filter 19. The upper limit frequency of the low-pass filter 19 must be considerably lowerthan the lower identification frequency, that is to say its value must be low compared to 117 Hz; for reasons of efficiency it has been given exactly the same value as the limit frequency of the low-pass filter 15.The Schmitt trigger 20 must be adjusted such that it is responsive to an output voltage of this low-pass filter 19 which is located between the output voltage of this low-pass filter in the event of mono-reception on the one hand and the output voltage in the event of undisturbed stereo or dual sound reception on the other hand.

Figure 3 shows the blocks 16,18 and 19 in greater detail. The output signal K is applied to the base of a transistor 21 the emitter of which is connected to the emitter of a further transistor 22 whose collector is connected to the operating voltage Us and whose base is connected to a constant voltage, for example Us/2. A current source which is formed by a series resistor 23 and the collector-emitter path of a transistor 24, the emitter of which is connected to ground, is connected into the emitter lead which is common to the two npn-transistors 21 and 22. Via a resistor 25 the base of transistor 24 is connected to the output of the low-pass filter 15 (Figure 2).The collector current of the transistor 21 flows through a first current mir ror which is formed by the transistor 26, 27 and 28 and the output current of which is applied to a sec ond current mirror which is formed by the transistors 29 and 30. The output current iab of the second current mirror consequently corresponds to the col lector current of the transistor 21 and is proportional to that current.

The square-wave signal R is applied to the base of a transistor 31 the emitter of which is connected to ground and the collector via a resistor 32 to a third current mirror formed by the transistors 33 and 34.

The transistor 31 is made conductive and nonconductive by the square-wave signal R in the rhythm of the identification frequency, and the output current izu of this third current mirror also varies in a corresponding manner.

The collector-emitter path of the output transistor 34 of the third current mirror which produces the current izu which corresponds to the square-wave signal R is arranged between ground and the supply voltage U5 in series with the collector-emitter path of the output transistor 30 of the second current mirror.

The low-pass filter 19 which is formed by the parallel arrangement of a resistor 35 and a capacitor 36 is arranged in parallel with the last-mentioned output transistor. As a result thereof the capacitor 36 is charged by the output current izu of the third current mirror and discharged by the output current iab of the second current mirror. The following two modes of operation are possible: a) the transmitter broadcasts (dual-sound or stereo signals) with identification frequency; good reception. In this case the signal K is stationary and consequently also the output signal of the low-pass filter 15.Two signals (K, K) having logic levels which are complementary to each other are present at the bases of the series arranged transistors, so that one of the two transistors 21,24 is always nonconductive (it being a requirement that one of the two logic levels corresponds to a voltage which has a value which is lower than the base-emitter voltage of the transistor 24 required for a current flow).

Therefore the collector current of the transistor 21 is in this case always equal to 0 and consequently also the output current iab of the second current mirror, which discharges the capacitor 36. However, the charging current izu which varies in a square-wave manner as a function of time and charges the capacitor 36 in a pulse-shaped mannerflowssimul- taneously, until the capacitor voltage has reached a constant average final value which is, for example, just below the voltage U5.

b) The transmitter broadcasts signals with the identification frequency; the reception is, however, weak and disturbed by noise. In this case the signal K is not constant with time, so that the output voltage of the low-pass filter 15 is located between the val ues determined by the signals K - 0 and K = 1, respectively. If the fluctuations occur often enough then the output voltage of the low-pass filter exceeds the base-emitter voltage of the transistor 24, so that this transistor conducts.Simultaneously, transistor 21 is continuously made non-conductive and conductive via its base by the signal K which fluctuates in synchronism with the signal K (it being assumed that one logic level [K =0 or K = 1] corresponds to a voltage which is more positive than the base bias voltage UB/2 of the transistor 22). As a resultthereof transistor 21 carries a collector current which fluctuates in the rhythm of the fluctuations of the signals K between zero and a value determined by the magnitude of the low-pass filter output signal and consequently by the frequency of occurrence of the fluctuations.As a result thereof a current tab which differs from zero is obtained at the output of the second current mirror, which current discharges the capacitor 36. In spite of the presence of the squarewave signal which produces the square-wave current izu, the capacitor 36 can therefore, in this mode of operation not be charged to the same extent as described in the foregoing.

c) the transmitter broadcasts signals without identification frequency. In this case the transistor 31 is permanently nonconductive, so that the capacitor 36 is not charged. Independent of the behaviour of the signal Kthe capacitor voltage consequently remains zero.

The capacitor voltage is applied to the Schmitttrigger 20 (Figure 2), the threshold value of which must be adjusted such that it is lower than the capacitor voltage resulting from mode of operation a) but above the capacitor voltage in the mode of operation b) and c), respectively. The response of the Schmitttrigger 20 can not only be influenced by var iation of the threshold value but also by variation of the charging and/or discharging current-for example by changing the emitter areas of the transistors in the current mirrors.

Claims (5)

1. A binary signal processing circuit, characterised in that the binary signal and the inversion of the binary signal are respectively applied, one directly and the other via a first low-pass filter to two inputs of a product circuit the output signal of which is equal to zero only when the input signals each correspond to one of the two states of the binary signal, the output signal of the product circuit being applied to a threshold value circuit via a second low-pass filter.

2. A circuit as claimed in Claim 1 for a receiver having an evaluation circuit for responding to at least one identification frequency the input of which receives a square-wave signal having the identifica tion frequency and the output signal of which characterises either the absence or the presence of the identification frequency, characterised in that the square-wave signal and the output signal from the product circuit are superposed on each other with opposite polarities and the result being applied to the input of the second low-pass filter.

3. A circuit as claimed in Claim 2, characterised in that the second low-pass filter comprises an RCnetwork the capacitor of which is charged by the square-wave signal and discharged by the output signal of the product circuit.

4. A circuit as claimed in any of the preceding Claims, characterised in that the product circuit comprises the series arrangement of a current source which produces a current which corresponds to the output signal of the first low-pass filter and a switch which is controlled by the binary signal, or its inversion, the said current being applied to the input of the second low-pass filter via the said series arrangement.

5. A binary signal processing circuit substantially as herein described with reference to the accompanying drawings.