JPH0115176B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a binary signal processing circuit. This type of circuit transmits an (identification) signal having a predetermined frequency in addition to the audio signal, and has an evaluation circuit in the signal receiver that responds to the identification signal and displays the presence or absence of the identification signal as a binary signal. It is suitable for use in transmission systems comprising:

For example, in wireless transmission, a stereo transmitter transmits a pilot signal (19KHz) representing a stereo broadcast in addition to an audio signal. The traffic information transmitter also transmits a 57KHz identification signal. Currently, in television transmissions in the Federal Republic of Germany, two identification signals are transmitted, each representing a stereo broadcast and a dual-audio broadcast (for example, a bilingual broadcast).

In all these cases, an evaluation circuit is required that responds to the identification signal when it is transmitted. In the case of good reception conditions, the evaluation circuit has a stable 2 state, which is in the first state when the identification signal is present and in the second state when the identification signal is not present.
Generates an advance force signal. However, if the reception is disturbed, for example by noise, the yes/no indication provided by the binary output signal of the evaluation circuit will be inaccurate. That is, in this case, the binary output signal of the evaluation circuit continuously fluctuates back and forth between the first state and the second state.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a binary signal processing circuit that is responsive to variations in a binary signal as described above. For this purpose, the binary signal processing circuit of the present invention directly processes a binary signal and its inverted binary signal.
The other one passes through the first low-pass filter and then goes to the multiplier circuit 2.
input terminals respectively, so that the output signal of the multiplier circuit becomes zero only when each of the two input signals corresponds to each of the two states of the binary signal, and the output signal of the multiplier circuit The present invention is characterized in that the output signal is supplied to the threshold circuit through the second low-pass filter.

According to the binary signal processing circuit of the present invention, when the binary signal does not vary, a signal corresponding to one state of the binary signal appears at the output terminal of the first low-pass filter and one input terminal of the multiplication circuit, Since a signal corresponding to the other state of the binary signal appears at the other input terminal of the multiplier circuit, the output signal of the multiplier circuit becomes zero. As a result, the output signal of the second low-pass filter also becomes zero. However, if the binary signal fluctuates continuously between its two states, the output signal of the first low-pass filter will exhibit a value corresponding to the instantaneous average value of the binary input signal, and It has a level located between two logical levels. The level of the binary signal at the other input terminal of the multiplier circuit is 2
The leading signal continuously changes back and forth between two states. In this case, the multiplier circuit generates a signal different from zero, which signal is smoothed by a second low-pass filter and fed to a threshold switch, for example a Schmitt trigger. Since the Schmitt trigger is triggered by the output signal of the second low pass filter above a predetermined threshold, the output signal is indicative of whether the binary signal is changing.

The multiplier circuit can be an analog multiplier circuit, for example, when one of the two binary states of the signal to be processed is to be set to a zero value. In another example of the present invention, the multiplication circuit is constituted by a series circuit consisting of a current source that generates a current corresponding to the output signal of the first low-pass filter and a switch controlled by a binary signal or its inverted signal, The current of the current source is supplied to the input terminal of the second low-pass filter via this series circuit.

The essential feature of this multiplier circuit is that its output signal is zero when each of the signals at both of its input terminals corresponds to each of the two states of the binary signal;
A binary signal between "0" and "1" is present at the input terminal connected to the output terminal of the first low-pass filter, and a binary signal that changes back and forth between two states is present at the other input terminal. exists, the output signal is at a point where it no longer becomes zero.

For a receiver, the evaluation circuit is equipped with a circuit for evaluating at least one identification frequency, the evaluation circuit receiving at its input terminal a rectangular wave signal having the identification frequency and generating an output signal indicating whether or not the identification frequency is present. In another example of the binary signal processing circuit of the present invention configured as follows, the rectangular wave signal and the output signal of the multiplication circuit are superimposed with opposite polarities and then supplied to the input terminal of the second low-pass filter.

This configuration is suitable for a receiver in which two identification signals are received and the evaluation circuit generates a binary signal representing one identification signal in one state and the other identification signal in the other state. . When there is a good reception condition and one of the two identification frequencies is present, the output signal of the multiplier circuit becomes zero for the reason mentioned above, so the input terminal of the second low-pass filter receives a square wave signal (e.g. (positive polarity) is supplied, and the output of the second low-pass filter becomes a predetermined level. If one of the two identification frequencies is present but the reception condition is poor, a non-zero signal is generated at the output terminal of the multiplier circuit, which signal is of opposite polarity to the square wave signal and is subtracted from this square wave signal. Therefore, the output level of the second low-pass filter also changes.
Furthermore, large changes occur in the absence of the identification frequency and therefore the square wave signal. The threshold switch can therefore be designed to respond when the identification frequency is not being transmitted and when the identification frequency is being transmitted but reception is being interfered with.

In principle, this binary signal processing circuit can also be used if only one identification frequency needs to be detected by the evaluation circuit.

In yet another embodiment of the invention, the second low-pass filter is constructed with an RC network including a capacitor that is charged with the square wave signal and discharged with the output signal of the multiplier circuit. When the identification frequency exists and the reception condition is good, this capacitor is only charged with the rectangular wave signal and is not discharged, so that the highest voltage can be obtained between both ends of the capacitor. In the reception jamming condition, the capacitor is partially discharged by the non-zero output signal of the multiplier circuit, so that the capacitor voltage is lower than in the undisturbed reception condition. If there is no identification frequency, there is also no square wave signal to charge the capacitor, so the capacitor voltage will be zero volts.

German Patent Application No. 2559860 discloses a receiving circuit in which a capacitor is charged and discharged with two signals of opposite polarity and the capacitor voltage is supplied to a Schmitt-triggered threshold switch. However, in the case of this circuit, the coincidence between the synchronization pulse and the line flyback pulse,
Therefore, the tuning to the television transmitter must be determined.

The invention will be explained with reference to the drawings.

In the receiver shown in FIG. 1, a high frequency signal received by an antenna 1 is amplified in a high frequency stage 2 and mixed with a local oscillation frequency. The intermediate frequency obtained thereby is amplified and demodulated in the intermediate frequency stage 3. The demodulated video signal is further processed in a circuit 4 and supplied to a picture tube 5.

The audio frequency stage 6 coupled to the intermediate frequency stage 3 takes out the audio intermediate frequency signal by filtering,
This audio intermediate frequency signal is demodulated in demodulation stage 7. In the case of monaural broadcasting, the demodulation stage 7 generates a monaural signal at its output terminals 71 and 72.
Stereo/dual audio transmission method (“Rund funk”)
"Technische Mitteilungen" Vol.23, 1979, pp10
-13), one output terminal receives the sum signal of the "left" and "right" channels, and the other output terminal receives the "right" channel (stereo) signal and two types of audio signals (A voice and B voice) are obtained. Two output terminals 71 and 72 of demodulation stage 7
is connected to a dematrix/switching device 8, which drives two speakers 9 and 10.
The dematrix/switching circuit 8 uses a logic circuit 13 to select monaural reception (for monaural and stereo broadcasting), stereo reception, A audio or B audio reception.
It is controlled so that two reception modes are possible.
For this purpose, the logic circuit 13 combines binary signals M and K, representing the presence and absence of the identification frequency, with signals U and V, which can be preset by the user, so that the user can receive monophonic signals in the case of stereo broadcasting. For either stereo reception, A for two-audio broadcasting.
It is configured so that either voice or B voice can be selected. For details, please refer to the German patent application
Disclosed in p3036973.4.

In dual audio/stereo broadcasting, the transmitted signal is 54.6875 KHz (3.5 times the line frequency) in addition to the audio signal to be transmitted (appearing on output lines 71 and 72).
This pilot signal includes an identification signal of 274.1Hz (1/57 of the line frequency) in the case of two-audio broadcasting, and an identification signal of 117.5Hz (1/133 of the line frequency) in the case of stereo broadcasting. The identification signal is amplitude modulated (modulation depth is 0.5). This pilot signal is filtered and demodulated in circuit 11, and the demodulated component is converted into a rectangular wave signal. Therefore, in the case of stereo broadcasting and dual audio broadcasting, the output of the circuit 11 is a rectangular wave signal R having the transmission identification frequency.

The circuit 12 receives a signal K representing the difference between the two identification frequencies (for example, in the case of stereo broadcasting, K=0,
In the case of two-audio broadcasting, K=1,) is generated. This circuit 12 can be configured, for example, by a period measuring device that compares the period of the input rectangular wave signal R with a predetermined period intermediate between the periods of each of the two identification frequencies. If the period of the input rectangular wave signal R is longer, it is a stereo broadcast, and if it is shorter, it is a two-audio broadcast. However, if the reception is significantly interfered with, the zero transition of the square wave signal derived from the identification signal frequency fluctuates, so that the circuit 12
It becomes impossible to "identify" whether it is a stereo transmission or a two-audio broadcast. That is, in this case, the output signal continuously changes back and forth between "0" and "1". Another possible detection method is disclosed in German patent application no. P3109129, but the same problem arises in this case as well.

The square wave signal R and the output signal K of the evaluation circuit 12 are fed to a circuit 14 which generates a binary output signal M. The binary output signal M is the first when no identification signal is present or when a particular identification signal is present but its reception is interfered with to such an extent that clear identification is impossible and the binary signal K is not constant. state (for example, M=0), and changes to a second state (M=1) when a specific identification signal is present and complete reception is occurring. This circuit 14 is the object of the present invention, and is shown in block diagram form in FIG.

The output signal K of the evaluation circuit 12 is passed through the low-pass filter 15 having a time constant of 100 to 400 ms to the multiplication circuit 1.
6. low pass filter 1
When the input signal K is constant, the output signal of 5 becomes "0" or "1" corresponding to the input signal. However, if the signal K fluctuates continuously between two logic levels, a signal located between the two logic levels will be available at the output of the low-pass filter 15.
The low-pass filter 15 can be composed of a parallel circuit of a resistor and a capacitor that can be charged by a current source that can be turned on and off by the signal K, for example.

Furthermore, the signal K is supplied to the second input terminal of the multiplication circuit 16 via the NOT element 17. Multiplication circuit 16
converts one of the two logic levels of signal K to signal value O
In this case, it can be configured with an analog multiplication circuit. In a stable state, ie, when K and are constant and do not change, the output signal of this multiplier circuit is zero. On the other hand, if the signal K is not constant and changes back and forth between 0 and 1, the output signal of the low-pass filter 15 will have a value different from zero, and the output signal of the NOT element 17 will have a value between zero and a finite value. Since the multiplier circuit 16 changes back and forth between , the multiplier circuit 16 becomes a non-zero value during the time when at least the value is non-zero.

Identification frequency rectangular wave signal R generated in circuit 11
is superimposed on the output signal of the multiplier circuit 16 at a point 18. The average value of the rectangular wave signal R as a function of time has an opposite polarity to the average value of the output signal of the multiplier circuit 16 as a function of time. The difference between the two signals is applied via a low-pass filter 19 to a threshold switch 20, for example a Schmitt trigger. low pass filter 1
The upper limit frequency of 9 needs to be significantly lower than the identification frequency. In other words, it is necessary to set the value significantly lower than 117Hz, and for efficiency reasons, the low-pass filter 1
The value was set to be the same as the upper limit frequency of 5. The Schmitt trigger 20 responds to the output voltage of the low-pass filter 19 located between the output voltage of the low-pass filter 19 in the case of monaural reception and the output voltage of the low-pass filter 19 in the case of uninterrupted stereo reception and audio multiplex reception. need to be adjusted accordingly.

Figure 3 shows blocks 16, 18 and 19 of Figure 2.
Show details. The output signal is provided to the base of transistor 21. The emitter of this transistor 21 is connected to the emitter of another transistor 22, and the collector of the transistor 22 is connected to the power supply voltage.
connected to U _B , whose base is a constant voltage, e.g.
Connected to U _B /2. A current source consisting of a series resistor 23 and a collector-emitter path of a common emitter transistor 24 is connected in the common emitter lead of both transistors 21 and 22. The base of transistor 24 is connected via resistor 25 to the output terminal of low pass filter 15 (FIG. 2). The collector current of the transistor 21 is the transistor 26,
The current flows through a first current mirror circuit consisting of 27 and 28, the output current of which is supplied to a second current mirror circuit consisting of transistors 29 and 30. Therefore, the output current i _ab of the second current mirror circuit corresponds to the collector current of the transistor 21 and is proportional to this current.

The rectangular wave signal R is supplied to the base of a transistor 31 whose emitter is grounded and whose collector is connected via a resistor 32 to a third current mirror circuit consisting of transistors 33 and 34. Since this transistor 31 is turned on and off at the rhythm of the identification frequency by the rectangular wave signal R, the output current i _zu of the third current mirror circuit also changes accordingly.

The collector-emitter path of the output transistor 34 of the third current mirror circuit, which generates a current i _zu corresponding to the square wave signal R, is connected between the supply voltage U _B and ground to the collector of the output transistor 30 of the second current mirror circuit. Connected in series with the emitter passage. A resistance filter 18 consisting of a parallel circuit of a resistor 35 and a capacitor 36 is connected in parallel with the output transistor 30 of the second current mirror circuit. As a result, the capacitor 36 receives the output current i _zu of the third current mirror circuit.
The output current i _ab of the second current mirror circuit is used to charge and discharge the output current i ab of the second current mirror circuit, and the following two modes of operation are possible.

a. If the transmitter transmits a (bi-audio or stereo) identification frequency signal and the reception is good; in this case the signal K remains constant and does not change;
Therefore, the output signal of the low-pass filter 15 is also constant. Two signals K and a transistor 2 connected in series are connected to each other with logic levels of opposite polarity.
4 and 21, so that one of the transistors 21 and 24 is always non-conducting (this requires one of the two logic levels to be lower than the base-emitter voltage required to make transistors 21 and 24 conductive). value voltage). Therefore, in this case, the collector current of the transistor 21 is always zero, and therefore the output current _iab of the second current mirror circuit discharging the capacitor 36 is also zero. However, a charging current i _zu that changes in a rectangular waveform as a function of time and charges the capacitor 36 in pulses flows until this capacitor voltage reaches a constant average final value (eg, a value slightly lower than the voltage U _B ).

b The transmitter is transmitting an identification frequency signal, but
If its reception is weak and disturbed by noise; in this case the signal K fluctuates and the low-pass filter 1
The output voltage of No. 5 has a value between the voltage value of K=0 and the voltage value of K=1. When the fluctuations become frequent, the output voltage of low pass filter 15 exceeds the base-emitter voltage of transistor 24, causing this transistor to conduct. At the same time, the transistor 21 is continuously turned on and off by a signal that fluctuates in synchronization with the signal K (one signal level K=0 or K=1 is the base bias voltage U _B /2 of the transistor 22).
(assumed to be a more positive voltage). As a result, the transistor 21 conducts a collector current which varies with the rhythm of the fluctuations of the signal K between a zero value and a value determined by the magnitude of the output signal of the low-pass filter 15 and thus the frequency of occurrence of the fluctuations. As a result, the non-zero current
i _ab is obtained at the output terminal of the second current mirror circuit,
This current discharges capacitor 36. Therefore, in this mode of operation, the capacitor 36 cannot be charged to the same extent as in the above-described mode of operation, despite the presence of a square wave signal that generates a square wave current i _zu .

c. When the transmitter transmits a monaural signal and does not transmit an identification signal; in this case, the capacitor 36 is not charged because the transistor 31 is permanently non-conductive. Therefore, the capacitor voltage is maintained at zero regardless of the operation of signal K.

This capacitor voltage is the Schmitt trigger 20
(Figure 2). The threshold value of this shot trigger is adjusted to a value lower than the capacitor voltage occurring in operating mode a, but higher than the capacitor voltage occurring in operating modes b and c. The response characteristics of the Schmitt trigger 20 can be controlled not only by changing the threshold value, but also by changing the charging and/or discharging current, for example by changing the emitter area of the transistor of the current mirror circuit.

[Brief explanation of drawings]

FIG. 1 is a basic circuit diagram of a television receiver equipped with a binary signal processing circuit according to the present invention, and FIG. 2 is a basic circuit diagram of a television receiver equipped with a binary signal processing circuit according to the present invention.
FIG. 3 is a block circuit diagram of an example of a forward signal processing circuit, and FIG. 3 is a detailed circuit diagram of a portion of FIG. DESCRIPTION OF SYMBOLS 1... Antenna, 2... High frequency stage, 3... Intermediate frequency stage, 4... Video processing stage, 5... Picture tube, 6... Audio frequency stage, 7... Demodulation stage, 8... Dematrix and switching device, 9, 10... Speaker, 11... Rectangularization circuit, 1
2... Evaluation circuit, 13... Logic circuit, 14... Binary signal processing circuit, 15... First low pass filter, 16...
Multiplier circuit, 17...NOT element, 18... Superimposition point, 1
9...Second low-pass filter, 20...Threshold switch (schmitt trigger).

Claims (1)

[Claims] 1. A binary signal K and its inverted binary signal are input to two input terminals of a multiplier circuit 16, one directly and the other via a first low-pass filter, to generate the multiplier circuit. The output signal of the multiplier circuit is made zero only when each of its two input signals corresponds to each of the two states of the binary signal K, and the output signal of the multiplier circuit is passed through a second low-pass filter 19. A binary signal processing circuit characterized in that the binary signal processing circuit is configured to supply the signal to the threshold value switch circuit 20 through the threshold value switch circuit 20. 2. A receiver that is a circuit for evaluating at least one identification frequency and has an evaluation circuit at its input terminal that receives a rectangular wave signal having the identification frequency and generates an output signal representing the presence or absence of the identification frequency, respectively. In the binary signal processing circuit according to claim 1, after the rectangular wave signal R and the output signal of the preceding multiplication circuit 16 are superimposed with opposite polarities, A binary signal processing circuit configured to supply a binary signal. 3. In the binary signal processing circuit according to claim 2, the second low-pass filter includes a capacitor that is charged with the rectangular wave signal i _zu and discharged with the output signal i _ab of the multiplier circuit. A binary signal processing circuit comprising RC circuit networks 35 and 36. 4. In the binary signal processing circuit according to any one of claims 1 to 3, the multiplication circuit 1
6 consists of a series circuit of current sources 23 and 24 that generate a current corresponding to the output signal of the first low-pass filter 15 and a switch controlled by the binary signal or its inverted signal (K or); The current i _ab
A binary signal processing circuit characterized in that the signal is supplied to the input terminal of the second low-pass filter 18 via this series circuit.