GB2081972A

GB2081972A - Non volatile ram element

Info

Publication number: GB2081972A
Application number: GB8100510A
Authority: GB
Original assignee: Plessey Co Ltd
Current assignee: Plessey Co Ltd
Priority date: 1980-08-07
Filing date: 1981-01-08
Publication date: 1982-02-24
Also published as: DE3131436A1; GB2081972B

Abstract

A non-volatile dynamic ram element utilizes a conventional random access memory element in combination with a non-volatile semiconductor memory element. The ram element (23, 24, 25) and memory element (27, 30, 31) may be isolated from one another by electrode 28, the memory element being utilized to store data from in the ram element when required and this data being retained in the semiconductor memory element independently of further normal operation of the ram element. True data may be returned to the ram element at any convenient time. The surface portion of region 27 of the memory element has such a dopant concentration that it inverts when a predetermined amount of charge of suitable polarity is trapped in an overlying insulating layer 30. <IMAGE>

Description

SPECIFICATION Non-volatile ram element United Kingdom Patent Application No.

8009223 describes a semiconductor memory element of relatively high packing density and utilising relatively simple non-epitaxially isolated technology.

This invention seeks to provide a non-volatile random access memory (RAM) element in which the semiconductor memory element of the above patent application is utilised.

According to this invention there is provided a random access memory element comprising a semiconductor substrate of a first conductivity type provided with first and second diffused regions of opposite conductivity type; a first electrode overlying surface portion of each of the substrate and the first diffused region; a second electrode overlying a portion of the substrate adjacent the first electrode; a third electrode adjacent the second electrode and overlying a portion of each of the substrate and the second diffused region; a charge trapping dielectric layer overlying a surface portion of each of the second diffused region and the substrate; a gate electrode overlying the charge trapping dielectric layer and wherein the second diffused region has a surface doping concentration such that the surface portion of the second diffused region beneath the charge trapping dielectric layer inverts in conductivity type when a predetermined amount of charge of a suitable polarity is trapped in the charge trapping dielectric layer and the concentration of charge of opposite polarity attracted to the inverted region approaches degeneracy.

Typically the surface doping concentration of the second diffused region is greater than 1018 cam~3.

The first, second and third electrodes may each overlie via an intermediate dielectric layer which may be formed from silicon oxide, silicon nitride or aluminium oxide.

The charge trapping dielectric layer may overlie each surface portion via an intermediate dielectric layer which may be silicon oxide.

The second electrode may be electrically isolated from and overlie a portion of each of the first and third electrodes.

The electrical isolation may be provided by layers of silicon oxide.

The first, second, third and gate electrodes may be formed from polysilicon.

An exemplary embodiment of the invention will now be described with reference to the drawings in which; Figures la and 1b illustrate alternative embodiments of a p-channel semiconductor memory element which forms part of a random access memory element in accordance with the present invention; Figure 2 illustrates the out-of-fabrication charge structure of the memory element of Fig. 1; Figure 3 illustrates the written charge structure of the element of Fig. 1; Figure 4 shows a band structure diagram for the written structure of Fig. 3; Figure 5 illustrates schematically the flow of tunnel current during the reading of a written element illustrated in Fig. 3; Figures 6a and 6b illustrate alternative methods of erasing a written element; Figure 7 illustrates current voltage characteristics for the element of Fig. 1 in various states;; Figure 8 illustrates current voltage characteristics for an n-channel version of the element of Fig. 1, Figure 9 illustrates the change of the characteristics of Fig. 8 with time Figure 10 shows a conventional random access memory element and Figure 11 illustrates a random access memory element in accordance with the present invention.

Referring to Fig. 1 a there is shown a pchannel version of a semiconductor memory element in accordance with this invention comprising an N type silicon semiconductor substrate generally referenced 1 having a surface 2 into which is diffused a P type region 3. The diffused region 3 has a boundary edge 4 which extends to the surface 2 of the substrate 1.

A thin layer 5 of silicon oxide is formed on the surface 2 so as to overlie a portion of the surface 2 of the substrate 1 and a surface portion of the diffused region 3. The oxide therefore crosses the boundary region 4 between the diffused regions 3 and the remaining portion of the substrate 1. A layer of silicon nitride which is a charge trapping dielectric material is formed on the oxide layer 5 and therefore also overlies surface portions of both the P type diffused region 3 and the N type substrate 1. Remaining surface portions of the P type diffused region 3 and N type substrate 1 are protected by a thick layer of silicon oxide 7.

Electrical contact is made to the silicon nitride layer 6 by means of an aluminium contact layer 8 which also extends partly over the thick oxide layer 7. The diffused region 3, the oxide and nitride layers 5 and 5 respectively and the aluminium layer 8 are formed by well known semiconductor processing techniques including photolithographic masking and etching.

In operation of the memory element a negative voltage may be applied to the aluminium gate 8 relative to the diffused region 3, a suitable value being of the order of 40 volts.

The application of this negative potential to the gate 8 causes a significant quantity of positive charge to be trapped in charge trapping sites in the silicon nitride dielectric layer 6. This action is similar to that in known MNOS transistor memory elements but in the present invention the diffused region 3 has a surface doping concentration such that the charge trapped in the nitride layer 6 attaches a sufficiently large number of charges of opposite polarity to the surface of the P type diffused region 3, that this surface region inverts and becomes N type forming a PN junction at the surface of the diffused region 3.

To effect this inversion the doping concentration at the surface of the diffused region 3 must be such that the attracted charged concentration approaches degeneracy. To achieve this action a typical doping concentration of greater than 1018 carriers per cubic centimetre is required. In this state the memory element is referred to as being written and the state will be retained due to the retention of the trapped charge in the nitride layer 6 after removal of the initial negative voltage applied to the gate electrode 8.

Referring now to Fig. 1b where like parts to those in Fig. la bear like reference numerals, the only essential difference is that the diffused region 3 is now provided in the shape of an annular ring, the silicon nitride layer 6 now being provided to overlie the surface 2 in the centre of the annular ring and to extend to overlap the surface of the P type diffused region 3.

Referring now to Figs. 2 and 3 these illustrate charge structures for the memory element in the out of fabrication, that is as manufactured but before writing, and the written element respectively.

In Fig. 2, the device as fabricated contains a small amount of trapped positive charge 9 within the silicon nitride layer 6 but this is insufficient to cause any inversion of the surface of the P type diffused region 3. The physical boundary within the substrate 1 of the diffused region 3 is illustrated at 4 and on each side of this boundary extends a depletion region, the edge of which in the diffused region 3 is indicated by the dashed line 10.

The depletion edge in the substrate 1 is indicated by the solid line 11. As can be seen, where the depletion region boundary 11 approaches the surface 2 of the substrate 1 the surface width 12 of the depletion region is slightly pinched.

In Fig. 3 the memory element is in the written state with a large amount of trapped positive charge within the silicon nitride dielectric layer 6. As indicated previously this trapped charge is sufficient in view of the surface doping concentration within the diffused region 3, to cause an N type inversion layer 13 to be formed at the surface of the P type diffused region 3. This inverted region 13 forms a PN diode with the P type diffused substrate 3 and a further depletion region having a boundary 14 is formed at this PN junction Referring now to Fig. 4 this shows a band structure diagram for the PN diode formed by the diffused region 3 and the surface inversion region 13 in a written memory 1 element.

The band 1 5 represents the donor band for the P type diffused region 3 whilst the band 16 represents the donor band for the inverted region 13. The band 17 represents the acceptor band for the diffused region 3 whilst the band 18 represents the acceptor band for the inverted region 13.

Under conditions of slight reverse bias of the PN diode formed after inversion a tunnel current can flow through the depletion region before the diode breaks down and this is illustrated by the arrows 19.

The flow of tunnel current is illustrated schematically for the memory element structure shown in Fig. 6 and as can be seen this flows from the diffused region 3 across the depletion region into the inverted region 13 and into the substrate 1.

As will be explained later in order to read a written device the flow of tunnel current before avalanche breakdown under slight reverse bias conditions is sensed.

In order to erase a written device it is necessary to disperse the charge which is trapped and stored in the silicon nitride layer and this is illustrated in diagrams (a) and (b) of Fig 6 which respectively show alternative ways of performing this erasure.

In the first method illustrated in Fig. 6a a large negative voltage typically 40 volts or more is applied to the diffused region 3 relative to the gate electrode 8 and the substrate 1. This causes the boundary 11 of the depletion region within the substrate 1 to expand outwardly at 20 thereby causing the trapped charge within the silicon nitride layer 6 also to move outwardly and to disperse into the substrate 1.

In Fig. 6b a positive voltage is applied to the gate electrode 8 of the silicon nitride layer 6 and this causes a uniform outward spreading of the depletion region edge 11, as illustrated at 21 and a corresponding uniform spreading of the charge stored in the silicon nitride dielectric layer 6. This charge once again decays into the substrate 1.

Referring now to Fig. 7 there are shown characteristic curves of the memory element illustrating the flow of current from the diffused region 3 to the substrate 1 in dependence upon the value of the voltage applied to the diffused region 3 for each of three states of the memory element, these states being the written state illustrated in curve (a), the out-of-fabrication state illustrated in curve (b) and the erased state illustrated in curve (c).

The memory element described is implemented in p-channel technology but the memory element may equally well be fabricated in N-channel technology which has the advantage of allowing lower operating voltages.

Characteristic current-voltage curves of an equivalent N-channel memory element are shown in Fig. 8. This Figure once again shows the flow of current between the diffused region and the substrate in dependence upon the value of voltage applied to the diffused region and the curves are again plotted for each of three states of the memory element.

Two sets of curves are shown, those with a solid line being for zero volts applied to the gate electrode of the memory element whilst those curves shown with a dashed line are for + 5 volts applied to the gate electrode.

Curves (a) and (b) show the full and dashed line curves respectively for the element in the written state whilst curve b is also the solid line curve for the element in the out-of-fabrication state. The dashed line curve for the element in this state is that shown in line (c).

Curves (d) and (e) show the full line and dashed line curves respectively for the element in the erased state.

Fig. 9 illustrates the way in which the curves decay after a period of 20 hours at 175 C. Curves (a), (b) and (d) in Fig. 9 correspond with curves (a), (b) and (d) in Fig.

8. The dashed line curve (c) is that curve to which curve (a) decays after the decay period whilst curve (d) decays to curve (e).

Referring now to Fig. 10 this shows a conventional random access memory element formed in N channel technology. Referring to Fig. 10 the element consists of a silicon substrate 22 in which is formed a N plus diffused region 23. A polysilicon electrode 24 overlies surface portions of the substrate 22 and the diffused region 23 via the intermedi- ary of a thin layer of silicon oxide (not shown).

A second polysilicon electrode 25 extends on the surface of the substrate 22 adjacent the electrode 24 and overlaps the electrode 24 at 26, but is electrically isolated therefrom by a thin layer of silicon oxide (not shown).

Data is stored and read in the memory element by selective use of potentials Ol and 82 applied to the electrodes 24 and 25 respectively. A potential ~ 2 typically of + 12 volts applied to the electrode 25 will create a potential well in the substrate 22 beneath the electrode 25. By the application of a similar + 12 volt potential ~1 to the electrode 24, and a suitable potential to the diffused region 23 the potential well created beneath the electrode 25 may either be maintained full or empty of charge in dependence upon the logical state of the data to be stored.

In order to create a full potential well beneath the electrode 25 the potential 81 is maintained at + 12 volts and the potential ~1 applied to the electrode 24 is pulsed to the same value of + 12 volts. With the diffused region 23 maintained at zero volts charge will be injected from the N plus diffused region 23 into the potential well beneath the electrode 25.

In order to read the memory element the potential 82 applied to the electrode 25 is maintained at zero volts while the potential 81 applied to the electrode 24 is pulsed to + 12 volts. This causes charge in the potential well beneath the electrode 25 to be dumped into the diffused region 23 and suitable sensing circuitry may be used to sense the resulting current flow.

The memory element described above is a dynamic ram element since the stored data decays because regeneration currents cause the potential well beneath the electrode 25 to fill with charge with the elapse of time, typically of the order of 1 second. The stored data therefore has to be continually refreshed.

The above described memory element is of course a volatile element and does not store data when power is removed.

Referring now to Fig. 11 this shows a nonvolatile random access memory element in accordance with the present invention. In this Figure where like parts to those in Fig. 10 bear like reference numerals a second N plus diffused region 27 is provided in the substrate 22 and a third electrode 28 is formed on the substrate 22 to bridge surface portions of both the substrate 22 and the diffused region 27.

The electrode 28 also lies adjacent the electrode 25 and is overlapped thereby at 29 but the electrodes 28 and 29 are electrically isolated from one another by means of a thin layer of silicon oxide (not shown).

A silicon nitride layer 30 is formed on the substrate 22 and separated therefrom by a thin layer of silicon oxide (not shown). The silicon nitride layer 30 also overlies part of the surface of the diffused region 27. A fourth electrode 31 is provided on top of the silicon nitride layer 30.

The resulting non-volatile random access memory element thus formed essentially consists of two portions, one of which is the conventional RAM element as described with reference to Fig. 10 whilst the other is the non-volatile memory element of Fig. 1.

The substrate 22 together with the diffused region 23 and the electrodes 24 and 25 form the conventional random access memory element portion whilst the substrate 22, the diffused region 27, the silicon nitride layer 30 and the electrode 31 form an N-channel version of the non-volatile memory element of Fig. 1. The diffused region 27 corresponds to the region 3 of Fig. 1, the silicon nitride layer 30 corresponds to the layer 6 of Fig. 1 whilst the electrode 31 corresponds to the gate electrode 8 of Fig. 1. The two portions are interfaced by means of the electrode 28 as will become apparent in due course.

Data which is stored in the conventional random access memory element by use of the potentials 81 and 82 applied to the electrodes 24 and 25 may be stored in non-volatile form by use of potentials 83 and 84 applied to the electrodes 31 and 28 respectively.

The function of the electrode 28 is to isolate the conventional ram portion of Fig.

11 from the non-volatile memory element portion formed by the diffused region 27 the nitride layer 30 and the gate electrode 31.

When the potential 84 applied to the electrode 28 is set at zero volts, then the diffused region 27 will be electrically isolated from the surface potential beneath the electrode 82.

whilst if 84 is set at + 12 volts then the diffused region 27 will assume the same potential as the surface of the substrate 22 beneath the electrode 25.

Assume that the potential well under the electrode 25 is full of negative charge so that the surface potential of the silicon substrate 22 immediately beneath the electrode 25 is at zero volts.

In order to store this data state in nonvolatile form the potential 84 is pulsed to + 12 volts so that the N + diffused region 27 assumes the same potential of zero volts.

If the 83 potential applied to the electrode 31 is also pulsed to + 12 volts at the same time as the potential 84 is pulsed to + 12 volts, then there will be approximately a 12 volt potential difference across the silicon nitride layer 31. This is the required condition for the semiconductor memory element described above to be transformed into the written condition in which charge is trapped in the silicon nitride layer 30.

If on pulsing 83 and ~4, the potential well beneath the electrode 25 had been empty so that the surface potential of the silicon substrate 22 beneath the electrode 25 was at + 12 volts rather than zero volts, then the diffused region 27 would also have assumed a + 12 volt potential and there would have been no potential difference across the silicon nitride layer 30. The memory element would therefore have remained in the unwritten state and there would have been no charge trapping in the silicon nitride layer 30.

Once data in the ram element has been stored the potentials 83 and 84 applied to the electrodes 29 and 31 respectively are returned to zero so that the conventional ram element and the non-volatile semiconductor memory element are effectively isolated from one another. The ram element may be clocked to change the data therein without affecting the data stored in the memory element portion. The stored data need not be called back immediately and the conventional ram element portion may be operated independently In order to read back stored data the potential 81 is maintained to zero volts and 82 is set at + 12 volts so as to create an empty potential well beneath the electrode 25.The potential 83 is maintained at zero volts and the potential ~4 is brought to the same + 12 volts potential as 82. The diffused region 27 will assume the potential of the silicon surface beneath the electrode 25 and under these conditions if the semiconductor memory element is in the written state tunnel current will flow in the manner described above and will flow into the potential well beneath the electrode 25 so as to fill this well.

The surface potential beneath the electrodes 25 will gradually decrease until tunnel current ceases to flow. A well full of charge and having a zero surface potential will result beneath the electrode 25 which exactly reproduces condition which originally caused the writing of the memory element during the data storage stage. It can be seen therefore that real data has been returned to the ram element.

If the semiconductor memory element is in the erased state with no charge trapped in the silicon nitride layer 30 the N plus region 27 assumes the surface potential of the substrate 22 beneath the electrode 25 and no tunnel current flows through the diffused region 27 due to the absence of charge trapped within the silicon nitride layer 30. In the absence of a tunnel current the potential well beneath the electrode 25 does not fill with charge and the surface potential remains at 12 volts.

Real data in the form of an empty potential well is returned since this was the condition during reading which caused no charge to be trapped within the silicon nitride layer 30.

As explained above the non-volatile ram element of this invention effectively consists of two parts, one a conventional ram element portion and the other a storage portion. The ram element portion can be operated quite independently of the storage portion this latter portion only being used to store data in a nonvolatile manner when power is to be removed.

Under these circumstances 83 and 84 would be pulsed together to + 12 volts immediately before the removal of power. When power is restored the data stored in the nonvolatile memory element portion need not be recovered immediately but may be retained in the memory element whilst the ram element portion operates in a conventional manner.

The present invention provides a true nonvolatile ram element. Currently known nonvolatile MNOS elements are not true ram elements but only PROM elements. The present invention provides a true ram element which is non-volatile.

The invention has been described by way of example and modifications may be made without departing from the scope of the invention.

In particular the electrodes 24, 25, and 29 are separated from the substrate by a thin layer of silicon oxide but this is not essential and a separating layer of silicon nitride or aluminium oxide could be used instead. In addition the electrode 25 overlaps each of the electrodes 24 and 28 but this is not essential.

The electrodes, although formed in the example in polysilicon may also be formed from metal.

The invention may be implemented in both n and p-channel technology.

Claims

1. A random access memory element comprising a semiconductor substrate of a first conductivity type provided with first and second diffused regions of opposite conductivity type; a first electrode overlying surface portion of each of the substrate and the first diffused region; a second electrode overlying a portion of the substrate adjacent the first electrode; a third electrode adjacent the sec orid electrode and overlying a portion of eacbi of the substrate and the second diffused region; a charge trapping dielectric layer overlying a surface portion of each of the second diffused region and the substrate; a gate electrode overlying the charge trapping dielectric layer and wherein the second diffused region has a surface doping concentration such that the surface portion of the second diffused region beneath the charge trapping dielectric layer inverts in conductivity type when a predetermined amount of charge of a suitable polarity is trapped in the charge trapping dielectric layer and the concentration of charge of opposite polarity attracted to the inverted region approaches degeneracy.

2. A random access memory element as claimed in claim 1 in which the surface doping concentration of the second diffused region is greater than 1018cm-3.

3. A random access memory element as claimed in claim 1 or 2 in which the first, second and third electrodes each overlie via an intermediate dielectric layer.

4. A random access memory element as claimed in claim 3 in which the intermediate dielectric layer is formed from silicon oxide, silicon nitride, or aluminium oxide.

5. A random access memory element as claimed in any preceding claim in which the charge trapping dielectric layer overlies each surface portion via an intermediate dielectric layer.

6. A random access memory element as claimed in claim 5 in which the charge trapping dielectric layer overlies each surface portion via an intermediate dielectric layer.

7. A random access memory element as claimed in claim 5 in which the intermediate dielectric layer is silicon oxide.

8. A random access memory element as claimed in any preceding claim in which the second electrode is electrically isolated from and overlies a portion of each of the first and third electrodes.

9. A random access memory element as claimed in claim 8 in which the electrical isolation is provided by layers of silicon oxide.

10. A random access memory element as claimed in any preceding claim in which the first, second, third and gate electrodes are formed from polysilicon.

11. A random access memory element substantially as herein described with reference to and as illustrated in Fig. 11 of the drawings.