DE3131436A1 - "VENTILATED MEMORY ELEMENT (RAM) WITH DIRECT ACCESS" - Google Patents

Description

Non-volatile memory element (RAM) with direct access

GB Patent Application No. 8009223 discloses a semiconductor memory element described with a relatively high packing density, in which a relatively simple, 'non-epitaxial technology with insulation applied.

The object of the invention is to create a non-volatile one Memory element (RAM) with direct access in which the semiconductor memory element from the above-mentioned patent application applies.

The direct access memory element (RAM) provided by the invention is characterized by a semiconductor substrate of a first conductivity type, with a first and a second diffused region, the conductivity type of which is opposite; a first electrode over a
Surface part of the substrate as well as the first diffused area lies; a second electrode covering one part
the substrate is adjacent to the first electrode; a third electrode adjoining the second electrode and
diffused over part of the substrate and the second

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Area lies; a charge trapping dielectric layer / the over a surface portion of the second diffused area as well as the substrate; a gate electrode overlying the charge trapping electrical layer; whereby the second diffused region has such a surface doping concentration comprises that the surface part of the second diffused region, which is below the dielectric Charge trapping layer, changes its conductivity type, when a predetermined amount of charge of suitable polarity in of the charge trapping dielectric layer, and the charge concentration of opposite polarity / that of is attracted to the area that changes its conductivity type has approximated the state of degeneration.

In a particular embodiment, the surface doping concentration of the second diffused region is more than 10 ¹⁸ cm ^-3 .

The first, second and third electrodes can each be superimposed with the interposition of a dielectric intermediate layer be those made of silicon oxide, silicon nitride, or aluminum oxide can be formed.

The charge trapping dielectric layer may each have a surface part with the interposition of a dielectric intermediate layer be overlaid, which can be made of silicon oxide.

In a further embodiment, the second electrode is electrically insulated from a part of each of the first and second electrodes the third electrode over which it lies.

In a further embodiment, the electrical insulation is produced by silicon oxide layers.

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According to a further feature of the invention, the first, second, third and fourth gate electrodes made of polysilicon educated.

Further features and advantages of the invention result from the following description of exemplary embodiments with reference to the drawing. In the drawing show:

1a and 1b two different embodiments of a p-channel semiconductor memory element, which is a Part of a memory element (RAM element) forms with direct access of the invention;

FIG. 2 shows the charge structure of the storage element according to FIG. 1 at the end of the manufacturing process;

3 shows the written charge structure of the storage element according to Fig. 1;

FIG. 4 is a diagram showing the course of the bands in the structure according to FIG. 3 after writing; FIG.

Fig. 5 is a schematic representation of the course of the tunnel current during readout in a memory element according to FIG. 3, which has been written into;

6a and 6b show two different embodiments for erasing the memory content of a memory element;

7 shows the current-voltage characteristics of the memory element according to FIG. 1 in different states;

8 shows the current-voltage characteristic for an n-channel version of the memory element according to FIG. 1;

9 shows the change in the characteristic over time Fig. 8;

Fig. 10 shows a conventional direct access memory element; and

FIG _o 11 a storage element for direct access in accordance with the invention,

In Fig. La is a p-channel embodiment of a semiconductor memory element shown according to the invention, with an N-silicon semiconductor substrate, which is generally designated 1 and has a surface 2 into which a P-region 3 diffuses is. The diffused area 3 has a delimiting edge 4 which extends towards the surface 2 of the substrate

1 extends out.

A thin layer 5 of silicon dioxide is on the surface

2 formed so as to be over a part of the surface 2 of the substrate 1 and a surface part of the diffused area 3 lies. The oxide therefore crosses the delimitation area 4 between the diffused areas 3 and the rest Part of the substrate 1. A layer of silicon nitride which is a charge trapping dielectric material is formed on the oxide layer 5 and therefore also surface parts of both the diffused P-region and the substrate 1 of the N conductivity type are superimposed. The remaining surface parts of the diffused P-area

3 and the N-type substrate 1 are covered by a thick silicon oxide layer 7 protected.

The electrical contact with the silicon nitride layer 6 is made by a contact layer 8 made of aluminum, the furthermore extends partially over the thick oxide layer 7. The diffused area 3, the oxide layer 5 and the nitride

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Layer 6 as well as the aluminum layer 8 are well known by means of Manufacturing processes formed from semiconductor technology, including photolithographic masking and etching processes .

_R In the operation of the semiconductor element may be a negative voltage to the aluminum layer 8 and the gate formed therefrom over the diffused region 3 applied with a suitable voltage value is on the order of 4O V. By applying this negative potential to the gate 8, a considerable amount of positive charge is trapped at charge trapping sites in the silicon nitride dielectric layer. This effect is similar to that of known MNOS transistor memory elements; In the memory element according to the invention, however, the diffused region 3 has such a surface doping concentration that this charge trapped in the nitride layer 6 fixes such a large number of charge carriers of positive polarity in the surface of the diffused P region 3 that this surface region changes to the N conductivity type and a PN junction is formed on the surface of the diffused region 3.

In order to bring about this reversal, the doping concentration must at the surface of the diffused area be such that the concentration of the attracted charges brings about an approach to the state of degeneration. Around To bring about effect is a doping concentration of

1 8

more than 10 load carriers per cubic centimeter required. In this state, the memory element is used as such referred to i.n that was inscribed, and this state is retained after removal of the initially applied negative voltage at the gate electrode 8, because the charges in the Nitride layer 6 are captured.

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In Fig. 1b, in which corresponding elements are denoted by the same reference numerals as in Fig. 1a, there is The only significant difference is that the diffused area 3 is now annular, the silicon nitride layer 6 is formed so that it is in the middle of the Ring is above the surface 2 and extends so far that it overlaps the surface of the diffused P-region 3.

Reference is now made to FIGS. 2 and 3, which show the Charge structures of the storage element at the end of the manufacturing process show in the state before or after registered mail.

As shown in Fig. 2, the completed assembly includes a small amount of a trapped positive charge 9 within the silicon nitride layer 6, which however is insufficient, around an envelope of the surface of the diffused P-region 3 evoke. The physical interface of the diffused area in the interior of the substrate 1 is denoted by 4; on either side of this interface extends a depletion type region, the edge of which is in the diffused Area is denoted by a dashed line 10. The edge of the depletion type area in Substat 1 is through a solid line 11 is indicated. As from the drawing As can be seen, the surface width is 12 of the depletion type area where the interface 11 of the depletion type region approaches the surface 2 of the substrate 1, rejuvenates.

In Fig. 3, the memory element is in the state after writing, with a large amount of trapped positive charges inside the silicon nitride dielectric layer 6. As previously stated, this is enough this trapped charge in terms of surface

doping concentration within the diffused region 3 to form an N-type inversion layer 13 the surface of the diffused P-region 3 to generate. This inverted region 13 forms a PN diode with the P diffused substrate 3, and another depletion type region with an interface 14 is formed at this PN junction.

Reference is now made to Figure 4 which is a band diagram shows for the PN diode, which in a memory element after writing through the diffused area and the Surface inversion region 13 is formed.

The band 15 represents the donor band for the diffused P-region 3, while the belt 16 represents the donor belt for the inverted region 13. The belt 17 represents the acceptor belt for the diffused area 3, while the band 18 represents the acceptor band for the inverted area 13.

Under the conditions of a low bias voltage of the PN diode in the reverse direction, which occurs after the inversion or the change of the Conduction type is formed, a tunnel current can flow through the depletion type area flow before the diode breaks down, which is shown by arrows 19.

The tunnel current profile is for the memory element shown in FIG. 6 shown schematically; this current passes from the diffused region 3 through the depletion type region to the inverted region 13 and into the substrate 1.

As will be explained later, an arrangement after writing the tunnel current before the avalanche collapse under "the low bias conditions detected in reverse direction.

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In order to erase a memory array after it has been written, the one captured and stored in the silicon nitride layer must Charge will be dispersed; this is shown in diagrams a and b of FIG. 6, in which two different Possible solutions for realizing this deletion are shown.

In the first deletion method shown in FIG. 6a a high negative voltage, in particular of 40 V or more, to the diffused region opposite the gate electrode 8 and applied to the substrate 1. This expands the interface 11 of the depletion type area inside the substrate 1 to the outside at the point indicated by 20, which causes the trapped inside the silicon layer 6 Charge also migrates outward "and into the substrate 1 is dispersed.

In Fig. 6b, a positive voltage is applied to the gate electrode 8 of the silicon nitride layer 6, whereby a uniform Expansion of the edge 11 of the depletion type area is effected outwardly, as shown in the drawing by the Reference numeral 21 is indicated, with a corresponding uniform expansion in the dielectric silicon nitride layer 6 stored charge. Here, too, this charge is dissipated into the substrate 1.

Reference is now made to Fig. 7, in the characteristics of the Storage element are shown, the current flow from the diffused area 3 into the substrate 1 depending on the value of the applied to the diffused area 3 Voltage for three states of the storage element are shown; these states are; State after writing, i.e. curve a; State at the end of manufacture, i.e. Curve b; deleted state, i.e. curve c.

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The memory element described is in p-channel technology manufactured; However, it can also be produced in N-channel technology, with the advantage that lower operating voltages be made possible. The current-voltage characteristics of an equivalent N-channel memory element are shown in FIG. 8 shown. In this figure, too, the flow of current between the diffused area and the substrate is dependent of the value of the voltage applied to the diffused area, the curves here also for the three states of the spexcher element are shown.

Two groups of curves are shown, namely with a solid line for 0 volts at the gate electrode of the Spexcher element and dashed for +5 volts, which are applied to the gate electrode. The curves a and B are those with the solid line Characteristic curves shown in dashed or dashed lines for the element after writing, while curve b furthermore is the characteristic curve drawn in with a solid line for the element at the end of its manufacture. The characteristic for the element in this state, "is the dashed curve c. The curves d and e show with solid lines and dashed lines, respectively the item in the deleted state.

Fig. 9 shows how the curves drop after 20 hours at 175 ° C, FIGS. A, b and d in FIG. 9 correspond to curves a, b and d in FIG. 8. The dashed curve c is the one to which curve a drops after the fall time has elapsed, while curve d drops to curve e.

Reference is now made to Fig. 10, which shows a conventional memory element for a random access memory (RAM) using N-channel technology. This element consists of a silicon substrate 22 in which. an N ⁺ diffused region 23 is formed. A polysilicon electrode 24 overlies surface portions of the substrate

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22 and the diffused area with interposition a thin layer of silicon oxide (not shown). A second electrode 25 made of polysilicon extends on the Surface of the substrate 22 is adjacent to the electrode and overlaps the electrode 24 at the designated 26 However, location / is electrically isolated from this by a thin layer of silicon oxide (not shown).

In the memory element, data are stored or read out by the selective application of potentials φ1 and φ2, which are at the electrode 24 and 25 are applied. A potential φ2 of typically 12 V applied to electrode 25 creates a potential well in the substrate 22 under the electrode 25. By applying the same potential φ1 with +12 V to the electrode 24 and a suitable potential to the diffused area 23 can be the under the electrode generated potential wells are either filled with charges or kept free of charges, depending on the digital status of the data to be saved.

In order to form a filled potential well under the electrode 25, the potential φ1 is kept at +12 V while the Potential 1 applied to the electrode 24 is pulsed with the same value of 12 V. When the diffused area 23 is at 0 V is held, a charge becomes from the diffused N region

23 is injected into the potential well under the electrode 25.

In order to read out the memory element, the potential φ2 applied to the electrode 25 is kept at G V while that is on the electrode 24 applied potential φ1 pulses with + 12V. As a result, the charge stored in the potential well under the electrode 25 is diverted into the diffused area 23, and suitable sensing circuitry can be used to sense the resulting current flow.

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The one described above. Storage element is a dynamic RAM element, as the stored data lose their intensity and refreshing currents a filling of the potential well effect under the electrode 25 after a period of typically about 1 second. The stored data must so be continuously refreshed.

The memory element described above is of course a volatile memory element in which the data is not stored stay when the power is turned off.

In Fig. 11 is a non-volatile memory element according to the invention for a direct access memory (RAM) is shown. In this figure, in the same. Elements with the same Reference numerals as denoted in FIG. 10 is a second N diffused region 27 in the substrate 22 is provided, and a third electrode 28 is formed on the substrate 22 so as to be surface parts of the substrate 22 and the diffused area 27 bridged.

The electrode 28 is also adjacent to the electrode 25 and is overlapped by it at the point marked 29, however, electrodes 28 and 29 are electrically separated from one another by a thin layer of silicon oxide (not shown) are isolated.

A silicon nitride layer 30 is formed on the substrate 22 and from this by a thin silicon oxide layer (not shown) separately. The silicon nitride layer 30 lies also over part of the surface of the diffused area 27. A fourth electrode 31 is provided on top of the silicon nitride layer 30.

The non-volatile RAM memory element thus formed exists essentially of two parts, one of which is the

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tional RAM memory element which has been explained with reference to FIG 10 _0, while the other nonvolatile memory element shown in Fig. 1.

The substrate 22 forms together with the diffused area 23 and the electrodes 24 and 25 the part of the conventional RAM memory element, while the substrate 22, the diffused area 27, the silicon nitride layer 30 and the electrode 31 an N-channel embodiment of the non-volatile Form memory element according to FIG. The diffused area 27 corresponds to the area 3 in FIG. 1, the silicon nitride layer 30 corresponds to layer 6 in FIG. 1, while electrode 31 corresponds to gate electrode 8 in FIG. 1. The two parts are coupled to one another by means of the electrode 28, as will be seen further below.

Those stored in the conventional RAM memory element by applying the potentials φ1 and φ2 to electrodes 24 and 25, respectively Data can be stored in non-volatile form by applying potentials φ3 and φ4 applied to the electrodes or 28 can be created.

The function of the electrode 28 is to separate the conventional RAM part in FIG. 11 from the part of the non-volatile To isolate the storage element that diffused through the Region 27, the nitride layer 30 and the gate electrode 31 is formed.

When the potential φ4 applied to the electrode 28 is 0 volts is set, the diffused area 27 is electrically isolated from the surface potential under the electrode 25, while, when setting the potential φ4 to + 12V, the diffused Area 27 assumes the same potential as the surface of the substrate 22 under the electrode 2-5.

It is now assumed that the potential well under the electrode 25 is filled with negative charge, so that the surface potential of the silicon substrate 22 immediately below the- "electrode 25 is at 0 volts .:. ■ ·.

In order to save this data status non-volatile, the potential φ4 is sampled or pulsed at +12 V, so that the N ⁺ -diffu:
accepts.

N -diffused area 27 has the same potential of 0 volts

If the ". At the same time as the potential is pulsed to +12 φ4 to the electrode 31 applied potential φ3 also with +12 V, so-there is a voltage difference of 12 V at the" Siliziumnitridschieht 31. This is the _required: state for the semiconductor memory element described above, so that it is brought into the state after writing, in which the charge irv the silicon nitride layer 30; - is trapped.

If with pulsating potentials φ3υηά φ4 the potential well below the electrode 25 was empty, so that the surface potential the silicon substrate 22 under the electrode 25; not is on Ö volts, but on +12 volts, then the diffused area 27 also assumes a potential of +.12 V, and it results no potential difference occurs on the silicon nitride 30. The memory element therefore remains in the state before writing, and there is no charge trapping operation in the silicon nitride layer 30. -

As soon as data is stored in the RAM memory element, the potentials applied to electrodes 28 and 31 become φ3 and φ4 are reset to zero, so that the conventional RAM memory element and the non-volatile semiconductor memory element are well isolated from each other, the RAM storage element can be clocked to change the data in it without

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affect the data that is in the storage element part are stored. The stored data do not need to be retrieved immediately, and that part of the conventional Storage element can be operated independently.

In order to read out stored data again, the potential φ1 is kept at 0 volts, while the potential φ2 is kept at + 12V is set to produce an empty potential well under the electrode 25. The potential φ3 is kept at 0 volts, while the potential φ4 is brought to the same potential as .φ2, i.e. to +12 V. The diffused area 27 increases the potential of the silicon surface under the electrode, and if under these conditions the semiconductor memory element is in the state after the writing has taken place, a tunnel current flows in the above-described Point into the potential well under the electrode 25 to fill it up.

The surface potential under the electrode 25 gradually decreases until the tunnel current flow ceases. One with loads filled well with the surface potential 0 results then under the electrode 25 in order to exactly reproduce the state that was originally written in the memory element during the data storage process. So it can be seen that data is actually in the RAM memory element are returned.

When the semiconductor memory element is in the deleted state is located at which no charge is trapped in the silicon nitride layer 30, the N region 27 takes the surface potential of the substrate 22 under the electrode 25, and no tunnel current flows through the diffused Area .27 because no charges are trapped in the silicon nitride layer. If there is no tunnel stream flowing, it becomes the potential trough under the electrode 25 not filled with charges,

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so that the surface potential remains at 12V.

It is then actual data in the form of an empty potential well restored, for this is the state during the readout in which charges are not caused are trapped within the silicon nitride layer 30.

As explained above, the non-volatile RAM memory element according to the invention consists of two parts, namely a part with a conventional RAM memory element, and with another part, namely a memory part ·. The part of the RAM memory element can be practically independent of the Storage part operated, the latter part only being used to store data in non-volatile form, when the power supply must be switched off.

Under these circumstances, the potentials φ3 and φ4 become common pulsed with + 12V immediately before the power supply is switched off. When the power supply is switched on again, those in the part of the non-volatile Storage element stored data are not immediately retrieved; rather, they can be in the storage element are pinned while the part · of the RAM storage element works in a conventional manner.

The invention actually makes a non-volatile one RAM storage element created. Conventional so-called incapable MNOS memory elements are not real RAM elements, but only PROM elements. The invention creates a real RAM element that is non-volatile.

In other embodiments "of the invention" are the electrodes 24, 25 and 29 from the substrate not through a thin layer separated from silicon oxide, but by a separating layer Silicon nitride or aluminum oxide. While-with the described-

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In an embodiment, the electrode 25 is both the electrode 24 and the electrode 28 overlap, this is not provided in other embodiments.

In other embodiments, the electrodes are not off Polysilicon, but from a metal.

The memory element according to the invention can be in both n and can also be implemented in p-channel technology.

Claims (9)

'■ ■.; - ; :. : -:: 313U36 Patent attorneys Dipl.-Ing. Dipl.-Chem. Dipl.-Ing. E. Prince - Dr. G. Hauser - G. Leiser Ernsbergerstrasse 19 8 Munich 60 PLESSEY OVERSEAS LIMITED. 7th August 1981 Vicarage Lane Ilford, Essex IG1 4AQ / England Our reference: P 2450 Non-volatile memory element (RAM) with direct access PATENT CLAIMS Memory element with direct access (RAM element), characterized by a semiconductor substrate of a first conductivity type, with a first and a second diffused area, the conductivity type of which is opposite? a first electrode overlying a surface portion of the substrate as well as the first diffused area; a second electrode overlying a portion of the substrate adjacent the first electrode; a third electrode adjacent to the second electrode and overlying a portion of the substrate and the second diffused area; a charge trapping dielectric layer overlying a surface portion of the second diffused region as well as the substrate; a gate electrode overlying the charge trapping dielectric layer; wherein the second diffused region has such a surface doping concentration that the surface part of the second diffused region, which lies under the charge trapping dielectric layer, changes its conductivity type when a predetermined ^v ο _ Charge amount of suitable polarity is trapped in the dielectric charge trapping layer, and the charge concentration opposite polarity, attracted by the area that has its conductivity type has changed, has approximated the state of degeneration. 2. Storage element according to claim 1, characterized in that that the surface doping concentration of the second diffused region is greater than 10 cm 3. Storage element according to claim 1 or 2, characterized in that that the first, second and third electrodes each with the interposition of a dielectric intermediate layer are superimposed. 4. Memory element according to claim 3, characterized in that the dielectric intermediate layer made of silicon oxide, Silicon nitride or aluminum oxide is formed. 5. Storage element according to one of the preceding claims, characterized in that the dielectric charge trapping layer in each case over the relevant surface parts with the interposition of a dielectric intermediate layer is arranged. 6. Storage element according to claim 5, characterized in that that the interlayer dielectric is made of silicon oxide. 7. Memory element according to one of the preceding claims, characterized in that the second electrode is electrical is isolated from a portion of both the first and third electrodes and is located above. 313U36 8. Memory element according to claim 7, characterized in that the electrical insulation by silicon oxide layers is formed. 9. Storage element according to one of the preceding claims, characterized in that the first, second, third and the gate electrode are formed from polysilicon.