GB2080616A - Power semiconductor devices - Google Patents
Power semiconductor devices Download PDFInfo
- Publication number
- GB2080616A GB2080616A GB8115206A GB8115206A GB2080616A GB 2080616 A GB2080616 A GB 2080616A GB 8115206 A GB8115206 A GB 8115206A GB 8115206 A GB8115206 A GB 8115206A GB 2080616 A GB2080616 A GB 2080616A
- Authority
- GB
- United Kingdom
- Prior art keywords
- mesa
- region
- defining
- conductive material
- major surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000000463 material Substances 0.000 claims description 21
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 230000005669 field effect Effects 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Bipolar Transistors (AREA)
Abstract
A mesa containing a power device is surrounded by a field electrode 30 contacting the semiconductor body. A vertical V-groove power MOSFET having a source 16, base region 14, drain 12 and insulated gate 22 is formed in a mesa. The source is contacted by an electrode 26 which extends over the side faces of the mesa to form a field electrode (source field plate). The mesa is surrounded by a field electrode 30 which contacts the drain region at 32. This electrode prevents any surface inversion layer from extending to adjacent derries. Reference is made to the use of this structure for diodes and bipolar transistors. <IMAGE>
Description
SPECIFICATION
Power transistor having improved termination
This invention relates generally to semiconductor devices and technology, and more particularly the invention relates to semiconductor power transistors.
Planar field effect transistors, particularly metal oxide silicon field effect transistors (MOSFET) have found applications in large scale integrated arrays and in discrete power devices. However, a limitation in power applications lies in the large surface area required for such devices. An improvement in power transistors has resulted from use of vertically aligned, grooved structures. By virtue of the Vgroove notch, formed by preferential etching of semiconductor material, the field effect transistor can be vertically constructed ratherthan laterally constructed, resulting in a shorter channel length and a lower source to drain on resistance.
Described in U. S. Patent 4,219,835 is a mesa structure, V-groove field effect power transistor. In this structure an insulating layer is disposed on a surface of the device and on the mesa sidewalls, with a metal layer disposed on the insulating layer to form a field electrode or source field plate. This unique mesa structure with the source field plate overlying the PN junctions of the mesa, provides improved breakdown voltage with corresponding low channel resistance.
An object of the present invention is an improved power mesa device transistor.
Another object of the invention is a V-groove field effect transistor and mesa structure having improved termination.
Yet another object of the invention is a method of terminating a power transistor to allow higher voltage breakdown with lower channel resistance.
Briefly, in accordance with the invention, a power device such as a diode or transistor is provided in a semiconductor body including a mesa defined on a major surface of the body. Active regions of the power device are defined in the mesa and an insulative material is provided on the surface of the mesa and extending to the major surface of the semi-conductor body. A first conductive material extends through the insulative material in contact with the semi-conductor body and surrounding the mesa, thereby providing a charge control ring on the surface of the device and maintaining the stability of the breakdown voltage of the power device.
In a preferred embodiment, the power device is a grooved vertical field effect transistor with the source and channel regions formed in the mesa and the substrate comprising the drain. The charge control ring contacts the substrate and drain region to discourage charge buildup on the surface of the substrate. A field electrode in electrical contact with the source and channel regions can be provided.
The invention and objects and features thereof will be more readily apparent from the following detailed description of an example, taken with the drawings, in which:
Figure 1 is a section view of a grooved field effect transistor in accordance with one embodiment of the present invention;
Figure 2 is a top view of the field effect transistor of Figure 1;
Figure 3 is a section view of the transistor of Figure 1 and illustrating equipotential voltage lines in the device; and
Figures 4A-41 are section views illustrating steps in fabricating the device of Figure 1.
Referring now to the drawings, Figure 1 is a section view of a power transistor in accordance with one embodiment of the present invention and
Figure 2 is a top view of the device. It will be appreciated that the figures are for illustration purposes and are not drawn to scale. In this embodiment the power transistor comprises a grooved mesa field effect transistor similar to the structure disclosed in Patent 4,219,835. The device comprises an N+ substrate 10 and an N- epitaxial layer 12. A P region 14, formed by ion implantation or by doped epitaxial growth, is formed above the
N- region 12 and a heavily doped N+ region 16 is formed in the P region 4. The N+ region 16 can be formed by selective diffusion of impurities into the P region 14, as will be described further hereinbelow, or other conventional techniques can be employed to form the region.A groove shown generally at 18 is formed in the structure and extends through the N+ region 16 and P region 14 into the N - region 12.
Silicon oxide 20 is formed on the surface of groove 18 and a conductor material 22 such as aluminum or doped polycrystalline silicon, for example, is formed over the silicon oxide 20 and forms the gate electrode of the field effect transistor with the region 16 functioning as the source, the regions 10 and 12 functioning as the drain, and the P region 14 between the source and drain comprising the channel region which is controlled by the gate electrode 22.
Silicon oxide material 24 is formed over the sides of the mesa with an electrical contact and conductive pattern 26 formed over the silicon oxide and ohmically contacting the source 16 and channel 14 regions, as shown. The portion of the conductive material 26 extending down the side of the mesa structure forms a source field plate (SFP).
For switching high voltages and currents, such a field effect transistor structure preferably provides a low on resistance, a fast switching speed, and a high breakdown voltage. The low resistance is achieved by the vertical structure. However, in achieving increased breakdown voltage the on resistance of the transistor is impacted.
In accordance with the present invention a termination scheme is provided to increase the breakdown voltage and control surface charge spreading, thus insuring device stability and reliability. As shown in the embodiment of Figure 1 and 2, a conductive layer 30 is provided on the structure which surrounds the grooved transistor and contacts the drain region at 32. Thus, the ring 30 has a voltage equal to the drain voltage thus preventing the buildup of charge in the silicon oxide material overlying the structure. A silicon oxide layer 34 covers the device.
Figure 3 is a section view of the structure, similar to Figure 1, and showing equipotential lines 36 within the drain-substrate region during device operation. By providing the mesa structure and termination the equipotential lines are smooth and relatively planar without abrupt changes in the lines near the substrate-silicon oxide interface. The equipotential lines extend through the silicon oxide between the field plate 26 and the charge control ring 30, as illustrated.
The device illustrated in Figure 1 is readily fabricated using conventional semiconductor techniques such as described in Patent 4,219,835. Steps in fabricating the device are illustrated in the section views of Figures 4A-41. It will be understood that this description is illustrative of one sequence of steps in fabricating the device, and that other conventional processes could be employed with the invention.
Referring to Figure 4A, the N+ substrate 40 (e.g.
0.007-0.05 ohm cm.) is provided. In Figure 4B the N epitaxial layer 42 (e.g. 5-8 ohm cm.) is grown on the substrate 40, and in Figure 4C the P region 44 is formed in the N epitaxial layer 42 by ion implantation (e.g. 1013 ions per cm.3) through oxide layer 43.
Alternatively, a P epitaxial layer can be grown on the
N epitaxial layer 42.
In Figure 4D a diffusion window 47 is etched through layer 43 and an N+ region 48 (e.g. 1019 atoms per cm.3) is formed by the diffusion of dopant through the window 47.
Thereafter, as shown in Figure 4E a new silicon
oxide 50 is thermally grown on the surface of region
48; and window 52 and windows 54 are formed
through the silicon oxide. As illustrated in Figure 4F a preferential etchant is then applied to the semicon
ductor body through the windows 52 and 54 and the
grooves 56, 58, and 60 are etched through the P
region into contact with the N- epitaxial layer 42.
As illustrated in Figure 4G, a thin oxide layer 62 is
formed on the surface of grooves 56, 58, and 60.
Doped polysilicon 66 is then formed on the silicon
oxide and selectively removed except over the gate
oxide. As shown in Figure 4H, additional silicon
oxide is deposited. Openings are etched through the
silicon oxide to expose the source 48 and channel 44
regions and the N- epitaxial layer 42. Thereafter, a
conductive material such as aluminum for example,
is applied over the silicon oxide layer and selectively
etched to form the source and field plate 68 in
contact with the source and channel regions, and the
charge control ring 70 in contact with layer 42.
Finally, as illustrated in Figure 41 a thicker insulation
layer 74 such as vapor deposited silicon oxide is
formed over the surface of the device.
By using the recessed charge control ring 70 in
combination with the source field plate 68 in the
recessed regions 56 and 60 surrounding thetransis
tor structure, a device termination is provided which
accommodates higher voltage and current switch ing. It will be appreciated that the described embodi
ment is illustrative and is not to be construed as
limiting the invention. For example, other mesa type
power diodes and transistors including bipolar and
vertical DMOS can be employed. The charge ring 70
can be placed directly on the semiconductor material without the underlying silicon oxide. The specific selection of device configuration may be determined by compatibility with the fabrication process used, in making the transistor structure.
Claims (10)
1. A power device comprising a semiconductor body having a major surface, a mesa on said major surface, at least one P-N junction in said mesa and defining active region of said power device, said power device being characterized by a first conductive material on said major surface surrounding said mesa and contacting said semiconductor body.
2. A power device as defined by claim 1 and further characterized by an insulative material on said major surface surrounding said mesa, said first conductive material overlying said insuiative material.
3. A power device as defined by Claim 1 or 2 and including a groove formed in said mesa, said plurality of P-N junctions defining source, channel, and drain regions of a field effect transistor,
4. A power device as defined by Claim 3 and further including insulative material on said mesa, and further characterized by a second conductive material in contact with said q3urce and channel regions and overlying said insulative material on said mesa, said second cot#Auctive.material being spaced from said first conductive material.
5. A vertical field effect powertransistorcom- prising a semiconductor body of a first conductivity type and having a major surface, a mesa on said major surface, a first region in said mesa-pt opposite conductivity type and defining a channei#region,a second region of said first conductivity type and defining a source region in said first region, a groove in said mesa extending through said first and second regions, a first insulative material formed over the surface of said groove, a first conductive material formed over said first insulative material and defining a gate electrode, an electrode second insulative material over the surface of said mesa, a second conductive material over said second insulative material, said second conductive material contacting said second region and defining a source contact, said transistor being characterized by a third conductive material in contact with said semiconductor
body and surrounding said mesa and defining a charge control ring.
6. A power transistor as defined by Claim q and t further characterized by a third insulative material on said major surface surrounding said mesa, said third
conductive layer overlying said third insulatiye. ç material. -
7. A power transistor as defined by Claim 5 or 6 wherein said second insulative material and said
second conductive layer extend down said mesa and
over a portion of said planar surface, said second
conductive layer comprising a field plate.
8. A power transistor as defined by Claim 7 wherein said semiconductor body comprises siLicon, said first insulative material, said second ir,suL,ve material, and said third insulative m2teriai wrnprise silicon oxide.
9. A power transistor as defined by Claim 8 wherein said first conductive material comprises doped polysilicon.
10. A field effect power transistor substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17056480A | 1980-07-21 | 1980-07-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2080616A true GB2080616A (en) | 1982-02-03 |
Family
ID=22620378
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8115206A Withdrawn GB2080616A (en) | 1980-07-21 | 1981-05-18 | Power semiconductor devices |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS5752170A (en) |
| DE (1) | DE3128035A1 (en) |
| FR (1) | FR2487128A1 (en) |
| GB (1) | GB2080616A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2227605A (en) * | 1989-01-30 | 1990-08-01 | Philips Electronic Associated | A vertical field effect semiconductor device |
| GB2291257A (en) * | 1994-07-12 | 1996-01-17 | Int Rectifier Corp | Polysilicon field ring structure for power IC |
| WO2001008226A2 (en) * | 1999-07-22 | 2001-02-01 | Koninklijke Philips Electronics N.V. | Cellular trench-gate field-effect transistors |
| WO2003023862A1 (en) * | 2001-09-13 | 2003-03-20 | Koninklijke Philips Electronics N.V. | Edge termination in a trench-gate mosfet |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5218070B2 (en) * | 1972-10-04 | 1977-05-19 | ||
| JPS5367382A (en) * | 1976-11-27 | 1978-06-15 | Mitsubishi Electric Corp | Semiconductor device |
| US4219835A (en) * | 1978-02-17 | 1980-08-26 | Siliconix, Inc. | VMOS Mesa structure and manufacturing process |
-
1981
- 1981-05-18 GB GB8115206A patent/GB2080616A/en not_active Withdrawn
- 1981-06-04 FR FR8111067A patent/FR2487128A1/en active Pending
- 1981-07-16 DE DE19813128035 patent/DE3128035A1/en not_active Ceased
- 1981-07-20 JP JP56113439A patent/JPS5752170A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2227605A (en) * | 1989-01-30 | 1990-08-01 | Philips Electronic Associated | A vertical field effect semiconductor device |
| GB2291257A (en) * | 1994-07-12 | 1996-01-17 | Int Rectifier Corp | Polysilicon field ring structure for power IC |
| US5686754A (en) * | 1994-07-12 | 1997-11-11 | International Rectifier Corporation | Polysilicon field ring structure for power IC |
| GB2291257B (en) * | 1994-07-12 | 1999-02-17 | Int Rectifier Corp | Polysilicon field ring structure for power ic |
| WO2001008226A2 (en) * | 1999-07-22 | 2001-02-01 | Koninklijke Philips Electronics N.V. | Cellular trench-gate field-effect transistors |
| WO2001008226A3 (en) * | 1999-07-22 | 2001-09-13 | Koninkl Philips Electronics Nv | Cellular trench-gate field-effect transistors |
| WO2003023862A1 (en) * | 2001-09-13 | 2003-03-20 | Koninklijke Philips Electronics N.V. | Edge termination in a trench-gate mosfet |
| US6833583B2 (en) | 2001-09-13 | 2004-12-21 | Koninklijke Philips Electronics N.V. | Edge termination in a trench-gate MOSFET |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3128035A1 (en) | 1982-04-15 |
| FR2487128A1 (en) | 1982-01-22 |
| JPS5752170A (en) | 1982-03-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |