FR2487128A1 - POWER TRANSISTOR COMPRISING AN IMPROVED ELECTRODE CONFIGURATION - Google Patents

Abstract

THE INVENTION CONCERNS SEMICONDUCTOR TECHNOLOGY. A MESA STRUCTURED POWER TRANSISTOR IN WHICH SOURCE 16, CHANNEL 14 AND DRAIN 10, 12 ARE MADE IN THE MESA STRUCTURE WITH VERTICAL CONFIGURATION, HAS A FIELD PLATE 26 AT THE SURFACE OF THE MESA STRUCTURE AS WELL AS IN THE REGION WITHDRAWAL THAT SURROUND THIS STRUCTURE. IN ADDITION, A LOAD LIMITATION RING 30 IS PLACED IN THE RETREAT REGION, LOCATED A DISTANCE FROM THE FIELD PLATE, AND IN CONTACT WITH THE TRANSISTOR DRAIN REGION. APPLICATION TO THE MANUFACTURE OF POWER TRANSISTORS.

Description

2487 128

  The present invention relates generally to semiconductor devices and their technology and

  more particularly relates to power transistors.

  Planar structure field effect transistors, particularly metal-oxide-silicon (MOS) field effect transistors, are used in high integration level networks and in discrete power devices. These devices, however, have a limitation for power applications, which lies in the high area they require. The use of vertically aligned grooved structures has led to an improvement of the power transistors. Thanks to the V-groove formed by preferential attack of the semiconductor material, the field effect transistor

  can be built vertically, instead of being

  This leads to a shorter channel length and lower resistance between source and

the drain, in the conductive state.

  U.S. Patent 4,219,835 discloses a structure V-shaped power field effect transistor.

  mesa. In this structure, an insulating layer is provided

  on a surface of the device and on the side walls

  of the mesa structure, with a layer of metal on the insulating layer to form a field electrode or

  a source field plate. This mesa structure originates

  nale, in which the source field plate covers the PN junctions of the mesa structure, provides an improved breakdown voltage, with a channel resistance having

  correspondingly a low value.

  The object of the invention is to produce a transistor

  of improved mesa-type power.

  Another object of the invention is to provide a V-groove field effect transistor and a structure

  mesa having an improved electrode configuration.

  Another object of the invention is to provide a method for producing the electrode configuration

  of a power transistor making it possible to obtain a voltage

  higher breakdown voltage with channel resistance

weaker.

  In summary, in accordance with the invention, a device

  A power transistor such as a diode or transistor is formed in a semiconductor body having a mesa structure defined on a major surface of the body. The active regions of the power device are defined in the mesa structure and an insulating material is placed on the upper surface of the mesa structure and extends to the main surface of the semiconductor body. A first conductive material passes through the insulating material to contact the semiconductor body and surrounds the mesa structure, thereby establishing a ring limiting

  charges on the surface of the device and maintains the stability

  the breakdown voltage of the power device.

  In a preferred embodiment, the device

  The power tif is a grooved vertical type field effect transistor in which the source and channel regions are formed in the mesa structure while the substrate forms the drain. The charge-limiting ring contacts the substrate and the drain region to resist the accumulation of charges on the surface of the substrate. There may be a field electrode in electrical contact with the source regions and

of channel.

  The invention will be better understood when reading

  the following description of an embodiment

  given by way of non-limiting example. Following the

  description refers to the accompanying drawings in which

  Figure 1 is a section of a grooved field effect transistor according to an embodiment of the invention; FIG. 2 is a view from above of the field effect transistor of FIG. 1; Figure 3 is a sectional view of the transistor of Figure 1 and shows the equipotential lines in the device; and Figures 4A-4I are cross-sections illustrating

  the manufacturing steps of the device of FIG.

  We will now consider the drawings in which Figure 1 is a section of a transistor of

  power corresponding to an embodiment of the invention

  and Figure 2 is a top view of the device. It should be noted that the figures are only intended to illustrate the invention and are not drawn to scale. In this embodiment, the power transistor consists of a grooved mesa type field effect transistor, similar to the structure described in US Pat. No. 4,219,835. The device comprises an N + type substrate and a layer. N-type epitaxial region 12. A P-type region 14, formed by ion implantation or doped epitaxial growth, is established on the N-type region 12 and a heavily doped N + type region 16 is established on the N-type region. P. The region 16 of

  N + type can be formed by selective diffusion of impure-

  in the P-type region 14, as will be described in more detail below, or

  other classical techniques to form this region.

  A groove generally designated 18 is formed in the structure and passes through the N + type region 16 and the P type region 14 to enter the N-type region 12. Silicon oxide 20 is formed on the surface of the groove 18 and a conductive material 22,

  such as aluminum or polycrystalline silicon

  The doped tallin is formed on the silicon oxide 20 and forms the gate electrode of the field effect transistor. Region 16 acts as a source, regions and 12 act as a drain, and P-type region 14, between the source and the drain, constitutes the region of

  channel which is controlled by the gate electrode 22.

  Silicon oxide 24 is formed on the sides of the mesa structure while a conductive pattern 26, for making electrical contacts, is

  formed on silicon oxide and made an ohm contact

  that with the source region 16 and the channel region 14,

  as he is represented. The part of the conductive

  trice 26 that goes down to the side of the mesa shape structure

a source field plate.

  For switching high voltages and currents, such a field effect transistor structure

  preferably offers low resistance to the conductive

  a high switching speed and a high breakdown voltage. The weak resistance is obtained by the vertical structure. However, obtaining a high breakdown voltage has an adverse effect on the resistance

  from the transistor to the conductive state.

  The invention provides a technique for producing the electrode configuration which is intended to increase the breakdown voltage and to limit the spreading of the surface charges, thus ensuring the stability and reliability of the

  device. As it is represented in the mode of

  of FIGS. 1 and 2, a conductive layer 30 is

  placed on the structure and this layer surrounds the

  tor to gorgeset comes into contact with the drain region at 32. Thus, the ring 30 is brought to a voltage equal to the drain voltage, which prevents the accumulation of charges in the silicon oxide that covers the structure . A

  silicon oxide layer 34 covers the device.

  FIG. 3 is a section of the structure, similar to FIG.

  Figure 1, and shows equipotential lines

  36 in the drain-substrate region during operation

  the device. Thanks to the mesa structure and the

  figuration of electrodes, equipotential lines have

  a regular and relatively rectilinear shape, without

  sudden changes in the vicinity of the border between the

  substrate and silicon oxide. Equipotential lines

  they extend inside the silicon oxide between the field plate 26 and the load limiting ring

as he is represented.

  The device shown in FIG. 1 can be easily manufactured using conventional semiconductor device manufacturing techniques, such as

  those described in U.S. Patent 4,219,835.

  FIGS. 4A-4I show the steps

  manufacturing device. It should be noted that this description

  tion shows only one example of a succession of manufacturing steps of the device and that could be used

  other conventional processes within the scope of the invention.

  FIG. 4A shows the N + type substrate 40 (0.007-0.05 ohm.cm for example). Figure 4B shows the N-type epitaxial layer 42 (5-8 ohm cm, for example) grown on the substrate 40, and Figure 4C shows the P-type region 44 formed on the epitaxial layer. N-type 42 by ion implantation (1013 ions / cm3 for example), through the oxide layer 43. According to one variant, a P-type epitaxial layer can be grown on the N-type epitaxial layer 42. FIG. 4D shows a diffusion window 47 which is formed by etching through the layer 43 and an N + type region 48 (1019atoms / cm3 for example) which is formed by diffusion of an impurity through the window 47. Then, as as shown in FIG. 4E, a new layer of silicon oxide 50 is formed by thermal growth on the surface of region 48; and we form the

  window 52 and windows 54 in silicon oxide.

  As shown in FIG. 4F, a selective etching agent is then applied to the semiconductor body through the windows 52 and 54, and the grooves 56, 58 and 60 are formed by an attack which passes through the P region to come into operation.

  contact with the N-type epitaxial layer 42.

  As shown in FIG. 4G, a thin layer of oxide 62 is formed on the surface of grooves 56, 58 and 60. Polycrystalline silicon 66 is then formed on the silicon oxide and the polycrystalline silicon is selectively removed unless on the gate oxide. As shown in FIG. 4H, an additional deposition of silicon oxide is carried out. Apertures are etched through silicon oxide to expose source regions

  48 and channel 44 and the N-type epitaxial layer 42.

  A conductive material, such as aluminum, is then applied to the silicon oxide layer and selectively etched to form the source field plate 68 in contact with the source and channel regions. and the load limiting ring 70, in contact with the layer 42. Finally, as shown in FIG.

  4I, an insulation layer is formed on the surface of the device.

  a thicker fraction, 74, consisting for example of

silicon deposited in the vapor phase.

  By using the charge limiting ring 70, having recessed portions, in combination with the source field plate 68 in the recessed regions 56 and 60 surrounding the transistor structure, an electrode configuration is obtained for the device that allows switching at higher voltage and higher current. Note that the described embodiment is only one example and should not be considered as limiting. For example, other diodes and

  power transistors of the mesa type, including arrangements

  bipolar devices and vertical-type DMOS devices.

  The charge limiting ring 70 can be placed directly on the semiconductor material, without the oxide of

  underlying silicon. The choice of a particular configuration

  device can be determined by the compatibility with the manufacturing process used to achieve the

transistor structure.

  It goes without saying that many modifications

  can be made to the device described and shown, -

  without departing from the scope of the invention.

Claims (9)

  A power device comprising a semiconductor body (10, 12) having a main surface, a mesa structure on said main surface, at least one PN junction located in the mesa structure and defining an active region of the power device, characterized in that it comprises a first conductive material (30) which is disposed on the main surface, surrounds the   mesa structure and comes into contact with the semicon- ducer.   2. Power device according to the claim   1, characterized in that it further comprises an insulating material (24) located on the main surface and surrounding the mesa structure, and in that the first material   conductor (30) covers this insulating material.   3. Power device according to one -   Claims 1 and 2, characterized in that it comprises   a groove (18) formed in the mesa structure, and the   P-N junction junctions define the source (16), channel (14) and drain (10, 12) regions of a transistor field effect.   Power device according to claim 3, further comprising insulating material (24) on the mesa structure, characterized in that it comprises a second conductive material (26) in contact with the source regions (16) and channel (14) and covering the insulating material (24) on the mesa structure, the second conductive material (26) being spaced from the   first conductive material (30).   A vertical type field effect power transistor comprising a semiconductor body (10, 12) of a first conductivity type and having a main surface, a mesa structure on that main surface, a first region (14) in the mesa structure which is of a type of opposite conductivity and defines a region of   channel, a second region (16) of the first type of   which defines a source region in the first region (14), a groove (18) in the mesa structure that extends through the first and second regions, a first insulating material (20) formed on the surface of that groove (18), a first conductive material (22) formed on the first insulating material (20) and defining a gate electrode, a second insulating material (24) on the surface of the mesa structure, a second conductive material (26). on the second insulating material, this second conductive material coming into contact with the second region (16) and defining a source contact, characterized in that it comprises a third material   conductor (30) which is in contact with the semicon-   driver (10, 12), which surrounds the mesa structure and   defines a load limiting ring.   6. Power transistor according to claim, characterized in that it further comprises a third   insulation material located on the main surface   mesa structure, and the third conductive layer   (30) covers this third insulating material.   7. Power transistor according to one   claims 5 and 6, characterized in that the second   insulating material (24) and the second conductive layer (26) descend to the side of the mesa structure and cover part of the main surface, the second layer   conductor constituting a field plate.   8. Power transistor according to claim 7, characterized in that the semiconductor body (10, 12) is made of silicon and the first insulating material (20), the   second insulating material (24) and the third insulating material lante are in silicon oxide.   9. Power transistor according to claim 8, characterized in that the first conductive material   (22) consists of doped polycrystalline silicon.