DE3128035A1 - POWER TRANSISTOR - Google Patents

Description

DIPL.-ING. J. RICHTER -'- - ": P Α.ΤΈ.Ν TANWALTE D1PL.-1NG. F. WERDERMANN

ZUSEL. REPRESENTATIVE AT THE EPO · PROFESSIONAL REPRESENTATIVES Bl FORE LPO · MANDATAIRES AGREES PRES U'OEB

SOOO HAMBURG 36 t 5. 7 t

NEW WALL

■ g- (O 4O) 34 OO 43/34 OO

TELEGRAMS: INVENTIUS HAMBURG

TELEX 2163 551 INTU D

OUR CHARACTERISTICS / OUR FILE ^ · 1 ^) Uc. "!" OIcT ^

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PATENT APPLICATION

PRIORITY: July 21, 1989

(corresponds to U.S. Serial No. 170 564)

DESIGNATION: Power transistor.

APPLICANT: SILICONIX INCORPORATED

Laurelwood Road Santa Clara, Caliph. V.St.A.

INVENTOR: 1. Steeve Teong Sin Kay

Mxddleborough Court San Jose, Caliph. 95132 V.St.A.

2. Eng Tsan Gaw

Sierra Road

San Jose, Caliph. 95132

V.St.A.

J Ί '/. Ö U ό b

The invention relates generally to semiconductor devices and their technology and, in particular, mainly on power transistors with a semiconductor body, in particular those with a mesa structure, on one side of which is flat and at least one P-N junction in it, which is the active zone of the power transistor forms.

Field effect transistors, in particular metal oxide silicon field effect transistors (MGSFET) have in highly integrated circuits, but also in discrete arrangements for high performance Application found. However, one limitation of their application in high power devices is that for such devices require a large surface on the flat side. An improvement in power transistors resulted from the use of vertically aligned, grooved structures. By training with a V-groove, which is preferably is formed by etching semiconductor material, the field effect transistor may have a vertical structure instead of a lateral structure, with a shorter channel length and results in a lower resistance between the source and drain regions.

US Pat ^{. No. 1} J 219 835 describes a field effect power transistor with a mesa structure with a V-groove. With this one

Structure, an insulating layer is provided on a flat side of the device and on the side walls of the mesa, wherein a metal layer is arranged on the insulating layer in order to form a field electrode or Sourcofeid plate. This unique mesa structure with the source field plate, which lies above the P-N junctions of the mesa results in an improved breakdown voltage with a correspondingly low channel resistance.

The invention is based on the object of improving a transistor of the type in question with a mesa structure in that that the mesa structure receives an improved boundary that has an even higher breakdown voltage with even allows lower channel resistance.

This object is achieved according to the invention by what is stated in the claim specified features of a power transistor solved. Possibilities for advantageous further refinement are given in claims 2 to 9 specified.

According to the invention, a power transistor or but also created a power diode with a semiconductor body, on one flat side of which a mesa structure is formed is. The active zones of this device capable of guiding high power are arranged in the mesa structure. One Insulating material layer is attached to the surface of the mesa.

arranges and extends over the flat side of the semiconductor body ·. A first layer of conductive material extends through the insulating material to contact with the semiconductor body and surrounds the mesa structure, thereby creating a charge control ring on the surface of the device that the stability of the breakdown voltage of the Guaranteed power transistor or the power diode.

According to a preferred embodiment, the device is a grooved field effect transistor with a vertical field, the source and channel zones being formed in the mesa structure and the substrate having the drain zone. The charge control ring contacts the substrate and the drain region to inhibit charge build-up on the surface of the substrate. In electrical contact with the source region and the channel region, a field electrode can, standing may be provided.

In the following the invention is illustrated by way of example with reference to the drawing explained in more detail. Show it

1 shows a vertical section of a grooved field effect transistor according to an embodiment of the invention ;

FIG. 2 is a plan view of the field effect transistor according to FIG. 1; ^;

Fig. 3 is a vertical section of the transistor according to Fig. 1 with indication of the equipotential field lines and

FIGS. ^4a-1H are sectional views illustrating
the production of the structure of a device according to FIG. 1.

Fig. 1 shows an embodiment of the invention
Power transistor and FIG. 2 its plan view. It
are schematic representations that are used to
Explanation are intended to serve and are not to be understood to be true to scale. The power transistor of this embodiment is a grooved field effect transistor with a mesa structure similar to the structure of that of US Pat. No. 4,219,835. The device comprises an N -type substrate 10 and an N-type epitaxial layer. A P-zone 14 created by ion implantation
or is formed by doped epitaxial growth is located above the N ~ zone 12, and a heavily doped N zone 16 is formed in the P zone Ik . The N zone 16 can be formed into the P zone 14 by selective diffusion of foreign matter
be prepared as further described below or other known methods can be used to form this zone. A groove designated by 18, which is formed in the structure, extends through the N zone 16 and the P zone 14 into the N ~ zone 12. On the surface of the
A silicon oxide layer 20 is formed in groove 18. Above is a layer of a conductive material 22 such as
Aluminum or doped polycrystalline silicon, which forms the gate electrode of the field effect transistor,

Λ *

its area l6 as the source and its areas 10 and 12 act as a drain, while the P-zone IiJ between source and Drain forms the channel zone, which is formed by the gate electrode 22 is controlled.

Silicon oxide material 2k is applied over the sidewalls of the mesa j with an electrical contact and line pattern over the silicon oxide and in ohmic contact with the source zone 16 and the channel zone Ik. The portion of conductive material 26 that extends down the sidewalls of the mesa structure forms a source field plate (SFP).

To switch high voltages and currents, such a field effect transistor structure should above all have a low switch-on resistance, have a high switching speed and a high breakdown voltage. The low resistance is through the vertical structure is achieved, but the on-resistance is created by creating a high breakdown voltage of the transistor impaired.

According to the invention, a demarcation scheme is created to ' to increase the breakdown voltage and the spread of the Control surface charge in order to achieve stability in this way and to ensure device reliability. As in Shown in the embodiments of Figures 1 and 2 is a conductive one Layer 30 is provided on the structure, which the grooved

Surrounds transistor and touches the drain region at 32. Thus, ring 30 has a voltage equal to the drain voltage _s thereby preventing charge build-up in the silicon oxide material overlying the structure. A silicon oxide layer 3 ^ covers the device.

Cut to Pig. 3 _S which of those of Pig. I, the equipotential lines 36 are shown within the drain-substrate region during operation of the device. Because the mesa structure and the boundary are created, the equipotential lines run smoothly and relatively flat without abrupt changes in the vicinity of the interface between substrate and silicon oxide. The equipotential lines extend through the silicon oxide between the field plate 26 and the charge control ring 30, as can be seen from FIG. 3.

The device shown in Fig. 1 is easy to manufacture conventional semiconductor technology can be used as described in U.S. Pat. U.S. Patent 4,219,835. The steps of the manufacturing process are illustrated by the sectional views of Fig. *) A to 41 explained. This description however, it is intended only to illustrate a sequence of steps in the manufacture of the device rather than it Other methods of practicing the invention can also be used.

3 (28035

According to FIG. 4A, the N substrate 40 (for example 0.007 to 0.05 ohm cm) is assumed. Referring to FIG. 4B, the N-type epitaxial layer 42 (e.g., 5 to 8 ohm cm) is grown on the substrate 40, and as shown in FIG 10 ions per cm ³ ) formed through the oxide layer 43. Alternatively, a P-type epitaxial layer may be grown on top of the N-type epitaxial layer 42 instead.

According to FIG. 4D, a diffusion window 4? through the shift

+ IQ

etched through and an N zone 48 (for example 10 ^y atoms per cm ³ ) is formed by the diffusion of the dopant through the window 47.

Thereafter, as shown in FIG. 4E, a new layer of silicon oxide is thermally drawn on the surface of zone 48; furthermore, windows 52 and 54 are formed through the silicon oxide. As illustrated in FIG. 4F, an etchant, which is preferably to be used, is then brought to act on the semiconductor body through the windows 52 and 54, and the grooves 56, 58 and 60 are made through the P-zone until they come into contact with the epitaxial N ~ - Zone 42 etched.

As shown in Fig. 46, a thin oxide layer 62 is formed on the Surface of the grooves 56, 58 and 60 formed. Then doping

is

tes polysilicon 66 is formed on the silicon oxad and selectively removed except above the gate oxide. As in As shown in Figure 4H, additional silicon oxide is deposited. Openings are etched through the silicon oxide, around the source zone 48 and the channel zone 44 as well as the epitaxial zone N zone 42 to be exposed. Conductive material such as aluminum is then deposited over the silicon oxide layer and selectively etched around the source and field plates 68 in contact with the source and channel regions and the charge control ring 70 to form in contact with zone 42. Finally, as shown in FIG. 4l, a thicker insulating layer 74 is used, for example applied by vapor deposition of silicon oxide over the surface of the device.

By using the recessed charge control ring 70 in conjunction with the source field plate 68 in the recessed areas 56 and 60, which form the transistor structure surround, a limitation of the device is provided, which enables the switching of higher voltages and currents. The possibilities for using and carrying out the invention are not limited to those described in detail here and examples shown. For example, other mesa construction power diodes and transistors may also be included bipolar and vertical DMOS can be produced according to the principle of the invention. The charge control ring 70 can directly can be applied to the semiconductor material without it

of the underlying silicon oxide. The special one Selection of the design of the device can be made depending on the compatibility with the manufacturing process in the construction the transistor structure can be determined.

Claims (9)

DI PL, -I NG. J. R ICHTER - 'P Ä.T "E..3M TANWALTE DIPL.- ING. F. WERDERMANN REINS. REPRESENTATIVE AT THE EPO · PROFESSIONAL REPRESENTATIVES EJtFORE EPO · MANDATAIRES AGREES PRiS L ¹ OEB 2000 HAMBURG 36 15.'7 · NEW WALL 1O "JS- (O4O) 34-45 / 34-56 TELEGRAMS: INVENTIUS HAMBURG TELEX 2163 551 INTU D U _NSER ZB, CH _EN , O _UR F ₁ LB S .4502-1-812 ^ 3 Wdm / le Patents η s ρ rt i ehe flj power transistor with a semiconductor body and a mesa structure on one flat side and at least one PN junction in this, which forms the active zone of the power transistor , characterized in that a first layer of conductive material is attached to the same flat side which surrounds the mesa structure and touches the semiconductor body. 2. Power transistor according to claim 1, characterized by a layer of insulating material on the same flat side of the semiconductor body j which surrounds the mesa structure and is superimposed by the mentioned first layer of the conductive material is. 3 »Power transistor according to claim 1 or 2, characterized in that a groove is formed in the mesa structure and the PN junctions form source, channel and drain zones of a field effect transistor. k. The power transistor according to claim 3 with an additional insulating material layer on the mesa structure, characterized in that a second layer of conductive material is in contact with the source and the channel zone and the insulating material layer is superimposed on the mesa structure, the second layer of conductive material being in one Distance from the first layer of conductive material. 5. Power transistor according to one of claims 1 to 4 with a vertical field, which has a semiconductor body of a specific first conductivity type with a flat side, on which there is a mesa structure in which a first zone of the opposite conductivity type is provided which forms a channel zone and in which a second zone of the first conductivity type is provided, which is a source zone forms within the first zone with a groove in the mesa structure extending through the first and second zones, and a first layer of insulating material is formed over the groove surface, and a first layer of conductive material is over the first insulating material layer and a gate electrode forms, and a second insulating material layer lies over the surface of the mesa structure, over which a second Layer of conductive material is located, which is in contact with the second zone and forms a source contact, characterized in that a third layer of conductive material is in contact with the semiconductor body, .den Surrounds mesa structure and forms a charge control ring. 6. Power transistor according to claim 5> characterized in that a third insulating material layer is located on the same flat side and surrounds the mesa structure, and that the third layer of conductive material lies over the third layer of insulating material. 7- power transistor according to claim 5 or 6, characterized characterized in that the second layer of insulating material and the second layer of conductive material extend down from the mesa and extending over part of the planar flat face and that the second layer of conductive material is a field plate forms. 8. Power transistor according to claim 7, characterized in that the semiconductor body consists of silicon and that the first insulating material layer, the second insulating material layer and the third insulating material layer are made of silicon oxide. 9. Power transistor according to claim 8, characterized in that that the first layer of conductive material comprises doped polysilicon.