GB2076266A - Adaptive equalizer - Google Patents

Abstract

An automatic adaptive equalizer operates on a test pattern including a carrier-only period, a clock-only period and a single test impulse. The equalizer employs a transversal a filter under control of a microprocessor 23. Samples Xi and Yi of in- phase and quadrature phase components of the received impulse response are cross-correlated and auto-correlated to form elements of a complex matrix equation describing the optimum equalizer tap settings Cp1 and Cq1 etc. The microprocessor performs a special iterative operation utilizing elements of this equation to rapidly and exactly calculate the optimum initial settings for the tap constants. The clock- only portion of the test pattern is analyzed to set a sampling clock to sample the received impulse so that the tap constant calculation can be carried out within the duration of the received impulse. Initial equalization can be achieved in a time of about 30 milliseconds at a data rate of 9600 bits per second. <IMAGE>

Description

1

GB2 076 266A

1

SPECIFICATION Adaptive equalizer

5 The present invention relates to data communication channel equalizers and more particularly to 5 * automatic adaptive equalizers such as are utilized in high speed data modems. The equalizer is particularly adapted to implementation under microprocessor control and can provide a highly accurate, ultra-fast equalization by operation on the channel response to only a single 1 transmitted test impulse.

10 The equalizer of the invention is thus particularly suited to high speed polling applications. In 10 such applications, it is customary to address a number of remote stations in rapid succession, for example in different cities, from a central site. Transmission to each remote station involves a new transmission line such that equalization must be re-established each time a new remote site is polled. Therefore, it is highly desirable to shorten the equalization time as much as possible in 15 order increase data throughput. 15

Many prior art equalizers have been relatively slow to equalize when first connected to a new transmission line and have thus wasted valuable data throughput time. Typically, many time consuming incremental adjustments of the equalizer taps are required during analysis of a relatively long period of random data or a training pattern containing numerous test pulses. 20 One prior art system proposes to equalize on a single transmitted test pulse but actually 20

requires a multiplicity of test pulses. This system is disclosed in the Bell System Technical Journal, Vol. 50. No. 6 pp. 1969-2041, in an article by Robert W. Chang titled "A new Equalizer Structure for Fast Start Up Digital Communications."

Another prior art system achieves equalization during the duration of the response to two 25 transmitted impulses utilizing a technique which approximates the well-known zero-forcing 25

scheme and does not employ correlation of signal samples. Equalization in this system requires an extra impulse to adjust the phase of the line signal so that proper sampling will occur.

Because this system uses a zero-forcing scheme and then only an approximation thereto, it will not work on a highly distorted line or when high precision is necessary. While this prior system 30 suggests itself for operation at 4800 bps, it is not suitable for operation at the much higher data 30 rate of 9600 bps at which the equalizer of the subject invention can operate.

In IEEE Transactions On Communications, Vol. Com-23, No. 6, June 1975, P. Butler et al disclose a method permitting a direct solution of a matrix equation in real variables describing the settings of equalizer tap constrants in a single sideband system. This technique requires a 35 much longer training sequence to reach an estimation of reasonable accuracy than that 35

proposed by the subject invention. Moreover, the method will not solve a complex variable matrix equation. Accordingly, the approach cannot be used to achieve equalization in a double sideband system as will the subject invention.

It is therefore an object of the invention to provide a faster operating and more accurate 40 equalizer for data transmission systems. 40

It is another object of the invention to provide a practical equalizer which requires analysis of only a single transmitted impulse to initially set the equalizer taps for a wide range of varying line distortions and data rates.

According to the present invention there is provided an adaptive equalizer as defined in claim 45 1 below. 45

The equalizer tap constants can be calculated exactly, rather than by using approximations.

Such an exact calculation can be achieved by an iterative technique which is performed during the time when a transmitted impulse response is being received such that the equalizer tap constants are calculated and set during the interval between the end of the impulse time and the 50 time when the first received data reaches the major tap of the equalizer. 50

An equalizer embodying the invention can achieve a precise initial setting within a very fast time, such as 30 milliseconds for a data rate of 9600 bps and 15-20 milliseconds for a data rate of 4800 bps. The initial equalizer settings compensate fully and completely for distortion in the communication medium over which the training signal was transmitted. After initial setting 55 with the equalizer according to this invention, more conventional adaptive equalization can occur 55 during reception of data.

The equalizer according to the invention has the major advantage of enabling precise equalization constant calculations from the samples in a time of the order of the duration of a single received impulse despite wide variations in the distortion induced by the medium over 60 which the received impulse is transmitted. Utilizing the invention, an equalizer has been 60

constructed which can achieve initial equalization of about 30 milliseconds at a data rate of 9600 bits per second. This is nearly five times faster than equalization can be achieved by systems which are at present commercially available. In the preferred embodiment of the invention, equalization is performed in response to a single received impulse, and an important 65 feature of the preferred embodiment is provision of a means to determine the optimum points at 65

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GB2 076 266A 2

which to sample the impulse response prior to receiving it. While equalization is performed using in-phase and quadrature phase impulse response signals at baseband frequencies in the preferred embodiment, such signals may be derived at passband or other translated frequencies. The invention will be described in more detail, by way of example, with reference to the 5 accompanying drawings, in which: f 5

Figure 1A illustrates the received signal utilized by the equalizer of the preferred embodiment. Figure 1B and 1C illustrate quadrature phase components produced from the received signal on the same time scale as Fig. 1A.

Figure 2 is a schematic diagram useful in illustrating the structure and operation of the 10 equalizer of the preferred embodiment. 10

Figure 3 is a schematic diagram illustrating the digital processor utilized in the preferred embodiment of the invention.

This application is one of four applications, all divided out of our application 791 3018 (Serial No 2022376). All five applications are concerned with features of the equalizer now to be 1 5 described and the numbers of the other divisional applications are as follows: 1 5

Application No Serial No

8118512

8118513

20 8118514 20

Figure 4 is a flow diagram illustrating the overall structure and operation utilized to properly time the sampling of the received signal in the preferred embodiment.

Figure 5 is a detailed flow diagram illustrating the method and apparatus utilized to detect the 25 presence of the received signal in the preferred embodiment. 25

Figure 6 is a detailed flow diagram illustrating the method and apparatus employed in the preferred embodiment to properly set the points for sampling the received signal.

Figure 7 is a detailed flow diagram illustrating the method and apparatus employed in the preferred embodiment to determine the equalizer tap constant settings from the samples of the 30 received signal. 30

Figure 8 is a continuation of the flow of Fig. 7.

Figure 9 illustrates one technique suitable for generating phase quadrature signals for use in the subject invention.

Figure 10 illustrates an alternative technique for generating phase quadrature signals for use 35 in the subject invention. 35

Figure 11 illustrates an alternative technique for generating phase quadrature signals for use in the subject invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 40 The automatic adaptive equalizer of the invention may be conveniently introduced in 40

conjunction with the training pattern utilized to set up automatic gain control, timing and equalization, as shown in Fig. 1. The training pattern of Fig. 1 is the analog demodulated pattern at the receiver after transmission. The system of the preferred embodiment is particularly directed to the quadrature amplitude modulation (QAM) technique.

45 The training pattern includes in succession a number of bauds of carrier-only 11, a number of 45 bauds of clock-only 13, a quiet or squelch period 1 5, a received impulse 1 7, and another squelch period 19. The training pattern may also include an optional fine tuning sequence before the transmission of customer data 20.

In the preferred embodiment, eight bauds of carrier-only 11 and seventeen bauds of clock-50 only 13 are sent. The squelch periods 15, 19 are twenty-seven and twenty-one bauds long, " 50 respectively, and the impulse period is one baud long. Each baud period is 416.7 microseconds. Of course, other baud periods could be utilized. Also, the length of the periods 11, 17, 15 and 19 depend on the maximum distortion. When the line distortion is less, less bauds are required for each one of them, especially for periods 17,15 and 19, and the total time for tuning will be 55 shorter. When the line distortion is severe, more bauds are required for each period, and the 55 total tuning time will be longer.

During the carrier-only period 1 3 in Fig. 1, the initial incidence of carrier energy on the line is detected (carrier detect), starting system operation. When carrier detect occurs, a rough timing counter KSTMX is started, which ultimately anticipates the occurrence of the impulse response 60 17. KSTMX counts once per baud. 60

Automatic gain control is then performed on the carrier-only signal 11. After a fixed number of bauds of carrier-only 11 are detected, the system knows it is actually receiving a training pattern and can then expect the clock-only signal 1 3.

During the clock-only pattern 13, the apparatus examines the transmitted pattern to determine 65 the optimum points to sample the forthcoming impulse response 1 7. The apparatus then sets up 65

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GB2 076 266A 3

for the impulse response sampling procedure. The first step is to use the sampling point previously calculated to jump or preset the sampling clock to the optimum sampling position. It may thus be seen that the preferred embodiment actually samples the response to a transmitted impulse although other means for generating signals representative of such samples could be 5. employed. 5

During the squelch period 1 5, the rough timing counter KSTMX, which was set-up upon detection of carrier-only, continues to count to subsequently indicate to the apparatus the point in time at which to start to sample the in-phase and quadrature phase impulse responses 17 (Fig. 1B, 1C). The samples are then taken, stored and correlated for forming a matrix. After the 10 matrix is formed a special iterative technique is utilized to determine the precise initial equalizer 10 tap settings, as discussed further below.

The apparatus employed to perform these operations is illustrated conceptually in block form in Fig. 2. The apparatus includes an analog to digital (A/D) converter and automatic gain control (AGC) section 21, a digital processor 23, and a transversal equalizer 28. The equalizer 15 28 is shown conceptually for purposes of illustration and is preferably implemented digitally, in 15 which case it could also be shown as part of the digital processor 23.

Digital demodulation of the QAM signal into in-phase (X) and quadrature phase (Y) base band components, is preferably accomplished in the digital processor 23. The analog form of the demodulated in-phase and quadrature phase baseband components is illustrated in Figures 1 B 20 and 1C, respectively. Demodulation again may be performed by well-known techniques and may 20 optionally be performed by dedicated apparatus outside the digital processor 23. Neither the AGC or demodulation technique used form a part of the subject invention.

The X and Y phase components produced by demodulation represent samples in digital form of the baseband signal, the Y component sample being demodulated by a carrier 90° out of 25 phase from the carrier demodulating the X component sample. In order to calculate the proper 25 sampling time during the clock-only period, two samples per baud are taken in the preferred embodiment. After the optimum clock phase is set, the system takes one sample per baud.

These samples X, Y are sent to separate channels 25, 27 of the transversal equalizer 28. Each channel 25, 27 includes equally spaced digital delay elements 29, 31 and digital multipliers 30 30, 32, 33, 35 as known in the prior art. The multipliers 32, 33 multiply the delayed samples 30 Xm by constants cp; and cqj while the multipliers 30, 35 multiply the delayed samples Ym by constants cpi and cq,. The outputs of each set of multipliers 30, 32, 33, 35 are summed by respective summers 40, 42, 44, 46 and fed to an adder 36. The output of one summer 46 is subtracted from that of the other 42 in a summer 37 to give the output data signal EQX. The 35 outputs of the other two summers 40, 44 are summed by a summer 36 to give the output data 35 signal EQY.

As shown in more detail in Fig. 3, the preferred embodiment of the invention includes a programmed microprocessor structure and an equalizer unit. The equalizer unit 34 includes the functions of the equalizer 28 of Fig. 2 and performs steady state adaptive equalization, for 40 example as taught in our U.S. Patent 4,035,625. In the preferred structure of the present 40

invention, the equalizer unit 34 also contains some circuitry for accomplishing the initial equalizer setting, as will be further detailed below.

The microprocessor structure of Fig. 3 is conventional, and includes a program store 16, a program counter 18, for addressing the program store 16, a command decoder 14 for decoding 45 instructions from the program store 1 6 to produce control signals and an arithmetic unit 22 for 45 performing the instructions in response to the control signals from the decoder 14. The microprocessor structure also includes a data storage memory 26 and an address decoder 24 for addressing the memory. The program store 1 6 is a conventional read only memory (ROM) of * sufficient capacity to store the instructions for performing the equalizer operations to be 50 described below and may be constructed from four AMD 9216 ROM chips. The program 50

counter 18 is a conventional counter which can be loaded or jumped as necessary in response » to control signals from the command decoder 20. The arithmetic unit 22 is also conventional in structure and of sufficient power to carry out necessary operations as hereafter described. The data storage memory 26 includes storage for constants and 256 words of random access 55 memory and may be configured from three AM91L12ADC RAM chips and one General 55

Instrument R03-5120 chip. The random access storage is used to store incoming samples of the impulse response 1 7 and subsequent data 20 while calculations are underway.

The apparatus of Fig. 3 just described performs rapid initial equalization by calculating the initial equalizer tap multiplier constants in very rapid fashion. The manner of this calculation and 60 the function and structure of the apparatus of Fig. 3 will now be explained in detail. 60

The multiplier constants to be calculated are labeled cp1, cp2, cp3... cpi and cql, cq2, cq3,.. cqi (see Fig. 2).

In complex form the equalizer tap constants may be expressed as:

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GB2 076 266A

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Cj = cpi + jcq[ ,i = 1, 2, 3 n

To calculate the equalizer constants C; from the pair of demodulated impulse responses as shown 5 in Fig. 1B and 1C, the following definitions are adopted:

rT = SH(X2 + Y2)

° m=l m 111

(1)

1 o ^ = £

M_1 + Ym W + ^

m=l in—1

Y X .,)

m nW-1

(2)

10

rT2 = T.K'2 (X„Xm m=l

+ YmYn+,) + j ZM;2(XmY„ m=0L

- VA(3)

15

"n-l " EH"n+1(XX H- V Y . + j _ - m ia+n-i m m+n-i J

15

20

The following elements are defined:

X,

ht =

n — q — k jvn_q_

q-k k = 1,2.. n rTn

(5)

20

25

rT:

i = 1,2 .. n — 1

rT0

(6)

25

In the above equations (1)-(6), Xm and Ym are the m th sample of the inphase and quadrature 30 phase of the impulse response used for calculating the autocorrelation and cross correlation. 30 Equations, (2), (3), (4) represent the autocorrelation and cross-correlation of the samples Xm and Ym.

In the above equations 1-6, M is the total number of samples used for calculating the autocorrelation and cross-correlation and n is equal to the number of taps, twenty for M and sixteen 35 for n in the preferred embodiment, and q equals the subscript of the first sample actually used 35 to calculate hk. The variable q accounts for the fact that in the preferred embodiment not all samples taken are used, in other words n is less than M as later explained in detail. If n equals M, q = 1.

With these definitions, the equations defining the optimum tap constants cu c2,... cn for an 40 equalizer of n taps is written as follows in matrix form: 40

45

50

ri 1

r i • n-l rn-l r*

n-2

n-3 r n-4

1 r*

c n

(7)

45

50

55 In equation (7), r, .... r, and h, ... hn are complex constants while c,... cn are complex 55

variables. The asterisk (*) indicates the complex conjugate form.

According to the invention, a special solution of this equation (7) permits a precise iterative calculation of the tap constants c, .. . c, within the time interval required by the training scheme of Fig. 1 plus the time relay required for data to propagate between the input and output of the 60 equalizer. According to this solution, the following definitions are made: 60

ei=1-|ri|2 (8)

Where |r,| represents the magnitude of the complex quantity r,;

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GB2 076 266A 5

5-

s,(1> = - r, (9)

Where superscript "(1)" indicates the first iteration i = 1; and

5

ct<1> = h, (10)

i Adapting these definitions, the exact iterative solution for the tap constants is as follows:

'"•r - °.a''!-««»'v 10

•i«" -• • W «V

15 ■>"*" - 'A™ 'Ui* 1131 15

aw, ID ,j(« l4Jsl ei+l

= V1" ls(£i I 2> ' <15)

20 zi+1 R 1 (16) 2(3

ei+l

The superscripts again indicate the value of the variable for a particular iteration. These equations 7-16 provide a simple means for rapidly and exactly calculating the tap constants c, 25 in the complex matrix equation (7). This iterative technique enables the apparatus of the 25

invention to calculate the constants c, and set the equalizer to achieve initial equatization during a total training time of approximately 30 milliseconds from the beginning of carrier only to the first bit of customer data in a 2400 baud machine. Variations of the matrix equation (7) may written and solved by the techniques illustrated above without departing from the scope of this 30 invention. 30

The structure and operation of the apparatus of Fig. 3, as it relates to the preferred embodiment of the invention, will now be described in further detail in conjunction with Figs.

4-8.

After the carrier is detected and the clock KSTMS is started, the system operates according to 35 the flow illustrated in the flow chart of Fig. 4. The flow of Fig. 4 illustrates accomplishment of 35 the automatic gain control function, filter, demodulation, the detecting of the training pattern present (TPP) and calculation of the optimum sampling point to be used in the subsequent operations of Fig. 7. Two samples of the carrier-only signal are processed each baud for the eight bauds of carrier-only 1 1. A counter N is set up at — 8 to direct operation.

40 As long as N is less than zero, the left branch 45 of the flow is followed and each sample is 40 subjected to an automatic gain control operation 47, a filter and demodulation operation 49 and the test pattern present detection 51. The test pattern detection checks six successive bauds of carrier-only signal and thereafter sets a flag indicating that a test pattern is in fact being received. Each baud, the counter N is incremented by one, as is the counter KSTMX.

45 When IM equals zero, the clock-only signal 13 begins. AGC is frozen and the right hand 45

branch 53 of the flow of Fig. 4 is entered. In this branch 53, a filter and demodulation operation 55 is performed and a test 57 of the TPP flag is made. Assuming TPP has been detected and the TPP flag set, the fast learn clock operation 59 is performed. During this * operation, denoted FLCLK, the apparatus calculates the optimum sampling point for the 50 forthcoming impulse based on the demodulated clock-only information. After each two samples 50 per baud have been demodulated and used in the FLCLK process, the counter KSTMS is - incremented by one, as is the N counter. When FLCLK is done, the flow proceeds to Fig. 7.

The manner in which the training pattern detection is performed is illustrated in more detail in Fig. 5. Referring to Fig. 5, X and Y samples of the demodulated baseband signal are supplied to 55 the respective input at the rate of two samples per baud. 55

The samples presented to the X input are operated upon as follows. Each sample is first squared by a multiplier 63 and the output of the multiplier 63 is stored for one sample time in a delay element 65. The current output of the multiplier 63 is added to the negative value of the previous output of the multiplier 63 in an adder 67. The output of the adder 67 is supplied as 60 one input to a second adder 69. The X input is also supplied to a second one sample time delay 60 element 71. The output of the second one-sample delay element 71 is supplied to a second multiplier 73, also supplied with the X input, such that the current X input sample is multiplied by the immediately preceding X sample. The output of the second multiplier 73 is fed to one input of a third summer 75.

65 The Y input is similarly operated on. A delay element 77 delays the first sample of the Y input 65

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GB2 076 266A

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and a multiplier 79 multiplies the first sample of the Y input by the delayed sample for supply to the third summer 75. The Y input is also squared and the square Y input value is supplied to a delay element 81. The delay squared sample is subtracted from a present squared sample by a summer 83 whose output is supplied to the second summer 69.

5 The output of the first summer 73 is multiplied by two at a multiplier 85 to form an output * 5 denoted as ACK. The output of the second summer 69 is denoted BCK. The arc tangent of ACK/BCK is then taken to determine the sampling angle 6n. The current value of 6n is stored by a delay element 87. The stored value of 6„ is used in the clock preset to be subsequently «

discussed.

10 It is then determined whether 9n is within bounds for each of a number of counts NTPP. 10

When NTPP is greater than 10, five bauds of samples have been examined. Thus, if \6„ — 90| is less than 1 5 continuously for greater than 10 NTPP counts it is confirmed that carrier has been received for 5 bauds, and the TPP flag is therefore set equal to 1. This operation is illustrated in Fig. 5 by proceeding through blocks 91, 92, 93, to block 94, TPP equals 1. Once 19n — 90| is 15 greater than 1 5 and TPP equals 1, the clock preset routine is entered. 1 5

In the event, however, that \6„ — 90| is greater than 1 5 on any of the carrier-only samples operated on, the test block 95, TPP = 1, will not be satisfied, and NTPP will be reset to zero. In such event, if KSTMX is greater than 1 9, indicating nineteen bauds have occurred without detecting TPP, TPP not present is indicated. Failure to detect TPP normally indicates line 20 dropout. 20

Once the training pattern is detected, it is necessary to properly align the timing of the sampling of the received impulse response 1 7. The sampling points are calculated such that the equalizer can best minimize the output error. The structure and technique used in the preferred embodiment for performing the presetting of the sampling clock (FLCLK) is illustrated in detail in 25 Fig. 6. 25

Assuming no distortion or noise, the difference between successive angles 6„ should be 180°. Therefore, if the magnitude

* = IK-0n-l|-18O°|

30 30

is less than 12° for several successive samples, the clock is in good range. Assuming that 6n is in good range over several sampling intervals of the clock-only pattern, the loop including blocks 101, 102, 103, 104, 105, 106, and 107 in Fig. 6 is operative. Initially, three counters NCNT, NSAMP, and NAV are set to zero. When the first sample is tested, the sampling counter 35 NSAMP is incremented by 1 as indicated by the block 101. The angle $ is then tested, and if it 35 is within range, the counter NCNT is incremented by 1. After four consecutive good samples, the test, NCNT greater than or equal to four (Block 104) is satisfied, and NAV = 0 is satisfied. In this event, the test indicated by block 106 is performed to ascertain whether the magnitude of 6n is less than 90°. If so, a counter NR is set equal to 1. The counter NAV, representing the 40 number to be averaged, is set equal to 1 and TAGL (total angle) is defined as equal to 0n at this 40 moment. The next time around the loop, the test NAV = 0 is not true, and NR is incremented by one at block 108. NR + 1 is then equal to two. NR is then not odd, and another sample is taken. After this sample, assuming <f> is still in bounds, NR is odd (equal to 3). Therefore the number averaged NAV +1=2 and TAGL is equal to the previous 6n value plus the new dn 45 value. Thus there are two angles to be averaged. Assuming that 0n continues to be within 45

bounds, the number of 0„ samples averaged is incremented to 4 and then the angle P9 is determined at block 109 by calculating the quotient of TAGL and NAV. Pfl indicates the number of degrees from which the sampling point being used diverges from the optimum sampling point. Thus, it takes 10 angle differences within bounds to reach the block Pfl = TAGL/NAV. * 50 In the event, however, that distortion is occurring, other provisions are made for calculating 50 Pe. For example, if it occurs that <j> is greater than 12, satisfying block 102, a test 110 is made to determine is the number of good samples counted NCNT is greater than or equal to 4, i.e.

wiehter four inbounds angle tests have occurred. If so, a test 111 is made of the NAV counter to determine whether any samples TAGL have been stored for averaging. If any samples have 55 been stored, the average 0av = TAGL/NAVL is computed as indicated by the four blocks 112, 55 113, 114, 115. These four blocks indicate that P„ is taken as equal to 0av if NR is even,

whereas Pfl is taken as equal to

60 |sgn teav> j [«o--|eav|

60

if NR is odd. If, however, at the test —11, NAV is found to be equal to zero, indicating no samples 0„ have been accumulated, Pe is taken to be the current sample 0n.

65 If the NCNT>4 test 110 is not satisfied, a test 11 7 of the number of samples, indicated by 65

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GB2 076 266A

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counter KSTMX, is made. If that number KSTMX is greater than 29 (>14 bauds), ?e is again taken to be 0n. If NCNT>4 is not satisfied and KSTMX>29 is not satisfied, NCNT is set to zero and another sample is examined. This procedure assures that if the angle determination is initially or occasionally out of bounds, subsequent angles can be examined to average the clock 5. according to the previously discussed procedures. 5

?g then determines the phase shift of the impulse sampling clock to be used in the matrix sampling operation illustrated in Fig. 7.

s In Fig. 7, the first time through, the new program (NP) test 121 is positive and the left branch 1 23 of the flow is followed. Here the equalizer random access memory (RAM) 26 is 10 reset. Also the optimum sampling point determined by FLCLK is used to jump the sampling 10

clock to the optimum sampling position within each baud. The clock rate is reduced in half to 2400 Hz such that one sample per baud of the impulse response is taken from each of the X and-Y channels.

The second time through the flow of Fig. 7, a second branch 125 is followed. Detected 15 samples are demodulated (block 127), and then a test 129 is performed on KSTMX to see if it 15 is greater than 45. If it is not, KSTMX is incremented (block 131). As soon as KSTMX is greater than 45, matrix formation 133 from the sampled impulse 1 7 begins.

The branch followed when KSTMX<45 includes a demodulated output energy test which assures that the system is receiving the equalizer test pattern and not customer data. After 20 KSTMX is greater than 38 the energy is determined as denoted by blocks 1 34, 1 38. If the 20

energy is below a set level Eref, the squelch period is assumed to have been detected and the system knows a training pattern is present. If the energy is greater than Eref, training pattern TPP not present is indicated. This provides a double check on the presence of a training pattern.

Sampling of the impulse wave form 1 7 is illustrated by the vertical lines in Fig. 1 B and 1C. 25 The number of samples is counted by a counter K, started when KSTMX = 45. Each sample 25 produces an X component x, and a Y component y,. As the samples x„ y, are successively taken, formation of the matrix equation (7) according to the definitional equations (1), (2), (3), (4)

begins. For example, during the first baud, x, and y, are taken and stored in the RAM 25 and may then be used to calculate x.,2 + y,2, the first iteration of rT0, equation (1). During the second 30 and successive samples, iterations of rT0 and the correlating equations rT1( rT2... are calculated. 30

As the second sample x2, y2 is taken, it is stored in the RAM 26, and the square of its magnitude, X22 + y22 is compared to the square of the first sample magnitude X-,2 + y,2 to determine which is larger. The larger is retained and compared to the square of the magnitude of the next sample to determine the largest sample and hence the peak 1 80 of the sampled 35 impulse response 17. The baud KP during which the peak 180 occurs is stored to be used in 35 subsequent operations. All samples x,, y, are also stored.

Sampling is terminated upon one of two conditions as indicated by a test 137 (Fig. 7). For the application of the preferred embodiment, it is advantageous to use eight samples before the peak and eleven after the peak. If eleven samples have occurred after the peak, K = KP + 11, 40 and matrix formation is terminated. If K<8, KP is set equal to eight (blocks 135, 136) so that 40 at least nineteen samples must be taken before formation can be terminated upon K — KP + 11. Otherwise, once twenty-four total samples have been taken, matrix formation is terminated and a flag is set.

Once the matrix flag is set, the next time through the flow, a branch 1 32 occurs to the test 45 141, K>20 (Fig. 8). If greater than 20 samples have been taken, the test 141 is satisfied, and 45 the processor 23 proceeds to correct the effect on the matrix of taking too many samples.

Thus, K>20 indicates that, because of the rough alignment of the counter KSTMX, too many samples before the occurrence of the peak 18 have been taken. These samples will likely ' contribute to inaccuracies and their effect is subtracted by an operation 143 denoted SUB 1.

50 This subtraction is accomplished by taking the first samples x,, y, from memory, calculating 50 their impact upon the values for the equations (1), (2), (3) for rT0, rT,, rT2, etc. and subtracting • that impact. After the effect of the first sample x1( y, is subtracted the sample counter K is decremented by one (block 145) and the K>20 test 141 is again performed. If the test 145 is not satisfied, the effect of the second sample pair x2, y2 is calculated and subtracted, etc. until 55 K<20. Once K<20, the values determined by the remaining sampels Xj, y: are utilized in the 55 subsequent matrix calculations.

Once K is reduced to 20, a branch 147 occurs to the tap constant calculation process,

equations (5)-(6) and (8)-(16), first passing through a test 149 to determine if the calculation has already been done. At the beginning of the calculation process, a counter N is set to zero. A 60 test 151 of the value of N is then made. 60

The first step 1 53 in the calculation process, with N equal to zero, is a normalization process. During this step, the r,'s and hk's of equations (4) and (5) are calculated by the microprocessor structure of Fig. 3.

The next time through branch 147, with N equal to 1 (block 155), the microprocessor 65 develops the equalization constants c, by calculating successive iterations of the equations (11) 65

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GB2076266A 8

(1 2) (1 3) (14) (15) (1 6), previously discussed.

With N = 2, the microprocessor structure of Fig. 3 begins to interact with the equalizer unit 34 in the following manner. The microprocessor calculates equations (11) and (12) and then transfer the "r" matrix (equation 7) and other intermediate calculation results to the equalizer 5 unit 34. In this manner, the microprocessor shifts part of the calculation responsibility to the equalizer unit 34 in order to free the processor to handle other operations on the incoming data. The equalizer unit 34 contains hard wired logic which performs or calculates the subsequent iterations of equations (11) through (14). For N = 2, the equalizer only calculates equations (13) and (14). At the end of each calculation of an iteration of equations (11) through (14) in the 10 equalizer unit 34, (1 3 and 14 only for N = 2) the processor calculates the quantity z, + 1,

equations (1 5) and (1 6), and returns that value to the equalizer 34 for performance of the next iteration of equations (11) through (14). This allocation of calculation between microprocessor and equalizer unit is merely due to a desire to efficiently utilize the apparatus. As is apparent, the assignment of the calculations of equations (11) through (14) to circuitry associated 15 schematically with the equalizer unit 34 is one approach to calculating the instant equalizer settings. Other approaches such as utilization of a more powerful microprocessor to do all calculations could be implemented according to the subject invention.

When N is equal to 1 5, the matrix has been solved for the tap constants ck and the iteration done flag is set. When the final tap constants are calculated, the hk's are stored and the final 20 equalizer constants Cj determined according to the just described procedure are set.

The just discussed operation is sufficient to set 1 6 taps. If the line signal is of such a poor quality that additional taps are needed, a fine tuning procedure may be performed in which additional bauds of known two phase data are sent and the error difference detected and used to adjust the additional taps according to conventional procedures.

25 As is indicated in the above discussion, many modifications and adaptations of the preferred embodiment are possible without departing from the scope and spirit of the invention.

For example, as illustrated in Fig. 9, 10, and 11 the in-phase and quadrature-phase signals used by the equalizer of the invention may be derived other than at baseband and in systems using various demodulation schemes.

30 Fig. 9 illustrates a simple quadrature demodulation technique wherein baseband signals x(t) and y(t) constitute the in-phase and quadrature-phase signals. In Fig. 9, the received signal on an input line 201 is fed to first and second mixers 203, 204 wherein the line signal is mixed with respective signals cos£oct and — sincoct where «c is the carrier frequency. The components are then filtered by respective baseband filters 207, 209 to yield the baseband quadrature 35 components x(t) and y(t).

In Fig. 10, the received signal is fed to a first passband filter 211 having an impulse response h(t) and to a second passband filter 213 having an impulse response h(t), which is the Hijbert transform of the impulse response h(t) of the first filter 211. The respective outputs h(t), h(t) of the filters 211, 213 are at passband frequency and constitute in-phase and quadrature-phase 40 signals which could be sampled by the equalizer of the subject invention.

In Fig. 11, an output h(t) of the filter 211 is fed to a first mixer 215 and to a third mixer 21 9. The output h(t) of the filter 213 is fed to a second mixer 217 and to a fourth mixer 221. The four mixers 215, 217, 219, 221 receive respective second inputs of coswct, sinco0t, sinwct, cos<act, where toc is the carrier frequency. The outputs of the first and second mixers 215, 217 45 are then summed by a summer 218 to give the demodulated baseband signal x(t). The outputs of the fourth mixer 221 is subtracted from the output of the third mixer 219 at a summer 220 to give the demodulated baseband signal y(t). In Fig. 11, x(t) and y(t) are in-phase and quadrature-phase signals which can also be sampled according to the invention to accomplish initial setting of the equalizer taps.

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Claims (1)

1. CLAIM

   1. Apparatus adapted for use with an equalizer, comprising first means adapted for connection to a communication channel and including a plurality of taps settable for compensating for distortions in the channel; and second means for producing a plurality of successive 55 samples of first and second signals representing the impulse response of the channel and for operating upon the samples to form elements of a matrix equation from the samples, iteratively calculate the exact values of the optimum settings for the taps utilizing the elements, and set the taps to the optimum values, wherein the successive samples are produced from a received test impulse and wherein the exact values are calculated in a time less than the duration of the 60 received test impulse.

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   Printed for Her Majesty's-Stationery Office by Burgess & Son (Abingdon) Ltd.—1981.

   Published at The Patent Office, 25 Southampton Buildings, London, WC2A 1AY, from which copies may be obtained.