GB2075808A - Equalizer with clock means for sampling data - Google Patents

Abstract

The quadrature demodulated data signal, sampled at 2 samples/baud, is represented by samples X and Y. Multipliers 63, 73, 79, 85, one sample delays 65, 71, 77, 81 and summers 67, 69, 75, 83 provide two signals ACK = 2(XnXn-1+YnYn-1> BCK = (Xn<2>-X<2>n-1)+(Yn<2>-Y<2>n-1> from which is calculated theta n = tan<-1>ACK DIVIDED BCK If theta n - 90 is less than 15 continuously for more than 10 counts, it is confirmed that the carrier-only portion of a training pattern has been received for 5 bauds and a flag TPP is set to 1 to indicate detection of the training pattern. <IMAGE>

Description

1

SPECIFICATION

Equalizer with clock means for sampling data GB 2 075 808 A 1 The present invention relates to an equalizer with clock means for sampling data and such as may be used as 5 a data communication channel equalizer, particularly an automatic adaptive equalizer sucy as are utilised in high speed data modems.

The invention is concerned with the problem of detecting carrier-only in a training pattern sent to the equalizer and the invention is defined in the claim below.

This application is one of four applications, all divided out of our application 7913018 (Serial No. 2022376), 10 All five applications are concerned with features of the equalizer now to be described and the numbers of the other divisional applications are as follows: Application No. 8118511, 8118512,8118513.

The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which:

Figure 1A illustrates the received signal utilized by the equalizer of the preferred embodiment.

Figure 18 and 1C illustrate quadrature phase components produced from the received signal on the same time scale as Figure 1A.

Figure 2 is a schematic diagram useful in illustrating the structure and operation of the equalizer of the preferred embodiment.

Figure 3 is a schematic diagram illustrating the digital processor utilized in the preferred embodiment of 20 the invention.

Figure 4 is a flow diagram illustrating the overall structure and operation utilized to properly time the sampling of the received signal in the preferred embodiment.

Figure 5 is a detailed flow diagram illustrating the method and apparatus utilized to detect the presence of the received signal in the preferred embodiment.

Figure 6 is a detailed flow diagram illustrating the method and apparatus employed in the preferred embodiment to properly set the points forsampling the received signal.

Figure 7 is a detailed flow diagram illustrating the method and apparatus employed in the preferred embodiment to determine the equalizer tap constant settings from the samples of the received signal.

Figure 8 is a continuation of the flow of Figure 7.

Figure 9 illustrates one technique suitable for generating phase quadrature signals for use in the subject invention.

Figure 10 illustrates an alternative technique for generating phase quadrature signals for use in the subject invention.

Figure 11 illustrates an alternative technique for generating phase quadrature signals for use in the subject 35 invention.

The automatic adaptive equalizer of the invention may be conveniently introduced in conjunction with the training pattern utilized to set up automatic gain control, timing and equalization, as shown in Figure 1. The training pattern of Figure 1 is the analog demodulated pattern at the receiver after transmission. The system of the preferred embodiment is particularly directed to the quadrature amplitude modulation (0AM) 40 technique.

The training pattern includes in succession a number of bauds of carrieronly 11, a number of bauds of clock-only 13, a quiet or squelch period 15, a received impulse 17, and another squelch period 19. The training pattern may also include an optional fine tuning sequence before the transmission of customer data 20.

In the preferred embodiment, eight bauds of carrier-only 11 and seventeen bauds of clock-only 13 are sent.

The squelch periods 15,19 are twenty-seven and twenty-one bauds long, respectively, and the impulse period is one baud long. Each baud period is 416.7 microseconds. Of course, other baud periods could be utilized. Also, the length of the periods 11, 17,15 and 19 depend on the maximum distortion. When the line distortion is less, less bauds are required for each one of them, especially for periods 17,15 and 19, and the total time fortuning will be shorter. When the line distortion is severe, more bauds are required for each - period, and the total tuning time will be longer.

During the carrier-only period 13 in Figure 1, the initial incidence of carrier energy on the line is detected (carrier detect), starting system operation. When carrier detect occurs, a rough timing counter KSTMX is started, which ultimately anticipates the occurrence of the impulse response 17. KSTIVIX counts once per 55 baud.

Automatic gain control is then performed on the carrier-only signal 11. After a fixed number of bauds of carrier-only 11 are detected, the system knows it is actually receiving a training pattern and can then expect the clock-only signal 13.

During the clock-only pattern 13, the apparatus examines the transmitted pattern to determine the 60 optimum points to sample the forthcoming impulse response 17. The apparatus then sets up for the impulse response sampling procedure. The first step is to use the sampling point previously calculated to jump or preset the sampling clock to the optimum sampling position. It may thus be seen that the preferred embodiment actually samples the response to a transmitted impulse although other means for generating signals representative of such samples could be employed.

2 GB 2 075 808 A 2 During the squelch period 15, the rough timing counter KSTMX, which was set-up upon detection of carrier-only, continues to count to subsequently indicate to the apparatus the point in time at which to start to sample the in-phase and quadrature phase impulse responses 17 (Figure 1 B, 1 Q. The samples are then taken, stored and correlated for forming a matrix. After the matrix is formed a special iterative technique is utilized to determine the precise initial tap settings, as discussed further below.

The apparatus employed to perform these operations is illustrated conceptually in block form in Figure 2.

The apparatus includes an analog to digital (A/D) converter and automatic gain control (AGQ section 21, a digital processor 23, and a transversal equalizer 28. The equalizer 28 is shown conceptually for purposes of illustration and is preferably implemented digitally, in which case it could also be shown as part of the digital processor23.

Digital demodulation of the QAM signal into in-phase (X) and quadrature phase (Y) base band components, is preferably accomplished in the digital processor 23. The analog form of the demodulated in-phase and quadrature phase baseband components is illustrated in Figures 1 B and 1 C, respectively. - Demodulation again may be performed by well-known techniques and may optionally be performed by dedicated apparatus outside the digital processor 23. Neither the AGC or demodulated technique used form a 15 part of the subject invention.

The X and Y phase components produced by demodulation represent samples in digital form of the baseband signal, the Y component sample being demodulated by a carrier 90'out of phase from the carrier demodulating the X component sample. In orderto calculate the proper sampling time during the clock-only period, two samples per baud are taken in the preferred embodiment. After the optimum clock phase is set, 20 the system takes one sample per baud.

These sampes X, Y are sent to separate channels 25, 27 of the transversal equalizer 28. Each channel 25, 27 includes equally spaced digital delay elements 29,31 and digital multipliers 30,32,33,35 as known in the prior art. The multipliers 32,33 multiply the delayed samples Xm by constants cpi and cqj while the multipliers 30,35 multiply the delayed Y,, by constants cpi and cqi. The outputs of each set of multipliers 30, 25 32,33, 35 are summed by respective summers 40,42,44,46 and fed to an adder 36. The output of one summer 46 is subtracted from that of the other 42 in a summer 37 to give the output data signal EQX The outputs of the othertwo summers 40,44 are summed by a summer 36 to give the output data signal EQY.

As shown in more detail in Figure 3, the preferred embodiment of the invention includes a programmed microprocessor structure and an equalizer unit. The equalizer unit 34 includes the functions of the equalizer 30 28 of Figure 2 and performs steady state adaptive equalization, for example as taught in our U.S. Patent 4,035,625. In the preferred structure of the present invention, the equalizer unit 34 also contains some circuitryfor accomplishing the initial equalizer setting, as will be further detailed below.

The microprocessor structure of Figure 3 is conventional, and includes a program store 16, a program counter 18, for addressing the program store 16, a command decoder 14 for decoding instructions from the 35 program store 16 to produce control signals and an arithmetic unit 22 for performing the instructions in response to the control signals from the decoder 14. The microprocessor structure also includes a data storage memory 26 and an address decoder 24 for addressing the memory. The program store 16 is a conventional read only memory (ROM) of sufficient capacity to store the instructions for performing the equalizer operations to be described below and may be constructed from four AMD 9216 ROM chips. The program counter 18 is a conventional counter which can be loaded or jumped as necessary in response to control signals from the command decoder 20. The arithmetic unit 22 is also conventional in structure and of suff icient power to carry out necessary operations as hereafter described. The data storage memory 26 includes storage for constants and 256 words of random access memory and may be configured from three AM91 Ll 2ADC RAM chips and one General Instrument R03-5120 chip. The random access storage is used to 45 store incoming samples of the impulse response 17 and subsequent data 20 while calculations are underway.

The apparatus of Figure 3 just described performs rapid initial equalization by calculating the initial equalizer tap multiplier constants in very rapid fashion. The manner of this calculation and the function and structure of the apparatus of Figure 3 will now be explained in detail.

3 GB 2 075 808 A 3 The multiplier constants to be calculated are labeled CP1, Cp2, CP3... cpj and C.1, Cq2, Cq3... c., (see Figure 2). In complex form the equalizertap constants may be expressed as:

Ci = Cp! + jCqi j = 1, 2,21---. n To calculate the equalizer constants cl from the pair of demodulated impulse responses as shown in Figure 1 B and 1 C, the following definitions are adopted:

M 2 2 rT = E (X + Y 0 - m m - M-1 rT 1 = E M-1 (na X M+1.+ Y m Y m+1) + j l1-1(x m Y 1n+l - Y m X m+l) (2) m=l lfi-i rT 2 2 jM2 (X m X m+2 + Y myni+2) + j E M-2 (X m Y m+2 --- Y m X m+2) (3) m=l. m=l 1 Mf R-9 - 25 rT n-1 = E M-+1 (XmXm+n-i+ Ymy+n-t + j (X m X M+nt Ymxm+n-1) (4) The following elements are defined:

hk Xn-q-k -iyn-qk k=1,2..n rTO (5) rTi 35 ri - rTO i=1,2n-1 (6) In the above equations (1) - (6), Xn, and Y,, are them th sample of the inphase and quadrature phase of the impulse response used for calculating the autocorrelation and cross correlation. Equations, (2), (3), (4) represent the auto-correlation and cross-correlation of the samples X,, and Y, In the above equations 1-6, M is the total number of samples used for calculating the auto-correlation and cross7correlation and n is equal to the number of taps, twenty for M and sixteen for n in the preferred embodiment, and q equals the subscript of the first sample actually used to calculate hk. The variable q accounts for the fact that in the preferred embodiment not all samples taken are used, in other words n is less than M as later explained in detail. If n equals M, q=1.

With these definitions, the equations defining the optimum tap constants cl, C2,... cn for an equalizer of n taps is written as follows in matrix form:

1 ri ri 1 r2 rl 1 r2...............

ri 1,.

h 12 h n (7) 4 GB 2 075 808 A In equation (7)m r,... ri and h,... hn are complex constants while cl... c,, are complex variables. The asterisk indicates the complex conjugate form.

A special solution of this equation (7) permits a precise iterative calculation of the tap constants cl... cj within the time interval required by the training scheme of Figure 1 plus the time relay required for data to propagate between the input and output of the equalizer. According to this solution, the following definitions are made:

el = 1 - /rl/2 Where/rl/ represents the magnitude of the complex quantity ri; si(l) = -rl Where superscript "(1)- indicates the first iteration i=l; and cl(') = h, Adapting these definitions, the exact iterative solution forthetap constants is asfollows:

ci+l). 1+1 S i+l) 1+1 c i+l) 5. (i+l) = S' i) 3 3 4 (8) (9) (10) (h,." i (i)) (Z) (11) c r. 1 1 30 +1 m=l m.1 -MI -- i -;:. (r + i+l ih=j r) (Z (12) im+l i 8 C!i) + c 5 (i) 1 js i < i (13) 35 3 i+1. i-i+l + S (i+l) S (i) - 1 < j < i (14) i+l ii+l - e.(1- S U+M 2 (15) 40 i+l i+l e.+1 45 The superscripts again indicate the value of the variable for a particular iteration. These equations 7-16 provide a simple means for rapidly and exactly calculating the tap constants cj in the complex matrix equation (7). This iterative technique enables the apparatus of the invention to calculate the constants cj and 50 set the equalizerto achieve initial equalization during a total training time of approximately. 30 milliseconds from the beginning of carrier only to the first bit of customer data in a 2400 baud machine. Variations of the matrix equation (7) may written and solved by the technique illustrated above without departing from the scope of this invention.

The structure and operation of the apparatus of Figure 3, as it relates to the preferred embodiment of the 55 invention, will now be descried in further detail in conjunction with Figures 4-8.

After the carrier is detected and the clock KSTMS is started, the system operates according to the flow illustrated in the flow chart of Figure 4. The flow of Figure 4 illustrates accomplishment of the automatic gain control function, filter, demodulation, the detecting of the training pattern present (TPP) and calculation of the optimum sampling point to be used in the subsequent operations of Figure 7. Two samples of the 60 carrier-only signal are processed each baud for the eight bauds of carrier-only 11. A counter N is set up at -8 to direct operation.

As long as N is less than zero, the left branch 45 of the flow is followed and each sample is subjected to an automatic gain control operation 47, a filter and demodulation operation 49 and the test pattern present detection 51. The test pattern detection checks six successive bauds of carrier-only signal and thereafter sets GB 2 075 808 A 5 a flag indicating that a test pattern is in fact being received. Eac. h baud, the counter N is incremented by one, as is the counter I(STIVIX.

When N equals zero, the clock-only signal 13 begins. AGC is frozen and the right hand branch 53 of the flow of Figure 4 is entered. In this branch 53, a filter and demodulation operation 55 is performed and a test 57 of the TPP flag is made. Assuming TPP has been detected and the TPP flag set, the fast learn clock operation 59 is performed. During this operation, denoted FI-CLK, the apparatus calculates the optimum sampling point for the forthcoming impulse based on the demodulated clock-only information. After each two samples per baud have been demodulated and used in the FLCLK process, the counter KSTMS is incremented by one, as is the N counter. When FLCLK is done, the flow proceeds to Figure 7.

The manner in which the training pattern detection is performed is illustrated in more detail in Figure 5. 10 Referring to Figure 5, X and Y samples of the demodulated baseband signal are supplied to the respective input at the rate of two samples per baud.

The samples presented to the X input are operated upon as follows. Each sample is first squared by a multiplier 63 and the output of the multiplier 63 is stored for one sample time in a delay element 65. The current output of the multiplier 63 is added to the negative value of the previous output of the multiplier 63 in 15 an adder 67. The output of the adder 67 is supplied as one input to a second adder 69. The X input is also supplied to a second one sample time delay element 71. The output of the second one-sample delay element 71 is supplied to a second multiplier 73, also supplied with the X input, such that the current X input sample is multiplied by the immediately preceding X sample. The output of the second multiplier 73 is fed to one input of a third summer 75.

The Y input is similarly operated on. A delay element 77 delays the first sample of the Y input and a multiplier 79 multiplies the first sample of the Y input 6y the delayed sample for supply to the third summer 75. The Y input is also squared and the square Y input value is supplied to a delay element 81. The delay squared sample is substracted from a present squared sample by a summer 83 whose output is supplied to the second summer 69.

The output of the first summer 73 is multiplied by two at a multiplier 85 to form an output denoted as ACK.

The output of the second summer 69 is denoted BCK. The arc tangent of ACK/BCK is then taken to determine the sampling angle On. The current value of 0, is stored by a delay element 87. The stored value of On is used in the clock preset to be subsequently discussed.

It is then determined whether On is within bounds for each of a number of counts NTPP. When NTPP is 30 greater than 10, five bauds of samples have been examined. Thus, if /On- 90/ is less than 15 continuously for greater than 10 NTPP counts it is confirmed that carrier has been received for 5 bauds, and the TPP flag is therefore set equal to 1. This operation is illustrated in Figure 5 by proceeding through blocks 91, 92, 93, to block 94, TPP equals 1. Once/On-90/ is greater than 15 and TPP equals 1, the clock preset routine is entered.

In the event, however, that/On-90/ is greater than 15 on any of the carrier-only samples operated on, the 35 test block 95, TPP=l, will not be satisfied, and NTPP will be reset to zero. In such event, if KSTMX is greater than 19, indicating nineteen bauds have occurred without detecting TPP, TPP not present is indicated. Failure to detect TPP normally indicates line dropout.

Once the training pattern is detected, it is necessary to properly align the timing of the sampling of the received impulse response 17. The sampling points are calculated such that the equalizer can best minimize 40 the output error. The structure and technique used in the preferred embodiment for performing the presetting of the sampling clock (FLCLK) is illustrated in detail in Figure 6.

Assuming no distortion or noise, the difference between successive angles 0, should be 180'. Therefore, if the magnitude (5 11On - On-11-1801 is less than 120 for several successive samples, the clock is in good range. Assuming that On is in good range 50 over several sampling intervals of the clock-only pattern, the loop including blocks 101, 102, 103,104,105, 106, and 107 in Figure 6 is operative. Initially, three counters NMT, NSAMP, and NAV are set to zero. When the first sample is tested, the sampling counter NSAMP is incremented by 1 as indicated by the block 101. The angle is then tested, and if it is within range, the counter NCNT is incremented by 1. After four 55 consecutive good samples, the test, NMT greater than or equal to four (Block 104) is satisfied, and NAV = 0 55 is satisfied. In this event, the test indicated by block 106 is performed to ascertain whether the magnitude of On is less than 90'. If so, a counter NR is set equal to 1. The counter NAV, representing the number to be averaged, is set equal to land TAGL (total angle) is defined as equal to On at this moment. The next time around the loop, thetest NAV = 0 is nottrue, and NR is incremented by one at block 108. NR + 1 is then equal to two. NR is then not odd, and another sample is taken. After this sample, assuming ( is still in bounds, NR 60 is odd (equal to 3). Therefore the number averaged NAV + 1 = 2 and TAGL is equal to the previous On value plus the new On value. Thus there are two angles to be averaged. Assuming that On continues to be within bounds, the number of On samples averaged is incremented to 4 and then the angle PO is determined at block 109 by calculating the quotient of TAGL and NAV. PO indicates the number of degrees from which the 65 sampling point being used diverges from the optimum sampling point. Thus, it takes 10 angle differences 6 GB 2 075 808 A 6 within bounds to reach the block PO = TAGUNAV.

In the event, however, that distortion is occurring, other provisions are made for calculating PO. For example, if it occurs that is greater than 12, satisfying block 102, a test 110 is made to determine is the number of good samples counted WNT is greaterthan or equal to 4, i.e. whether four inbounds angle tests have occurred. If so, a test 111 is made of the NAV counter to determine whether any samples TAGL have been stored for averaging. If any samples have been stored, the average 0., = TAGUNAV is computed as indicated by the four blocks 112,113,114,115. These four blocks indicate that PO is taken as equal to 0,v if NR is even, whereas PO is taken as equal to IS GN (0 av) 1 [1800 - 10av 11 if NR is odd. If, however, at the test 111, NAV is found to be equal to zero, indicating no samples 0,, have been 5 accumulated, PO is taken to be the current sample %.

If the NCNT -- 4 test 110 is not satisfied, a test 117 of the number of samples, indicated by counter KSTIVIX, is made. If that number I(STIVIX is greaterthan 29 (>14 bauds), PO is again taken to be %. If NCNT -- 4is not satisfied and KSTMX -- 29 is not satisfied, WNT is set to zero and another sample is examined. This procedure assures that if the angle determination is initially or occasionally out of bounds, subsequent angles can be examined to average the clock according to the previously discussed procedures.

PO then determines the phase shift of the impulse sampling clock to be used in the matrix sampling operation illustrated in Figure 7.

In Figure 7, the first time through, the new program (NP test 121 is positive and the left branch 123 of the flow is followed. Here the equalizer random access memory (RAM) 26 is reset. Also the optimum sampling point determined by FLCLK is used to jump the sampling clock to the optimum sampling position within each baud. The clock rate is reduced in half to 2400 Hz such that one sample per baud of the impulse response is taken from each of the X and Y channels.

The second time through the f low of Figure 7, a second branch 125 is followed. Detected samples are demodulated (block 127), and then a test 129 is performed on KSTMX to see if it is greater than 45. If it is not, KSTIVIX is incremented (block 131). As soon as KSTMX is greater than 45, matrix formation 133 from the 30 sampled impulse 17 begins.

The branch followed when I(STIVIX -- 45 includes a demodulated output energy test which assures that the system is receiving the equalizer test pattern and not customer data. After KSTIVIX is greater than 38 the energy is determined as denoted by blocks 134,138. If the energy is below a set level E,,f, the squelch period is assumed to have been detected and the system knows a training pattern is present. If the energy is greater 35 than Eref, training pattern TPP not present is indicated. This provides a double check on the presence of a training pattern.

Sampling of the impulse wave form.17 is illustrated bythe vertical lines in Figure 113 and 1C. The number of samples is counted by a counter K, started when KSTIVIX = 45. Each sample produces an X componentxi and a Y component yi. As the samples xi, yi are successively taken, formation of the matrix equation (7) according to the definitional equations (1), (2), (3), (4) begins. For example, during the first baud, xl and y, are taken and stored in the RAM 25 and may then be used to calculate X12 + yl ',the first iteration of rTO, equation (1). During the second and successive samples, iterations of rTO and the correlating equations rT,, rT2... are calculated.

As the second sample X2, Y2 is taken, it is stored in the RAM 26, and the square of its magnitude, X 2 2 + Y2 2 is 45 compared to the square of the first sample magnitude xl 2 + y12 to determine which is larger. The larger is retained and compared to the square of the magnitude of the next sample to determine the largest sample and hence the peak 180 of the sampled impulse response 17. The baud KP during which the peak 180 occurs is stored to be used in subsequent operations. All samples xi, yi are also stored.

Sampling is terminated upon one of two conditions as indicated by a test 137 (Figure 7). For the application 50 of the preferred embodiment, it is advantageous to use eight samples before the peak and eleven afterthe peak. If eleven samples have occurred after the peak, K= KP + 11, and matrix formation is terminated. If K < 8, KP is set equal to eight (blocks 135,136) so that at least nineteen samples must be taken beforeformation can be terminated upon K - KP + 11. Otherwise, once twenty-four total samples have been taken, matrix formation is terminated and a flag is set.

Once the matrix flag is set, the next time through the flow, a branch 132 occurs to the test 141, K> 20 (Figure 8). If greater than 20 samples have been taken, the test 141 is satisfied, and the processor 23 proceeds to correct the effect on the matrix of taking too many samples.

Thus, K > 20 indicates that, because of the rough alignment of the counter KSTMX, too many samples before the occurrence of the peak 18 have been taken. These samples will likely contribute to inaccuracies 60 and their effect is substracted by an operation 143 denoted SUB 1. This substraction is accomplished by taking the first samples xl, y, from memory, calculating their impact upon the values for the equations (1), (2), (3) for rTo, rT,, rT2, etc. and substracting that impact. After the effect of the first sample xl, y, is subtracted the sample counter K is decremented by one (block 145) and the K > 20 test 141 is again performed. If the test 145 is not satisfied, the effect of the second sample pair X2, Y2 is calculated and substracted, etc. until K -- 20.65 1 25 7 GB 2 075 808 A 7 Once K -- 20, the values determined by the remaining samples xi,y; are utilized in the subsequent matrix calculations.

Once K is reduced to 20, a branch 147 occurs to the tap constant calculation process, equations (5) - (6) and (8) - (16), first passing through a test 149 to determine if the calculation has already been done. At the beginning of the calculation process, a counter N is set to zero. A test 151 of the value of N is then made.

The first step 153 in the calculating process, with N equal to zero, is a normalization process. During this step, the ri's and hk'S of equations (4) and (5) are calculated by the microprocessor structure of Figure 3.

The next time through branch 147, with N equal to 1 (block 155), the microprocessor develops the equalization constants cj by calculating successive iterations of the equations (11) (12) (13) (14) (15).(16), previously discussed.

With N = 2, the microprocessor structure of Figure 3 begins to interact with the equalizer unit 34 in the following manner. The microprocessor calculates equations (11) and (12) and then transfer the "r" matrix (equation 7) and other intermediate calculation results to the equalizer unit 34. In this manner, the microprocessor shifts part of the calculation responsibility to the equalizer unit 34 in order to free the processor to handle other operations on the incoming data. The equalizer unit 34 contains hard wired logic 15 which performs or calculates the subsequent iterations of equations (11) through (14). For N = 2, the equalizer only calculates equations (13) and (14). At the end of each calculation of an iteration of equations (11) through (14) in the equalizer unit 34, (13 and 14 only for N=2) the processor calculates the quantity zi+l, equations (15) and (16), and returns that value to the equalizer 34 for performance of the next iteration of equations (11) through (14). This allocation ofcalculation between microprocessor and equalizer unit is merely due to a desire to efficiently utilize the apparatus. As is apparent, the assignment of the calculations of equations (11) through (14) to circuitry associated schematically with the equalizer unit 34 is one approach to calculating the instant equalizer settings. Other approaches such as utilization of a more powerful microprocessor to do all calculations could be implemented according to the subject invention.

When N is equal to 15, the matrix has been solved for the tap constants Ck and the iteration done flag is set. 25 When the final tap constants are calculated, the hk's are stored and the final equalizer constants cl determined according to the just prescribed procedure are set.

The just discussed operation is sufficient to set 16 taps. If the line signal is of such a poor quality that additional taps are needed, a fine tuning procedure may be performed in which additional bauds of known two phase data are sent and the error difference detected and used to adjust the additional taps according to 30 conventional procedures.

As is indicated in the above discussion, many modifications and adaptations of the preferred embodiment are possible without departing from the scope and spirit of the invention.

For example, as illustrated in Figure 9, 10, and 11 the in-phase and quadrature-phase signals used by the equalizer of the invention may be derived otherthan at baseband and in systems using various demodulation schemes.

Figure 9 illustrates a simple quadrature demodulation technique wherein baseband signals x(t) and y(t) constitute the in-phase and quad ratu re-phase signals. In Figure 9, the received signal on an input line 201 is fed to first and second mixers 203, 204 wherein the line signal is mixed with respective signals coswt and - sinoct where wc is the carrier frequency. The components are then filtered by respective baseband filters 207, 40 209 to yield the baseband quadrature components x(t) and y(t).

In Figure 10, the received signal is fed to a first passband filter 211 having an impulse response h(t) and to a second passband filter 213 having an impulse response M(t), which is the Hilbert transform of the impulse response h(t) of the first filter 211. The respective outputs h(t), fi(t) of the filters 211, 213 are at passband frequency and constitute in-phase and quadrature-phase signals which could be sampled by the equalizer of 45 the subject invention.

In Figure 11, an output h(t) of the filter 211 is fed to a first mixer 215 and to a third mixer 219. The output fi(t) of the filter 213 is fed to a second mixer 217 and to a fourth mixer 221. The four mixers 215, 217, 219, 221 receive respective second inputs of cosw,,t, sinwt, sincot, cosa),t, where coc is the carrier frequency. The outputs of the first and second mixers 215, 217 are then summed by a summer 218 to give the demodulated 50 baseband signal x(t). The outputs of the fourth mixer 221 is subtracted from the output of the third mixer 219 at a summer 220 to give the demodulated baseband signal y(t). In Figure 11, x(t) and y(t) are in-phase and quadrature-phase signals which can also be sampled according to the invention to accomplish initial setting of the equalizer taps.

Claims (1)

1. CLAIM

   An equalizer supplied with a training pattern including a carrier-only signal, including means for sampling said training pattern, and means for detecting the carrier-only signal comprising means for providing a succession of are tangents from the samples derived during the carrieronly signal; and means for testing 60 said arc tangents to determine that a carrier-only signal is present.

   Printed for Her Majesty's Stationery Office, by Croydon Printing Company Limited, Croydon, Surrey. 1981.

   Published by The Patent Office, 25 Southampton Building$, London, WC2A lAY, from which copies may be obtained.