CH645764A5 - DEVICE WITH A COMPENSATING CIRCUIT FOR RECEIVING A SIGNAL TRANSMITTED BY A DISTORMING MEDIUM. - Google Patents

Description

The invention relates to a device with an equalizing circuit for receiving a signal transmitted through a distorting medium. Such devices are used, for example, in high-speed data modems to which data is supplied via a transmission channel in which distortions occur.

The aim is to enable a very precise and fast adjustment by processing the reproduction of a single test pulse transmitted, preferably under the control of a microprocessor.

Accurate and quick adjustment is particularly desirable for quick query operations. In such operations, it is common to rapidly connect to a number of remote stations, e.g. in different cities, from a central station. The connection to each remote station is established via a new transmission line, so that the compensation must be adjusted each time a new remote station is queried. Therefore, it is highly desirable to shorten the time required for balancing as much as possible to increase the data transmission line.

With many known balancing devices, it is connected to a new transmission line, achieved relatively slowly, as a result of which valuable data transmission time is lost. As a rule, numerous time-consuming individual adjustments of the elements of an equalization circuit are required during an analysis of a relatively long time interval which contains random data or a setting signal pattern with numerous test pulses.

According to another known proposal, the compensation should be achieved with a single test pulse transmitted. In practice, however, several test pulses are required. This proposal is published in the Bell System Technical Journal, Volume 50, No. 6, pages

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1969-2041, in an article by Robert W. Chang entitled "A New Equalizer Structure for Fast Start Up Digital Communications".

With another known compensation device, which is described in US Pat. No. 3,962,637, the compensation is achieved during the duration of the reproduction of two transmitted pulses according to a method which is an approximation of the known zeroing technique (zero-forcing scheme) and not works with the correlation of signal samples. The adjustment with this device requires an additional pulse for adjusting the phase of the line signal in such a way that the test can be carried out correctly. Since this device uses the zeroing technique, or rather an approximation thereof, it does not work satisfactorily on a line with strong distortions or when high accuracy is required. The device is designed to operate at 4800 bits per second; it is not suitable for operation with the much higher data speed of 9600 bits per second.

In IEEE Transactions On Communications, Volume Com.23, No. 6, June 1975, P. Butler and co-workers describe a method which enables a direct solution of a matrix equation in real variables, which enables the setting of the element constants of an equalization circuit in a Single sideband system describes. However, the method requires a relatively long set of set signals to achieve an acceptable accuracy solution. The method also cannot solve a matrix equation with complex variables. Therefore, the method cannot be used for equalization in a second-sideband system.

The object of the invention is therefore to provide a device with a compensation circuit which can be set faster and more accurately than known compensation devices, the setting of the elements of the compensation circuit in a wide range of different line distortions and data speeds, preferably based on the analysis of a single one transmitted pulse should be possible. The limb constants of the compensation circuit should be calculated precisely, and not using approximations. The exact calculation is to be made possible by an iterative method, which is preferably carried out during the period in which a transmitted pulse is received, so that the limb constants of the compensation circuit in the interval between the end of the pulse time and the time in which the first received data reach the first link of the compensation circuit, can be calculated and set.

The initial adjustment of the compensation circuit should be possible in a very short time, e.g. in 30 milliseconds at a data rate of 9600 bits per second or in 15-20 milliseconds at a data rate of 4800 bits per second.

The compensation device according to the invention is defined in claim 1.

In this device, a signal can be analyzed, which is transmitted by a transmitter via a telecommunication medium. For example, this signal may contain a single received pulse. From the received signal, the device can form pulse reproduction signals in the form of a pulse demodulated with two carriers that are phase-shifted by 90 ° relative to one another, which pulses can be in the passband or in the baseband or on another converted frequency. Trial values from these two pulse reproduction signals are used to form a complex matrix equation. Such a matrix equation contains elements which are characterized by the eigen- and cross-correlation of

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sample values taken from the two pulse reproduction signals. The complex matrix equation thus formed is solved in the device, as a result of which the exact values for the setting of all elements of the compensation circuit are obtained. With these settings of the compensation circuit, the distortion in the telecommunication medium, via which the setting signal pattern was transmitted, can be completely compensated. After the setting has been made in the device, a conventional adaptive adjustment can then be carried out while data is being received.

A main advantage is that in preferred embodiments of the device according to the invention it is possible to carry out an exact calculation of the compensation constants from the sample values in a time period which is of the order of magnitude of the duration of an individual received pulse, even then, when the distortions caused by the medium over which the received pulse is transmitted are widely varied. In a preferred embodiment of the compensation device according to the invention, the compensation can be carried out in a time span of approximately 30 milliseconds at a data speed of 9600 bits per second. This is almost five times faster than the adjustment in today's commercial facilities. In the preferred embodiment, the equalization is carried out depending on a single received pulse, and an essential feature of this preferred embodiment is that it includes means for determining the optimal times for checking the pulse reproductions before receiving them. The compensation is preferably carried out using pulse reproduction signals in the baseband, but these signals can also be derived in the passband or at another converted frequency.

A preferred embodiment of the device according to the invention is explained in more detail below with reference to the drawing. The drawing shows:

1A shows the received signal used by the preferred equalizer;

1B and IC components that are generated from the received signals by demodulation with two carriers that are 90 ° out of phase with one another, on the same time scale as FIG. 1A,

2 shows a schematic illustration to explain the structure and mode of operation of the compensation device,

3 shows a schematic illustration of the digital process computer used in the compensation device, FIG. 4 shows a flow diagram for explaining the parts of the device and processes for the correct selection of the times for checking the received signal,

5 is a detailed flow chart for explaining the equipment parts and procedures for determining the presence of the received signal.

6 shows a detailed flow diagram to explain the equipment parts and processes for setting the times for checking the received signal,

7 is a detailed flow diagram for explaining the device parts and processes for determining the setting of the element constants of the compensation circuit from the samples taken from the received signal.

8 is a continuation of the flow diagram of FIG. 7, FIG. 9 is a diagram of means for generating signals obtained by demodulation with carriers that are 90 ° out of phase with one another,

10 is a diagram of other means for generating by 90 ° demodulation with each other

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signals and matrix obtained from shifted carriers. After the matrix is formed, a

11 shows yet another embodiment of means using a special iterative method to generate the precise signals obtained by phase-shifting the phase of the compensation circuit by demodulation with settings of the elements of the compensation circuit. gene, as explained in detail below.

The automatically adjustable compensating device is shown in FIG. 2. The setting signal device used for carrying out these operations in connection with the setting signal device shown in FIG. 1 is shown in block form. The one pattern described that for setting the automatic direction contains an analog / digital converter (A / D) and see gain control, timing and equalization an automatic gain control circuit is used in one. The setting signal pattern according to FIG. 1 is section 21, a digital process computer 23 and the analog, demodulated signal pattern which is obtained after the transversal equalization circuit 28. The equalization circuit averaging is received in the receiver. The device 28 is functionally shown for the explanation; it with amplitude modulation and demodulation with is preferably carried out digitally and could be phase-shifted in this 90 °. Case also be shown as part of the process computer 23.

The setting signal pattern contains a sequence of digital demodulation of the amplitude modulated

Number of character intervals 11 with carriers alone, a number 15 signals with two carriers phase-shifted by 90 ° in two character intervals 13 with clock signal alone on the carrier, baseband components X and Y are preferably in the pro a break 15 without a signal, a received pulse 17 and Process computer 23 performed. The analog form of this demodu- a second pause 19. The setting signal pattern can further Herten baseband components is shown in Fig. 1B or IC before the transmission of subscriber data 20. The demodulation can include fine-tuning in accordance with known procedures. 20 years can be performed; if she could, she could

In the preferred embodiment, eight times outside the digital process computer 23 will take place in predetermined intervals 11 with carriers alone and seventeen character-internal circuits. Neither the automatic amplifier 13 with the clock signal is sent out alone. The pauses 15 and kung control and the demodulation method 19 used are twenty-seven and twenty-one character interiors are essential to the invention.

valle long, and the pulse interval has a length of 25 The X and Y compo character interval generated by the demodulation. The length of each character interval is 416.7 microseconds, in digital form, samples of the baseband signal. Of course, other inter- dars could also be used, using the Y component sample with a carrier valle. Furthermore, the length of the signal is demodulated, against which the X-component sample 11, 13, 15 and 19 depends on the maximum distortion. demodulated carrier is 90 ° out of phase. If the line distortions are smaller, fewer character intervals are required for calculating the correct test time during which these signal intervals, in particular signal intervals with carrier alone are preferred for signal intervals 13, 15 and 19, and the embodiment in each character interval two rehearse

Total time for the vote will be shorter. If the leech taken. After setting the optimal clock signal distortions are strong, for each signal interval phase the device takes one more check per character interval and the entire tuning interval.

time becomes longer. These samples X and Y become separate channels 25

During the signal interval 11 with the carrier alone, the and 27 are fed to the transverse compensation circuit 28, the first occurrence of carrier energy on the line determines - each of the channels 25 and 27 contains established in a known manner (carrier detection), and the operation of the device arranged digitally spaced apart Delay elements begins. When the carrier detection occurs, a coarse 40 becomes 29 or 31 and digital multipliers 30,32,33,35. The timer counter KSTMX started, which finally predicts the occurrence multipliers 32 and 33 multiplying the delayed percentage of the pulse 17. The counter KSTMX counts one Xm with constants cpj and cqi5 and the multipliers times per character interval. 30, 35 multiply the delayed samples Ym by the con-

The automatic gain control will then be constant cp, and cq ,. The output signals of the multipliers are set on the basis of the carrier alone in the signal interval 11. 45 30, 32, 33, 35 are assigned in respective assigned summing scales. After a defined number of character intervals with deletions 40, 42, 44, 46 have been added and an adding circuit 36 has been determined alone, the device or 37 closes. The output of the one summing out that it is actually receiving a set signal pattern circuit 46 is subtracted from that of the summing circuit 42 and therefore the signal interval 13 with clock signal alone in the adding circuit 37 is expected to be an output da. 50 tensignal EQX form. The output signals of the two

During the signal interval 13 with the clock signal alone other summing circuits 40 and 44, the device checks the transmitted pattern in order to add the optical adder circuit 36 in order to form an output data signal to paint times for the test of the expected pulse EQY.

ses 17 to determine. Then, the device prepares the pulse. As shown in detail in Fig. 3, it contains the pre-test procedures. The first step consists in the fact that the fifty-fifth embodiment of the device according to the invention previously calculated test time is used to preset the test - a programmed microprocessor and a compensation clock for the optimal test time. In the circuit. The equalization circuit 34 has the functions of the preferred embodiment, so it is actually the over-equalization circuit 28 of FIG. 2 and effects the steady-state averaged and received pulse being checked, although other operations also provide the adjustable equalization, for example as in means for generating signals that generate the Impulse test values 60 of U.S. Patent 4,035,625. In the preferred embodiment, could be used. tion form contains the compensation circuit 34 also certain

During pause 15, the coarse timer counter counts circuit parts to effect the initial setting

KSTMX, which was started when the carrier was detected in the signal interval 11 of the compensation circuit, as described below, in order to then switch on the time. The microprocessor according to FIG. 3 is of a known type, in which the test of the demodulation with 05 and contains a program memory 16, a command counter received by 90 ° phase-shifted carriers pulse-18 for address selection in the program memory 16, a command order 17 (Fig. 1B, IC) has to begin. The test values are then decoder 14 for decoding the instructions from the prod, determined, stored and correlated to a gram memory 16 and generating control signals as well

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an arithmetic unit 22 for executing the instructions under the control of the control signals generated by the decoder 14. The microprocessor also contains a data memory 26 and an address decoder 24 for address selection in this memory. Program memory 16 is a conventional read-only memory (ROM) with sufficient capacity to store the instructions required for the compensation circuit operations described below; it can be made up of four "AMD 9216" read-only memory chips. The command counter 18 is a conventional counter that can count or jump in response to control signals from the command decoder. The arithmetic unit 22 also has a conventional structure and sufficient performance to perform the operations described below. The data memory 26 contains memory locations for constants and read-write memory locations for 256 words; it can be constructed from three “AM91L12ADC” read-write memory chips and a “R03-5120” chip from General Instruments. The read / write memory locations serve to store the incoming samples from the pulse reproduction 17 and the subsequent data 20 while the calculations are being carried out.

3 performs the rapid initial equalization by calculating the initial multiplication constants of the elements of the equalization circuit. The manner of this calculation and the function and structure of the device according to FIG. 3 will now be explained in detail.

10 The multiplication constants to be calculated are designated cpi, cp :, cp3 ... cpi and cqi, cqi, cqj ... cpi (see Fig. 2). In complex form, the multiplication constants of the elements of the compensation circuit can be designated as follows:

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c | = cpi + j-cqi, i = f, 2, 3, ... n

The following definitions are used to calculate the compensation constant c from the two demodulated pulse reproductions according to FIG. 1B 20 and IC:

rl0 = 4 + 1 *)

m = l fcl rTi =

+1 + YmYm + l ^ + Î '

l-l m = l rT2 + Vm + 2> + <Vm + 2

m = l m = l

<Vm.

+1

Vm + 2>

(1)

(2)

(3)

r3L

M-n + 1

a-1 (VW-1 + TmWl> + l'G <Vm + n-l "VW-1>

m = l

M-n + 1

(4)

The following elements are defined:

s "^ * Yn-q-k ri rar

k = ly 2 •• «H

i = 1,2. ♦ • n-1

(5)

(6)

In the above equations (1) - (6), Xm and Ym mean the pulse reproductions obtained by demodulation with two carriers phase-shifted by 90 °, which are used for the calculation of the self-correlation and the cross-correlation. Equations (2), (3) and (4) represent the self-correlation and the cross-correlation of the samples Xm and Ym.

In Equations (1) - (6), M is the total number of samples used to calculate the self-correlation and cross-correlation, twenty in the preferred embodiment, n is the number of terms, sixteen in the preferred embodiment, and q the index of the first sample that is effectively used for the calculation of hk

60 is applied. The variable q takes into account the fact that not all samples taken are used in the preferred embodiment, since n is less than M, as explained below. If n is M, then q = 1.

With these definitions, the equations that determine the optimal term constants ci, C2, ... cn for an equalization circuit with n terms are written in matrix form as follows:

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V

î

r.

r2 *

i rn

6

■ p *

1

1

• • •

•

• • • • • •

•

1

• • •

r * r *

n-1

n-2

r *.

r *.

n-3 n-4

r * -,

"n-1.

In equation (7), n ... n and ht ... hn are complex constants, while ci ... cn are complex variables. The asterisk (*) denotes the conjugate complex form.

A special solution to this equation (7) allows an exact iterative calculation of the element constants ci ... q within the time interval required for the setting signal pattern according to FIG. 1 and the time in which the data propagate from the input to the output of the compensation circuit. After this solution, the following definitions are made:

- »

H-,

(7)

in which | n | is the absolute size of the complex number ri

Sl

(i) = _

(9)

25 where the superscript “(1)” denotes the first iteration i = 1, and ci (') = hl

(10)

30th

ei = 1 - Ir, I2

(8th)

With these definitions, the exact iterative solution for the term constants is as follows:

0 (i + l) ° i + l

(i + 1) +1

(i + 1)

si + l

° 3

sA * V

V

'hi + l

-fr'i + l

° yes)

1

-nll m

+ + c

A

m

+ s sas atti ei + i = ei (1-

s

(i + 1) i + 1

zi + l =

egg + 1

(1) ri-m + l>

(l) (ai)

1 £ D ^ i

S * (i) i-j + l

* (i)

i-j + l

(11)

(12)

(15)

(14)

(15)

(16)

The superscript indices again denote the value of the variables for a particular iteration. These equations (7) - (16) allow a simple and quick calculation of the term constants q in the complex matrix equation (7). With this iterative procedure, the device can set the constants c; calculate and adjust the equalizer to effect the initial adjustment within a total response time of approximately 30 milliseconds between the start of the carrier alone interval and the first bit of subscriber data in a 2400 baud machine. Variants of the matrix equation (7) are possible and can be solved using the same method as described.

The structure and the mode of operation of the device according to FIG. 3 will now be explained in more detail with reference to FIGS. 4-8 for the preferred embodiment of the invention.

After the carrier has been determined and the coarse timer counter KSTMX has started, the device 60 operates according to the flow diagram shown in FIG. 4. FIG. 4 shows the setting of the automatic gain control, the filtering and demodulating, the determination of the presence of the setting signal pattern and the calculation of the optimal test time, which is to be used in the subsequent operations according to FIG. 7. Two samples of the carrier signal are processed in each of the character intervals of the signal interval 11 with carrier alone. A counter N is set to -8 to control the operations.

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As long as N is less than zero, the left branch 43 of the flowchart is operated, each sample being subjected to setting 47 of the automatic gain control, filtering and demodulating 49 and an operation 51 to determine the presence of the setting signal pattern (setting signal present = TPP) . Operation 51 checks six consecutive character intervals of the carrier signal and then sets a flag TPP which indicates that a set signal pattern is actually being received. The counter N is incremented by one with each character interval, and the same applies to the counter KSTMX.

If N is zero, the interval begins with the clock signal alone. The automatic gain control is fixed and the method continues according to the right branch 53 of the flow diagram of FIG. 4. In this branch 53, an operation 55 for filtering and demodulating and a check 57 of the mark TPP indicating the presence of the setting signal pattern are carried out. If the setting signal pattern has been detected and the TPP flag indicating its existence is set, then an operation 59 for quickly setting the clock signal generation is performed. During this operation, labeled RETSE, the device calculates the optimal test time for the subsequent pulse based on the demodulated received pure clock signal. After the two samples in each character interval have been demodulated and used in the RETSE process, the counter KSTMX is incremented by one, and the counter N as well. After the RETSE has been carried out, the flowchart proceeds to FIG. 7.

The manner in which the setting signal pattern is determined is shown in detail in FIG. 5. 5, X and Y samples of the demodulated baseband signal are fed to the corresponding inputs at the rate of two samples per character interval.

The samples fed to the X input are processed as follows. Each sample is first squared in a multiplier 63, and the output signal of the multiplier 63 is stored in a delay element 65 for the duration of a sample interval. The output current of the multiplier 63 is added in an adder circuit 67 to the negative value of the previous output signal of the multiplier 63. The output signal of the adder circuit 67 is supplied to a second adder circuit 69 as one of the input signals. The X-probe is also fed to a second delay element 71 and delayed there by the duration of a test interval. The output signal of this second delay element 71 is fed to a second multiplier 73, to which the X sample is also fed directly, so that the X sample is multiplied by the immediately preceding X sample. The output signal of the second multiplier 73 is fed to one input of a third adder circuit 75.

The Y samples are processed in a corresponding manner. A delay element 77 delays the first Y sample, and a multiplier 79 multiplies the sample subsequently supplied to the Y input by the delayed sample and supplies the product to the third adder circuit 75. The Y sample is also squared and the square is fed to a delay element 81. The delayed squared sample is subtracted from an actual squared sample in an adder 83, and the difference is supplied to the second adder 69.

The output signal of the third adder circuit 75 is multiplied by two in a multiplier 85 to form an output signal designated ACK. The output signal of the second adder circuit 69 is designated BCK. The arctg of ACK / BCK is then determined to set the test angle 0n. The current value of 0n is stored by a delay element 87. The stored value of 0n is used for the clock signal presetting described below.

It is then determined whether 0n is within predetermined limits during each count of a number of NTPP counts. If NTPP is greater than ten, the samples from five character intervals have been examined. If [0n-901 is continuously less than 15 for more than ten NTPP counts, it is confirmed that the carrier has been received during five character intervals, and therefore the setting pattern flag (TPP flag) is set. This process is illustrated in FIG. 5 by the sequence of blocks 91, 92, 93, 94. As soon as | 0 "- 901 is greater than 15 while the setting pattern mark is set, the process proceeds to the clock signal presetting.

However, if | 0n - 901 becomes greater than 15 for at least one of the processed carrier samples, then the condition of the test block 95, setting pattern mark on, is not met, so that NTPP is reset to zero. In such a case, if KSTMX is greater than 19, which means that 19 character intervals have occurred without the setting signal pattern being determined, then “Setting signal pattern not available” is displayed. The lack of setting signal pattern detection usually indicates a line failure.

When the setting signal pattern has been determined, the test timings for the received pulse reproduction 17 must be set correctly. The test times are calculated so that the results can be used to optimally adjust the compensation circuit for the smallest possible output error. The structures and methods used in the preferred embodiment for presetting test clock signal generation (RETSE) are shown in detail in FIG. 6.

Assuming that there is no distortion and no noise, the difference between successive angles should be 9 "180 °. The clock signal is therefore in a good range if the size

0 = II 0n - 0n_, | - 180 ° |

is less than 12 ° for several successive samples. If 0 ″ is in a good range during several test intervals of the clock signal, then the loop containing blocks 101, 102, 103, 105, 106 and 107 in FIG. 6 is used. Initially, three counters NCNT, NSAMP and NAV are set to zero. When the first sample is tested, the test counter NSAMP is incremented by one, as represented by block 101. The angle 0 is then checked, and if it is in the good range,

the NCNT counter is incremented by one. After four successive samples in the good range, the test conditions NCNT equal to or greater than four (block 104) and NAV = 0 are met. In this case, the test represented by block 106 is made to determine whether the size of 0n is less than 90 °. If applicable, a counter NR is set to one. The counter NAV, which represents the number of values to be averaged, is set to one, and 0N is recorded as TAGL (total angle) at this time. The next time through the loop, the test condition NAV = 0 is not met, and NR is advanced by one in block 108. NR + 1 is then two. NR is therefore not odd, so another sample is tested. After this check, and assuming 0 is still in the good range, NR becomes odd

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(three at once). Therefore, the number of values to be averaged becomes NAV + 1 = 2, and TAGL becomes equal to the sum of the previous 0n value and the new 0n value. So there are two angles to the middle. If 0n is still in the good range, the number of 0n samples to be averaged is increased to four, and then the angle Pe is determined in block 109 by calculating the quotient from TAGL and NAV. P0 denotes the angle by which the test time used deviates from the optimal test time. So ten good angular differences are required to reach the block PH = TAGL / NAV.

However, if distortions occur, Pein is calculated differently. If, for example, © is greater than 12 ° and thus fulfills the conditions of block 102, a check 110 is carried out in order to determine whether the number of counted NCNT samples which are in the good range is equal to or greater than four, i.e. whether four tests have already been carried out from angles in the good range. If applicable, a check 111 of counter NAV is performed to determine if any samples of TAGL are stored for averaging. If such samples are stored, the average value 0av = TAGL / NAV is calculated, as represented by the four blocks 112, 113, 114 and 115. These four blocks show that PB is taken equal to 0av when NR is even and that PH is taken

[SGN (0av)] [180 ° - | 0av |]

i.e. the sign of 0av times (180 ° - amount of 0av) is taken if NR is odd. However, if it is determined in test 111 that NAV is zero, that is to say that no samples 0n have been stored, then the sample 0n that is just occurring is taken as PB.

If the test condition NCNT> 4 is not fulfilled in block 110, then a test 117 determines the number of samples which is displayed by the counter KSTMX. If the number displayed by the counter KSTMX is greater than 29 (> 14 character intervals), then 0n is used again as PH. If the condition NCNT> 4 is not fulfilled and also the condition KSTMX> 29 is not fulfilled, NCNT is set to zero and another sample is examined. With this procedure it is achieved that if the determined angle is initially or occasionally outside the good range, subsequent angles can be checked in order to center the clock signal in the manner already described.

The phase shift of the clock signal which is to be used for the pulse test in the matrix test process shown in FIG. 7 is defined by PH.

In FIG. 7, the test 121 for a new program (NP) is positive on the first pass, so that the left branch 123 of the flowchart is used. The read / write memory 26 of the compensation circuit is deleted. Furthermore, the optimal test time determined with the RETSE is used to set the test clock signal generation to the optimal test time in each character interval. The clock signal repetition frequency is halved to 2400 Hz, so that one sample is taken from the pulse reproduction per character interval and in the Y channel.

The second pass through the flowchart of FIG. 7 occurs after a second branch 125. The detected samples are demodulated (block 127), and then a check 129 is performed to determine if KSTMX is greater than 45. If this is not the case, KSTMX is switched on (block 131). As soon as KSTMX is greater than 45, the matrix formation 133 begins on the basis of the pulse 17 that has been tested.

The branch traversed at KSTMX <45 contains a check of the demodulated output energy, with which it is determined that the device is receiving the setting signal pattern and not subscriber data. After KSTMX is greater than 38, the energy is determined by blocks 134, 138. If the energy is below a preset value Eref, it is assumed that a pause interval has been determined and that the device therefore receives a setting signal pattern. If the energy is greater than Ererist, it indicates that there is no set signal pattern. The existence of the setting signal pattern is thus checked twice.

The sample test of the pulse reproduction 17 is shown by vertical lines in Fig. 1B and IC. The number of samples is counted by a counter IC which is started when KSTMX = 45. Each sample provides an X component x; and a Y component y, -. If the samples x; and yi are received in succession, the formation of the matrix equation (7) begins according to the definition equations (1), (2), (3), (4). For example, xi and yi are received in the first sample interval and stored in the read-write memory 26 so that they can then be used to calculate xi2 + yi2, the first iteration of rTo, see equation (1). The further iterations of rTo and the correlation equations rTi, rT2 ... are calculated from the second and subsequent samples.

When the second sample X2, yi is received, it is stored in the random access memory 26 and the square of its size, X22 + yi2, is compared with the square of the size of the first sample, xi2 + yi2, to determine which is bigger. The larger square is saved and compared with the square of the size of the next sample in order to finally determine the largest square and thus the vertex 180 of the pulse reproduction 17 tested. The sample interval KP, in which the apex 180 occurs, is stored for later use. All samples X ;, y; are also saved.

Sampling ends when test 137 (FIG. 7) meets one of two conditions. In the preferred embodiment, it is advantageous to use eight samples before the apex and eleven samples after the apex. When eleven samples have appeared after the apex, K = KP + 11 and matrix formation is complete. As long as K <8, KP = 8 is set (blocks 135 and 136), so that at least nineteen samples must be taken before the matrix formation can be ended with K = KP + 11. Otherwise the matrix formation is ended and a corresponding mark is set when a total of 24 samples have been taken.

If the “matrix finished” mark is set, a branch 132 to a test 141 (FIG. 8) is taken the next time through the flow diagram, with which it is determined whether K> 20. If more than 20 samples have been taken, test condition 141 is fulfilled and process computer 23 corrects the effects that the too many samples have on the matrix.

If K> 20, it means that too many samples have been taken before apex 180 due to the coarse setting of counter KSTMX. These samples can contribute to inaccuracies and their effect is therefore subtracted in an operation 143 labeled SUB 1.

This subtraction takes place in such a way that the first sample xi, yi is taken from the memory, its effects on the values for the equations (1), (2), (3) for rTo, rTi, rT> etc. are calculated and these Effects are subtracted. After the effect of the first sample xi, yi is subtracted, the sample counter K is reset by one (block 145), and then the check 141 for K> 20 is again performed by 5

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OD

guided. If the condition is met, the effect of the second sample X2, ya is calculated and subtracted, and so on until K <20. If K <20, then the x, -, y; specified values are used for the subsequent matrix calculations.

As soon as K is reduced to 20, a branch 147 for calculating the term constants according to equations (5) - (6) and (8) - (16) is followed, first a test 149 is carried out to determine whether the Calculation has already been carried out. At the beginning of the calculation process, a counter N is set to zero. A check 151 of the value of N is then made.

The first step 153 in the calculation process, when N is zero, is a normalization process. In this step, the r, and hk of equations (4) and (5) are calculated by the microprocessor of FIG. 3.

The next time it passes through branch 147, with N equal to one (block 155), the microprocessor develops the compensation constants Cj by calculating successive iterations of equations (11), (12), (13), (14), (15) and (16) as already described.

When N = 2, the microprocessor of FIG. 3 begins to cooperate with the equalization circuit 34 as follows. The microprocessor calculates equations (11) and (12) and then transmits the "r" matrix (equation 7) and other intermediate results of the calculation to the equalization circuit 34. In this way, the microprocessor gives some responsibility for the calculation to the Compensating circuit 34 from, so that the microprocessor is free to perform other operations on the incoming data. The equalization circuit 34 contains logic circuits for performing or calculating the subsequent iterations of equations (11) to (14). If N = 2, the equalization circuit only calculates equations (13) and (14). At the end of each calculation of an iteration of equations (11) to (14) in the equalization circuit (only equations (13) and (14) when N = 2), the process computer calculates the quantity Zj + 1 according to equations (15) and (16 ) and returns the calculated value to the equalization circuit 34 so that it can perform the next iteration of equations (11) to (14). This distribution of the calculation between the microprocessor and the equalization circuit has only the purpose of improving the utilization of the device. The allocation of the calculations of equations (11) to (14) to circuit parts which are assigned to the compensation circuit forms only one of the possibilities for calculating the current settings of the compensation circuit. Other options, e.g. Use of a more powerful microprocessor to perform all calculations also exist.

If N is 15, the matrix is resolved according to the term constants ck. Then the “Iterations done” mark is set. When the last term constants have been calculated, the hk are stored and the final compensation constants C |, which were determined according to the method just described, are set.

645 764

The operations just described are sufficient for the setting of 16 links. If the quality of the transmitted signal is so bad that additional links are required, then a fine-tuning process can be carried out, in which additional character intervals are transmitted from known two-phase data and the error deviations are determined and used for setting the additional links according to conventional methods.

As indicated in the above description, various modifications and adaptations of the preferred embodiment are possible.

For example, as indicated in FIGS. 9, 10 and 11, the pulse reproduction signals used by the compensation circuit can be derived in the form of signals obtained by demodulation with two carriers that are 90 ° out of phase in a band other than the baseband and in systems with different types of demodulation .

FIG. 9 illustrates a simple demodulation technique with carriers shifted by 90 °, whereby baseband signals x (6) and y (6) are obtained. In FIG. 9, the signal received on an input line 201 is fed to a first and a second mixer 203 or 205, in which the line signal is superimposed with signals cos K> ct or - sin toct, where coc is the carrier frequency. The components are then filtered through associated baseband filters 207 and 209, respectively, to obtain the baseband components x (t) and y (t).

In Fig. 10, the received signal is supplied to a first band-pass filter 211 having a pulse reproduction characteristic h (t) and a second band-pass filter 213 having a pulse reproduction characteristic h (t) which has the Hilbert transform of the pulse reproduction characteristic h (t) ) of the first filter 211. The output signals g (t) and ft (t) of the filters 2 F and 213 lie on the pass band frequency and form the signals obtainable by demodulation with carriers that are phase-shifted by 90 ° and which can be checked by the compensation circuit.

11, the output signal g (t) of the filter 211 is fed to a first mixer stage 215 and a third mixer stage 219. The output signal h (t) of the filter 2F3 is fed to a second mixer 217 and a fourth mixer 221. The signals cos coct, sin © ct, sin coct and cos \ | / ct are supplied as second input signals to the four mixer stages 215, 217, 219 and 221, where toc is the carrier frequency. The output signals of the first and second mixer stages 215 and 217 are then summed in a summing circuit 218 to obtain the demodulated baseband signal x (t). The output signal of the fourth mixer stage 221 is subtracted from the output signal of the third mixer stage 219 in a summing circuit 220 in order to obtain the demodulated baseband signal y (t). In Fig. 11, x (t) and y (t) are the signals obtained by demodulation with phase-shifted carriers, which can also be checked in the manner described for the initial adjustment of the elements of the compensation circuit.

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9 sheets of drawings

Claims (12)

645 764 2nd PATENT CLAIMS 1. Device with an equalization circuit (28; 34) for receiving a first signal transmitted through a distorting medium, which equalization circuit has a plurality of elements (30, 32, 33, 35) which compensate for the distortion of the first signal caused by the medium are adjustable, characterized by means (23) for generating a plurality of second signals (X, Y), which represent samples of pulse reproduction signals in the form of a pulse demodulated with two carriers that are 90 ° out of phase with each other, the pulse reproduction being given by the pulse reproduction characteristic of the medium and means (23) for processing the second signals (X, Y) for determining the self-correlation and cross-correlation of the second signals and forming elements of a matrix equation from the self- and cross-corrected signals, which elements contain complex constants and complex variables , where the variables are initial settings for the links mentioned ( 30,32,33,35), for iteratively calculating the exact values of the settings using said constants and for setting the terms (30,32,33,35) to the exact values mentioned in order to obtain a practically distortion-free signal (Fig. 2,3). 2. Device according to claim 1, characterized in that the means (23) for generating the second signals (X, Y) are set up to generate the second signals from the received first signal. 3. Device according to claim 2, for receiving a signal which contains a setting signal pattern (11, 13) for the device, characterized in that the means (23) for generating the second signals (X, Y) contain the following parts: means for forming the two pulse reproduction signals (Fig. 1B, IC) from the received signal and for testing the two pulse reproduction signals at successive times in order to form the second signals, and means (23; Fig. 6) for fixing the times in which the received first signal is checked, depending on the setting signal pattern. 4. Device according to claim 3, characterized in that the part of the received first signal used to form the second signals is a single received pulse (17) (Fig. 1). 5. Device according to claim 4, characterized in that it additionally contains means (23, 143, 145) for determining the second signal closest to the apex of the pulse reproduction and for subtracting the effect of individual ones of the second signals on the elements mentioned depending on the determined position (Fig. 8th). 6. Device according to claim 4, characterized in that the means (23; Fig. 5) for determining the presence of the setting signal pattern include the following parts: means (69, 85) for forming an arc tangent from values obtained by checking during the transmission of the set signal pattern and means (91-95) for testing successive values of the arctangent formed. 7. Device according to claim 6, for the reception of a setting signal pattern (11, 13) which contains a signal interval with carrier alone, characterized in that the means (69, 85) for forming the arctangent respond to samples which during the interval Carriers can be taken alone. 8. Device according to claim 4, characterized in that the means (23; Fig. 6) for controlling the test times contain the following parts; a test clock signal generator, means (101-109) for determining the phase angle error of the test clock signals with respect to those caused by testing during the Transmission of the setting signal pattern (11, 13) obtained samples, and means (123) for setting the phase of the test clock signal generator to compensate for the phase angle error (Fig. 6). 9. Device according to claim 8, characterized in that the means (101-109) for determining the phase angle error are set up to test successive arctangent, which are formed from successive values obtained by checking the received signal. 10. The device according to claim 9 for the reception of a setting signal pattern (11, 13) which contains a signal interval with a clock signal alone, characterized in that the means (101-109) for determining the phase angle error are set up to determine with the said testing, whether the arctangent is alone within a predetermined range for several periods of the interval with the clock signal. 11. The device according to claim 10, characterized in that the means (101-109) for determining the phase angle error are arranged to center consecutive arc tangent for the determination of the phase angle error if the arc tang is in the predetermined range during the said periods. 12. The device according to claim 10, characterized in that it additionally contains means (112-115) for determining the phase angle error in the event that the arc tangent is not in the predetermined range during said periods.