GB2074374B - Method of making field effect transistors - Google Patents

Method of making field effect transistors

Info

Publication number
GB2074374B
GB2074374B GB8112047A GB8112047A GB2074374B GB 2074374 B GB2074374 B GB 2074374B GB 8112047 A GB8112047 A GB 8112047A GB 8112047 A GB8112047 A GB 8112047A GB 2074374 B GB2074374 B GB 2074374B
Authority
GB
United Kingdom
Prior art keywords
field effect
effect transistors
making field
making
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB8112047A
Other languages
English (en)
Other versions
GB2074374A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/141,120 external-priority patent/US4343082A/en
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of GB2074374A publication Critical patent/GB2074374A/en
Application granted granted Critical
Publication of GB2074374B publication Critical patent/GB2074374B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H10D64/259—Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
GB8112047A 1980-04-17 1981-04-16 Method of making field effect transistors Expired GB2074374B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14112180A 1980-04-17 1980-04-17
US06/141,120 US4343082A (en) 1980-04-17 1980-04-17 Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device

Publications (2)

Publication Number Publication Date
GB2074374A GB2074374A (en) 1981-10-28
GB2074374B true GB2074374B (en) 1984-04-26

Family

ID=26838805

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8112047A Expired GB2074374B (en) 1980-04-17 1981-04-16 Method of making field effect transistors

Country Status (5)

Country Link
DE (1) DE3115596A1 (enExample)
FR (1) FR2481005A1 (enExample)
GB (1) GB2074374B (enExample)
IT (1) IT1135748B (enExample)
NL (1) NL8101902A (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1197926A (en) * 1981-12-16 1985-12-10 William D. Ryden Zero drain overlap and self-aligned contacts and contact methods for mod devices
DE3211761A1 (de) * 1982-03-30 1983-10-06 Siemens Ag Verfahren zum herstellen von integrierten mos-feldeffekttransistorschaltungen in siliziumgate-technologie mit silizid beschichteten diffusionsgebieten als niederohmige leiterbahnen
FR2525029A1 (fr) * 1982-04-08 1983-10-14 Commissariat Energie Atomique Procede d'isolation d'une ligne conductrice dans un circuit integre et procede de fabrication d'un transistor mos utilisant un tel procede d'isolation
US4485550A (en) * 1982-07-23 1984-12-04 At&T Bell Laboratories Fabrication of schottky-barrier MOS FETs
JPS59106172A (ja) * 1982-12-07 1984-06-19 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン 電界効果トランジスタの製造方法
JPS59210642A (ja) * 1983-05-16 1984-11-29 Hitachi Ltd 半導体装置の製造方法
US4453306A (en) * 1983-05-27 1984-06-12 At&T Bell Laboratories Fabrication of FETs

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4141022A (en) * 1977-09-12 1979-02-20 Signetics Corporation Refractory metal contacts for IGFETS

Also Published As

Publication number Publication date
FR2481005A1 (fr) 1981-10-23
DE3115596A1 (de) 1982-04-01
FR2481005B1 (enExample) 1983-10-21
NL8101902A (nl) 1981-11-16
GB2074374A (en) 1981-10-28
DE3115596C2 (enExample) 1988-04-14
IT1135748B (it) 1986-08-27
IT8121239A0 (it) 1981-04-16

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee