GB2051435A - Digital correlator - Google Patents

Abstract

Apparatus forming a correlation function in relation to a stream of data items, for example a one-bit auto-correlator for spectral analysis of an r.f. signal, has a plurality of storage devices, e.g. shift registers 2, 3, to which successive data items are directed in cyclic sequence. Exclusive-OR Multipliers 422-43m, 432-43m, 8 form products of the data items in their associated storage devices and these products are combined by multiplexers 62-6m, 14 to form the different correlation terms in counters 7, 15. By using a plurality of storage devices in parallel, the required speeds of operation of the apparatus may be reduced. The two registers are clocked by different clock phases phi A, phi B and counters 9, 10 and associated switches 11, 12 clocked by different clock phases provide an odd number of bit periods delay to produce the odd order terms, multipliers 422 etc producing the even order terms. <IMAGE>

Description

SPECIFICATION Digital correlation This invention relates to apparatus for calculating correlation functions in relation to streams of received data. More particularly, but not exclusively, it concerns the calculation of a binary autocorrelation function of an r.f.

signal, which function can be transformed to give an estimate of the power spectrum of the signal. Thus, the invention is particularly applicable in the field of radio astronomy for example.

By the binary correlation technique, an estimate of the power spectrum of an r.f. signal is formed from a digital signal comprising a series of single bits each of which represents a polarity sample of an amplitude-limited version of the r.f. signal or i.f. signal derived from the r.f. signal. The binary signal is fed to a shift register of which the stages are connected to a series of multipliers which form the products of each newly received bit and each previously received bit stored in the register. The products are summed by a series of counters the contents of which are scanned, after the desired correlation period, to give the correlation function. This function can then be converted to the r.f. power spectrum by Fourier transformation.Examples of many references concerned with this technique are "A Digital Spectral Analysis Technique and its Application to Radio Astron omy' by S. Weineb. M.I.T. Technical Report No. 412, August 30th, 1963, and "The Jodrell Bank 1024-Channel Digital Autocorrelation Spectrometer" by L. Pointon, Journal of Physics E: Scientific Instruments 1977.

In order to avoid "aliasing", i.e. the formation of ambiguities relating to the sampling and subsequent correlation, the sampling rate and hence also the clocking rate of the shift register and the counting rate is made at least equal to 2 fa where fa is the highest frequency of the band to be analysed. Since there are practical limits to the speed of operation of shift registers and counters, there is a corresponding limit on the analysing bandwidth.

Further, the number of stages of the shift register might be one or two thousand for example and given that clocking is done at say 100 MHz (i.e. in order to achieve an analysing bandwidth of 50 MHz) it will be appreciated that the power associated with the clock generation circuitry is appreciable. This limits reduction in the size and weight of the equipment used.

According to this invention there is provided apparatus for forming a correlation function in relation to a received stream of data items, the apparatus comprising a plurality of parallel storage devices, switch means for selecting the storage devices in cyclic sequence to direct respective ones of the data items into the storage devices, a plurality of multiplier arrangements connected to respective ones of the storage devices for forming products of the data items directed to the associated storage devices, combining means which has inputs connected to the multiplier arrangements and a series of outputs, and which is operable for presenting at respective ones of said outputs the data item products associated with respective terms of the autocorrelation function.

By using parallel store devices, the speeds of operation of the circuit elements and clocking rates may be reduced. This may enable low power and volume technology, e.g.

charge coupled devices or metal oxide silicon devices (MOS), to be used for the same bandwidth as has been hitherto obtained using high-speed but power consuming technology or enables greater bandwidth to be obtained using the same high speed technology.

For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made by way of example, to the accompanying drawings in which: Figure 1 is a simplified circuit diagram of a binary autocorrelator comprising two parallel shift registers, Figure 2 is a diagram for explaining the operation of Fig. 1, Figure 3 is a block diagram of an autocorrelator using three shift registers, and, Figure 4 is a diagram showing how the Fig.

1 1 circuit may be implemented as a series of add-on-micro-circuit units.

The illustrated apparatus is a binary autocorrelator for forming a series of terms N R(k) = 2 f(tn) . f(tn#k), n=o where tn is the value of a data signal D comprising a series of bits having a repetition rate F and each representing a polarity sample of a signal whose power spectrum is to be analysed.

The signal D is applied to a changeover switch 1 which operates at the rate F to apply the odd-order bits of the signal to a first shiftregister 2 and the even-order bits to a second shift-register 3. Each register has m stages where m is equal to half the number (K) of correlation function terms to be formed. The data bits are shifted into and through the registers 2 and 3 at a rate F/2 by respective clock pulse trains fA and fB which are in antiphase in relation to one another. Only the first three and the last stages of each register and the circuitry associated with those stages are shown in the drawing in detail but it will be appreciated that each register might comprise say 500 stages, the stages not shown being interconnected in a manner similar to those which are shown.

In order to obtain the even-order terms R(O), R(2), R(4) and so on of the correlation function, the output of each of all but the respective first stages of the two registers 2 and 3 is fed to one input of a respective one of a series of "exclusive or" gates 422, 423 - - - 42m, and 432,433--- 43m. The other input of each gate 4 is connected to the output of the first stage of the register 2 or 3 containing the stage with which the gate is associated. The "exclusive or" gates here act as multipliers which they are able to do since the values to be multiplied are single binary digits representing polarity samples. Clearly these gates may be replaced by other suitable multiplying or coincidence detecting elements in dependence upon the form of the signals to be processed.The output of each of the gates is fed to a respective one of a series of single stage counters 522, 523 - - 52m and 532, 533 - - 52m.

The outputs of the counters are combined by a series of multiplexing devices 62, 63 - - - 6m and then passed to a series of main counters 7. Each multiplexing device comprises a switch having two inputs connected to respective ones of the two singlestage counters which are associated with corresponding stages of the registers 2 and 3.

Thus, the inputs of multiplexing device 62 receive the outputs of counters 522 and 532, which are associated with the second stages of the shift registers 2 and 3, device 63 receives the outputs of counters 523 and 533 which are associated with the third shift register stages and so on.

Each multiplexing device switches from one of its inputs to the other to pass the signal appearing there on to its output and hence on to a respective one of the main counters 7.

In order to obtain the odd-order terms R(1), (R(3), R(5) and so on, the output of each stage of each register 2 and 3 is also fed to one input of a respective "exclusive or" gate 8. The other input of each of the gates 8 associated with a stage of the register 2 receives the output of a two-stage counter 9 while the other input of each gate associated with a stage of the register 3 receives the output of another two-stage counter 10. The counters 9 and 10 receive at their inputs alternate digits of the signal D by way of respective sampling switches 11 and 12.

A function of the counters 9 and 10 and switches 11 and 12 is to provide a delay equal to the period of an odd number of bits of signal D. This is achieved by controlling the associated switches and counters by different phased signals i.e. sampling by the switch 11 is controlled by the clock signal fB while bits are shifted through the counter 9 associated with switch 11 in synchronism with the clock signal fA. The converse occurs for counter 10 and associated switch 12, i.e. the switch 12 is controlled by clock signal fA while counter 10 receives clock signal #B Thus, a sample enter the first stage of one of the counters 9 and 10 with the arrival of a pulse of the clock signal ssB or fA and is then shifted into the second stage with the arrival of a pulse in the other clock signal after half a period of the clock signals. Thus the arrangement gives the required odd delay although it does mean that the first stage of each of the counters 9 and 10 has to be able to operate at the bit rate F of the signal D.

The outputs of the gates 8 are fed to respective single stage counters 13 and are then combined by multiplexers 14, similar to the multiplexers 62, 63 - - 6m, before being fed to respective main counters 15. The counters 15 are scanned (by a scanner which is not shown), in the appropriate sequence with the counters 7 to give the respective averaged terms of the correlation function.

Like the gates 4, the gates 8 act in this case as multipliers and can be replaced by other multiplying elements in dependence upon the signals operated upon.

Fig. 2 shows the contents of the first few stages of each of the shift registers 2 and 3, the signals passed by the sampling switches 11 and 12 and the outputs of counters 9 and 10 during the times of reception of samples i.e. bits of the signal D, to to trO. Thus, reading horizontally across from a particular sample number in the lists thereof, at the lefthand side of the diagram, it can be seen which sample number is present at the output of counter 9 or 10 and in each stage of register 2 or 3 during the same time interval.

Referring also to Fig. 1, the even order correlation terms are obtained by forming the product of the content of the first stage of each register and the content of that stage of the same register which has a number corresponding to that of the term. These products are then added into the corresponding counter 7. Thus, the first counter, i.e. the one connected to multiplexer 62 will sum the products of stage 1 and 2 contents of register 2 and the products of stage 1 and 2 contents of register 3. Thus, referring to Fig. 2, the first counter will sum the products to. t2; t2, t4; t4.

t6 and so on from register 2 and t,. t3; t3. t5 and so on from register 3. By evaluating

for K= 2, it will be seen that the given products are those required for the first even correlation function term R(2). The other even order terms are obtained in a similar way.

For the odd order terms, there are formed the products of the outputs of the counters 9 and 10 with the contents of the register stages having numbers corresponding to those of the required terms. Thus, from Fig.

2, the first of the counters 15 sums t,. t2; t3.

t4 and so on from register 2 and to t,; t2. t3 and so on from register 3. These are the products required for term R(1).

In the embodiment shown, the shift registers used in the estimation of both the even and odd values of the autocorrelation function are common and so the only additional substantial hardware involved in the parallel processing is in the pre-delay networks and the multiple first stage counters for each delay summation.

The function of the single stage counters 522, 523 - - 52m, 532, 533 - -53m and 13 is, in effect, to perform some of the counting that would otherwise be done by the counters 7 and 15 and hence to divide by two the bit rate of the signal applied to the multiplexers 6. The multiplexers in turn double the bit-rate applied to the counters 7 (because they are switching back and forth to pass first the products originating in register 2 and then those originating in register 3). Thus, by the provision of the single-stage counters, the multiplexers can be operated at the rate F/2 and the first stage of each of the counters 7 and 15 also only has to operate at this rate.

It will be appreciated that there can be more than two shift registers. As a general case, there may be K registers each having a length N/K where N is the number of correlation terms required and being clocked by respective ones of K clock signals each of which has a frequency 2fa/K Hz and being 2n/K radians shifted in phase from each other. Thus as shown in Fig. 3, there might be three registers SR1, SR2, and SR3 receiving clock signals f #2 and f3 shifted in phase by 2it/3 radians.Connected to each register are K sets (G1 to G3 in Fig. 3) of "exclusive or" gates (like the gates 422 - -42m and 432 - - 43m and 8), one of which would be associated with the correlation terms R(1), R(K+ 1) etc., the next of which would be associated with the terms R(2), R(K + 2) etc., and so on for the remaining sets. The products formed by the corresponding sets of gates are then combined by a respective one of a series of K-input multiplexers (M1, M2 and M3 in Fig. 3) before being entered into a corresponding series of main counters such as the counters 7 and 1 5.

In order to extend the reduction in the shift register clocking rate to the operating rate of the multiplexers and the countrate of the main counters, some of the counting could be done, as in the case of the apparatus of Fig.

1, by counters (C1 to C9 in Fig. 3) connected between the gates and the multiplexers. These counters would have a number of stages appropriate to the counting rate reduction required.

One of each of the K sets of "exclusive or" gates would be connected to its associated shift register in a manner similar to the gates 422-43m. Each other set, however, is preferably arranged to receive appropriately delayed samples of the signal D in a manner similar to that of the gates 8 except that, for each set, the sampling and the delay is appropriate to the correlation term being formed by that set.

Thus, if separate sampling switches (the switches S1 to S6 in Fig. 3) were provided, there would be one for each of these other sets of gates and they would be operated by respective different ones of the clock signals.

Similarly each switch in connected via a respective delay unit (D1 to D6 in Fig. 3) having a delay appropriate to the correlation term to be formed.

It will be appreciated that the delay units and sampling switches (such as D1 to D6 and S1 to S6 in Fig. 3) are not absolutely necessary. However, if they are not used, there would be needed instead arrangements for sampling the contents of the registers at appropriate times between the clock pulses applied thereto so as to pass to the sets of gates only the signals which they require for the correlation terms with which they are associated. Such sampling arrangements would combine complexity and operability at the bit rate F of the signal D-hence the illustrated arrangement using delays is considered the more advantageous.

It will be appreciated from Fig. 3 that as the number of shift registers is increased the number of interconnections becomes great and, particularly in view of this, the correlator could be implemented in the form of a series of add-on units such as that shown in Fig. 4.

These units could be in the form of intergrated circuits. Each unit would comprise a few stages, say four, of each shift register 41, 42 together with the associated gates 43 to 46 and multiplexers 47 and 48, pre-multiplex counting capacity and, if desired, some maincounter capacity 49. The required number of units are connected together in tandem so as to form the required number of shift register stages and to synchronise the clock signals for each unit and carry through to the gates of the different units the various signals re quires.

As an example, with the use of CCD devices in mind (where the maximum clocking rates might be say 20MHz) a clocking rate reduction factor of 5 is needed to give fa = 100 MHz. Therefore a parallel CCD autocorrelation processor would employ five CCD registers in parallel clocking at 20mHz, each 2sir/5 radians out of phase with the others. Each register might have say 400 stages. Of course, a complex clocking and fractional clock period delay unit would be needed.

Nevertheless, overall, there would be a substantial reduction in power consumption of the high-speed sections of the circuitry and hence scope would be given for weight and volume reductions.

As an alternative to the fine resolution, low band-width device, the principles set forth may be applied to the construction of a very high speed autocorrelator for the coarse resolution, wideband mode.

As an example a 500mHz analysing bandwidth would require an autocorrelation function to be estimated at 1 nanosecond intervals, this being equivalent to a 1 GHz clocking rate. For coarse resolution to say 2MHz, shift registers of 500 stages long would normally be required. To get the clocking rate down to say low speed MECL (Metal emitter-coupled logic) rates (100MHz), then ten parallel registers each 100 stages long would be required. Again complex clocking, delays and phasing would be required together with the ability to sample data at aperture times 1 nanosecond.

Claims (6)

1. Apparatus for forming a correlation function in relation to a received stream of data items, the apparatus comprising a plurality of parallel storage devices, switch means for selecting the storage devices in cyclic sequence to direct respective ones of the data items into the storage devices, a plurality of multiplier arrangements connected to respective ones of the storage devices for forming products of the data items directed to the associated storage devices, combining means which has inputs connected to the multiplier arrangements and a series of outputs, and which is operable for presenting at respective ones of said outputs the data item products associated with respective terms of the autocorrelation function.

2. Apparatus according to claim 1, wherein the storage devices comprise shift registers into and through which data items are shifted by means of respective clock pulse trains of different phase but the same repetition rate, which rate equals the bit-rate of the received data stream divided by the number of shift registers.

3. Apparatus according to claim 1 or 2, including delay means for presenting data items to the multiplier arrangements at times appropriate to the products to be formed by the respective multiplier arrangements.

4. Apparatus according to claim 1, 2 or 3, including a plurality of counting devices, arranged between the multiplier arrangements and the combining means.

5. Apparatus according to claim 1, 2, 3 or 4 constructed in the form of an integrated circuit unit and having terminals for enabling the storage devices of the unit to be connected in series with corresponding storage devices of another similar unit.

6. Apparatus for forming a correlation function in relation to a stream of data items, the apparatus being substantially as hereinbefore described with reference to the accompanying drawings.