GB2036492A - Digital synchronizing signal generator with variable pulse width - Google Patents

Abstract

In the prior art a digitally generated signal, especially a synchronising pulse signal for a television system, has its positive and negative going edges both timed by positive going edges of clock pulses having a frequency which is a multiple of the frequency of the required synchronising pulse. As a result, the synchronising pulse is of fixed duration or width. In the embodiment of the invention which is described, the width of the clock pulses (generated by oscillator 100) is made variable and the positive going edge 02 of the synchronising pulse f'h (output from circuit 110) is timed by one edge of a clock pulse while the negative going edge 01 of the synchronising pulse is timed by the other edge of a clock pulse. Consequently by varying the width of the clock pulses an adjustment of the interval between the positive and negative going edges of the synchronising pulse may be achieved, hence adjusting the synchronising pulse width. <IMAGE>

Description

SPECIFICATION Digital synchronizing signal generator with variable pulse width BACKGROUND OF THE INVENTION This invention relates to improvements to digital television synchronizing pulse generators.

Television synchronizing pulse generators provide the timing pulses required to synchronize the camera scanning to the television receiver and are usually generated at a central location and routed throughout the television facility. Routing the signal in this manner ensures that all video sources maintain an identical scanning rateimportant when switching from one video source to another. Thus, it can be seen that the timing of the composite synchronizing waveform is critical.

In the United States, the FCC, in conjunction with the television industry, has established standards that specify the timing of the composite synchronizing waveform and the composite video components. There are corresponding standards for other countries and other television systems.

Digital synchronizing pulse generators have been developed that produce accurate pulse edges and durations.

Such a pulse generator is described in U.S.

Patent No. 3,935,387. The pulse generator in this patent is used to generate, without a delay line, one or more pulse series in which the edges occur at very accurate and stable fixed times, while satisfying the previously mentioned television standards. This pulse generator has a clock pulse period which is equal to or an integral part of eighty times the television line frequency. The subject pulse generator is based on the fact that pulse edges may be determined substantially by the pulse generator clock pulses with the aid of a clock pulse generator that has a frequency which is high relative to the television line frequency. The clock pulse generator frequency is divided down by digital elements having great accuracy.

However, since the delay relied upon to produce the accurate pulse edges is the propogation delay of the digital elements used, pulse-widths are only available in fixed increments of, for example, 70 ns, 1 40 ns, etc. It is desirable to have the inherent accuracy of digital pulse generation techniques, with variable pulse width increments since television standards may be changed. It is also desirable to have variable synchronizing pulse widths since pulse widths tend to increase as they are passed through the various equipment in a television facility; thus, the original pulse width could be adjusted to compensate for subsequent system delays.

SUMMARY OF THE INVENTION The present invention includes a circuit for varying the synchronizing pulse width in a digitally controlled synchronizing pulse generator for television systems. The circuit uses both edges of a clock pulse to establish the edges of the synchronizing pulse. All positive transitions of the synchronizing pulse are clocked on a positive transition of the clock pulse. However, negative transitions of the synchronizing pulse is clocked through a transmission gate immediately preceding the transition which would have normally clocked it. Consequently, the negative synchronizing pulse transition occurs before it normally would and the resulting synchronizing pulse is narrowed to meet the requirements of the established standards.

It is, therefore, the object of the present invention to provide a synchronously operating digital synchronizing pulse generator which has a variable synchronizing pulse width.

The invention, both as to organization and method of operation, together with further advantages and objects thereof may best be understood by reference to the following description taken in conjunction with the following drawing figures wherein like reference numerals represent like elements. It is to be understood, however, that this embodiment is not intended to be exhausting nor limiting of the invention but is for purposes of illustration in order that others skilled in the art may fully understand the invention and principles thereof and the manner of applying it in particular use so that they may modify it in various forms.

BRIEF DESCRIPTION OF THE DRAWING In the drawing: Fig. 1 is a synchronizing pulse generator according to the prior art; Fig. 2 is a synchronizing pulse generator according to the present invention; Fig. 3A is an embodiment of the pulse width modifying circuit of the present invention; and Fig. 3B is a representation of the various waveforms present in the circuit of Fig. 3A.

DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention is best understood by first referring to Fig. 1 which is a simplified block diagram of a digital synchronizing pulse generator as taught by U.S. Patent No. 3,938,387 which is incorporated herein by reference. A similar generator is shown in the article "Synchronizing Signal Generation" by Charles W. Rhodes in the Eiectronic Engineer's Handbook, edited by Donald B. Fink, copyright by McGraw-Hill, Inc., 1975. Fig.

1 illustrates only the generation of the basic line and field rate synchronizing signals since it is well known to generate the equalizing and blanking pulses from these basic frequencies.

In Fig. 1, the output of voltage-controlled crystal oscillator 12 is connected to a divide-by40 circuit 14 which may be comprised of commercially available counters connected so as to perform the necessary frequency division. The output of frequency divider 14 is routed to divideby-525 circuit 1 6 which may be commercially available counters connected so as to perform the desired division. The output of frequency divider 14 is also routed to divide-by-2 circuit 1 8 which may be a commercially available flip-flop circuit. The output of frequency divider 1 8 is connected to another divide-by-2 circuit 20 which may also be a commercially available flip-flop circuit. The output of frequency divider 20 is one input to phase sampling circuit 22 while the other input is the color subcarrier signal generated by crystal oscillator 10.Phase sampling circuit 22 supplies an error voltage, via low pass filter 24, back to oscillator 12.

In the circuit shown in Fig. 1 the output frequency of voltage controlled oscillator 12 was sele-cted to be eighty times the horizontal or line frequency, fh, for reasons disclosed in U.S. Patent No. 3,935,387 and will, therefore, not be explained in detail here. The output of oscillator 12 (operating at 1.258741 MHz) is digitally divided by frequency dividers 14, 18 and 20 to produce pulses that cause sampling circuit 22 to sample the color subcarrier frequency of 3.579545 MHz developed by crystal oscillator 10 once every 455 cycles. The output of phase sampling circuit 22 is a voltage representing the frequency error of the oscillator 12 relative to the color subcarrier frequency.

This error voltage is fed to oscillator 12 and controls its output frequency relative to the color subcarrier frequency. The design of low pass filter 24 and the inherent stability of crystal oscillator 10 prevent oscillator 1 2 from locking to the wrong multiple of the color subcarrier frequency. Once the oscillators are phase locked, the leading edges of the fh/2 pulse from divider 20 are held coincident with the positive-going zero crossing of the subcarriercycles.

The output of frequency divider 14, which is a signal at twice the line frequency of 2fah, is connected to frequency divider 1 6 which divides the 2fh signal by 525 to produce a synchronizing signal at a frequency of 59.94 Hz which is the field or vertical frequency fva The vertical synchronizing signal is then connected to circuitry (not shown) for generating, in a conventional manner, equalizing and blanking pulses. The 2 fh signal is divided by two in frequency divider 18 to produce a synchronizing signal at the line or horizontal frequency, fh The requirements for the duration of the horizontal synchronizing pulse set forth by the EIA and FCC standards are met in the manner described in U.S.Patent No. 3,935,387, i.e., by selecting an integral multiple of eighty times fh as the output frequency of oscillator 12. The pulse edges are fixed by the positive-going transitions of the 80 fh clock pulse and the reset time and propagation delay of the frequency dividers involved.

Fig. 2 is a block diagram of a synchronizing pulse generator constructed according to the present invention. By comparing Fig. 2 to Fig. it can be seen that the 80 fh oscillator 12 has been replaced by an oscillator 100 operating at 320 fh, a divide-by-4 circuit 120 and driver or buffer circuit 1 30. Also, pulse width modifying circuit 110 has been added. These new circuit elements allow the width of the fh pulse to be varied.Pulse width modifying circuit 110 receives the horizontal synchronizing signal from frequency divider 18 and narrows its previously established pulse width by an amount determined by the width of the 320 fh pulse from oscillator 1 00. The width of the 320 fh pulse may be varied remotely while maintaining the established operating frequency of 320 fah. Oscillators of this type are conventional and will, therefore, not be described in detail herein. Those interested in the construction of such an oscillator are referred to the IC Schematic Sourcemaster by K. S. Sessions, copyright 1978 by John Wiley and Sons.The divide-by-4 circuit 120 mav be constructed of flipflops connected to perform the necessary division to produce a 80 fh clock pulse which is necessary for previously discussed reasons. The 80 fh driver circuit is a conventional current source to provide drive for the subsequent counter stages. The pulse width modifying circuit 110 receives the original horizontal synchronizing signal fah from the frequency divider 18, the 320 fh clock pulse from oscillator 100, and the 80 fh clock pulse from frequency divider 120. It processes these inputs, in a manner to be described later, to produce the modified horizontal synchronizing pulse fth.

Fig. 3A is a combination block diagram and schematic that illustrates pulse width modifying circuit 110 and shows how it connects to other parts of the synchronizing generator. Fig. 3B shows the relationship of the signals at various points in the circuit of Fig. 3A. The operating frequency of oscillator 100 was chosen to be an integer multiple of 80 fh in order to allow synchronous operation with the other sections of the synchronizing pulse generator. For the purpose of illustration, the frequency of oscillator 100 was selected to be 320 fh. The output of oscillator 100, shown as signal A in Fig. 3B, passes through inverter 200 and is then routed to D-type flip-flops 210 and 230.This 320 fh clock pulse is routed to NAND gate 250 along with the output of flip-flop 210, shown as B in Fig. 3B. The original synchronizing signal, shown as pulse edges D1 and D2 in Fig. 3B, is clocked through D-type flipflop 270 and fed to inverters 260 and 290. The synchronizing signal is then allowed through CMOS transmission gate 360 according to control signals El and E2. The resulting modified synchronizing signal, shown as pulse edges 01 and 02 in Fig. 3B, exits the circuit via latch 370.

The CMOS transmission gates mentioned above are essentially single-pole, single-throw switches formed by parallel connection of a p-type CMOS device and an n-type CMOS device. The switch "contacts" are opened and closed by a control voltage thus permitting automatic operation. Input to output of the transmission gate is a bidirectional short circuit when the inverting control terminal is low and the noninverting control terminal is high; it is an open circuit when the inverting control terminal is high and the non inverting control terminal is low. D-type flipflops 210, 230, 270, and 370 are conventional positive-edge triggered CMOS devices.Flip-flops 210 and 230 and exclusive-OR circuit 220 are connected in a conventional manner to divide the 320fh clock pulse by four to thereby produce an 80fh clock pulse, shown as signal C in Fig. 3B, and synchronize this circuit with the remainder to the synchronizing pulse generator.

In order to simplify the operation description of the present invention, the original and modified synchronizing pulses are treated as rising and falling pulse edges. In this embodiment the negative-going edge of the synchronizing pulse is modified and the positive-going edge is held constant. The signal is later inverted (by circuitry not shown) to conform with the EIA standard which specifies that the negative-going edge must be held constant.

As mentioned previosly, the edges of the synchronizing pulse are conventionally established by the 80fh pulse. However, the present invention uses both edges of the 320fh clock pulse generated by oscillator 100 to establish the edges of the output synchronizing pulse. The positivegoing edge of the output pulse is clocked on the positive-going edge of the 320fh clock pulse and the negative-going edge of the output pulse is allowed to pass through a parallel transmission gate on the negative-going edge of the 320fh clock pulse immediately preceding the positivegoing edge of the 80fh clock pulse which would have normally established the negative-going edge of the output synchronizing pulse.Thus, the negative-going edge,01, occurs before it normally would and the synchronizing pulse is narrower than that established by the 80fh clock pulse.

Referring now to Fig. 3B, t2 represents the instant at which 01 would normally occur and t1 represents that instant at which it occurs in the present invention. the point t, is variable since it is dependent upon the width of the 320fh clock pulse from oscillator 100 which is, as mentioned previously, variable.

One way in which to understand the operation of the present invention is to determine the logic level throughout the circuit at instants t1 and t2.

For the discussion which follows, positive logic is assumed (i.e., a high signal = logical 1 and a low signal = logical 0). Immediately prior tot1, the original synchronizing pulse is high, as illustrated by signal D1 in Fig. 3B, and the 80fh clock pulse is low. The 80fh pulse is directly connected to the non-inverting control terminal of transmission gate 310; consequently, the low clock pulse disables transmission gate 310 and signals are not allowed to pass through it. The low clock pulse from flip-flop 230 is inverted by inverter 240 and the resulting high holds the Q output of flip-flop 270 high. The Q output of flip-flop 270 is applied simultaneously to the input of each transmission gate after being inverted by inverters 290 and 260.Thus, there is a low logic level at the input of transmission gates 310 and 360. This low logic level is also one input to NOR gate 280. At instant t1, the 320fh clock pulse goes positive. This positive transition is connected to NAND gate 250. The other input to gate 250 is the 0 output of flip-flop 210 which is high at instant t1. These two high levels produce a low at the output of gate 250. This low is connected to NOR gate 280 and gates the low from inverter 260 through as a high. This high level is shown in Fig. 3B as the positive-going edge of pulse El which activates the noninverting control terminal of transmission gate 360. The low at the input of transmission gate 360 then passes through the gate and sets latch 370. It exits the pulse width modifying circuit as the negative-going pulse edge 01.As mentioned previously, 01 would normally be established by the positive-going edge of the 80fh clock pulse. But it has been shown in the present invention that 01 occurs earlier in time by an amount equal to the duration of the 320fh clock pulse. In the circuit shown, the duration of the 320fh clock pulse is variable over a range of approximately 100 ns; thus, the width of the output synchronizing pulse is variable from 4.6667 ys to 4.5667,us which is adequate to compensate for delays in a chain of broadcast equipment.

Considering circuit operation at instant t2, it should be kept in mind that instant t2 corresponds to the positive-going edge of the 80fh clock pulse.

In other words, instant t2 is the point at which the positive-going edge of the synchronizing pulse would normally be established by the positivegoing edge of the 80fh clock pulse. At instant t2, the original synchronizing pulse D2 is low and the 80fh clock pulse is going high. The positive-going 80fh clock pulse is inverted by inverter 240 and used to clock flip-flop 270 thereby passing the low at its D input to its Q output. This low is inverted by inverters 260 and 290 and fed to transmission gates 360 and 310, respectively. The positivegoing 80fh clock pulse is connected to the noninverting control terminal of transmission gate 310 thereby activating it and allowing the high at its input to pass to its output.This high is then fed to the output via latch 370 as a positive-going pulse edge shown as signal 02. Transmission gate 360 is disabled by the low at its non-inverting input. This low signal is indicated by signal E2 and can be derived by following the 320fh clock pulse through gates 250 and 280.

It can be seen from the foregoing description that the negative-going edge of the synchronizing pulse is established by the positive-going edge of the 320fh clock pulse immediately preceding the positive-going edge of the 80fh clock pulse. It can also be seen that the positive-going edge of the synchronizing pulse is established by the negativegoing edge of the 320fh clock pulse which produces the positive-going edge of the 80fh clock pulse.

While there has been shown and described a preferred embodiment of the present invention, it will apparent to those skilled in the art that many changes and modifications may be made without departing from the invention in its broader aspects. For example, the applications of this circuit are, of course, not limited to the television field. Any digitally generated pulse may be modified using this circuit, therefore the clock frequencies and dividing circuits may vary.

However, the operating frequency of oscillator 100 must be an integer multiple of the basic clock frequency of the circuit. The transmission gates may be replaced by other switching devices that operate in the previously described manner.

Therefore, the appended claims are intended to cover all such changes and modifications that fall within the scope of the invention.

Claims (9)

1. A circuit for modifying the pulse width of a digitally-generated signal, the circuit comprising: means for receiving the digitally-generated signals; means for generating a first clock signal having a variable pulse width; means for dividing the frequency of said first clock signal to produce a second clock signal; means for providing an output signal; means responsive to one of the edges of said first clock signal for gating one of the edges of the digitally-generated signal to said output means before it would be gated by one of the edges of said second clock signal; and means responsive to the other one of the edges of said first clock signal for gating the other one of the edges of the digitally-generated signal to said output means.

2. The circuit according to claim 1 wherein said means responsive to said one of the edges of said first clock signal comprises: single-pole, single-throw switch means responsive to a control signal; and gating means responsive to said first clock signal and the digitally-generated signal for producing therefrom a control signal for opening and closing said single-pole, single-throw switch means.

3. The circuit according to claim 1 wherein said means responsive to the other one of the edges of said first clock pulse comprises: singie-pole, single-throw switch means connected between said means for receiving the digitally generated signal and said output means for controllably switching the digitally generated signal to said output means.

4. An improved synchronously operating digital synchronizing pulse generator which includes a clock pulse generator operating art a frequency equal to or an integral multiple of eighty times the line frequency, wherein the improvement comprises: means for controllably varying the pulse width of a synchronizing signal.

5. The improved digital synchronizing pulse generator according to claim 4 wherein said means for varying the pulse width of said synchronizing signal comprises: means for receiving said synchronizing signal; means for generating a first clock signal having a variable pulse width and a frequency equal to an integer multiple of eighty times the television line frequency; means for dividing the frequency of said first clock signal to produce a second clock signal at eighty times the television line frequency; output means for providing said synchronizing signal;; means responsive to one of the edges of said first clock signal for gating one of the edges of said synchronizing signal to said output means before it would be gated by one of the edges of said second clock signal, and means responsive to the other one of the edges of said first clock signal for gating the other one of the edges of the synchronizing signal to said output means.

6. The improved digital synchronizing pulse generator according to claim 5 wherein said means responsive to said one of the edges of said first clock signal comprises: single-pole, single-throw switch means responsive to a control signal; and gating means responsive to said first clock and said synchronizing signal for producing therefrom said control signal for opening and closing said single-throw, single-pole switch means.

7. The improved digital synchronizing pulse generator according to claim 5 wherein said means responsive to the other one of the edges of said first clock signal comprises: single-pole, single-throw switch means connected between said means for receiving said synchronizing signal and said output means for controllably switching said synchronizing signal to said output means.

8. The improved digital synchronizing pulse generator according to claim 6 or 7 wherein said single-pole, single-throw switch means comprises a transmission gate.

9. The circuit according to claim 2 or 3 wherein said single-pole, single-throw switch means comprises a transmission gate.

1 0. A synchronizing pulse generator substantially as hereinbefore described with reference described with reference to Figures 2, and 3A and 38 of the accompanying drawings.