GB2034899A - Improvements in electrical test apparatus - Google Patents
Improvements in electrical test apparatus Download PDFInfo
- Publication number
- GB2034899A GB2034899A GB7844773A GB7844773A GB2034899A GB 2034899 A GB2034899 A GB 2034899A GB 7844773 A GB7844773 A GB 7844773A GB 7844773 A GB7844773 A GB 7844773A GB 2034899 A GB2034899 A GB 2034899A
- Authority
- GB
- United Kingdom
- Prior art keywords
- output
- control
- switches
- input
- coupled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
A test apparatus for measuring electrical parameters of electronic circuits comprises a control/data processing unit (1) having outputs connected to a plurality of electronic testing boards (2) each corresponding to a respective lead (3) of the circuit to be tested. Each testing board (2) includes four switch networks (8, 9, 10 and 11) and an output switch network (6) all of which are controlled by means of a control network (4) which in turn is controlled by an output (5) of the control/data processing unit (1). Buffer amplifiers (16, 16') receive inputs from the control/data processing unit (1) directly and also via residual voltage compensation networks (17, 18) serially connected respectively with switch networks (8, 10), and have feedback paths including switch networks (9, 11) respectively, and provide outputs to the inputs (49, 50) of output switch network (6). Relay switches (21 to 27) are controlled by the control/data processing unit (1) selectively to connect a load (20) to lead (3), to connect a comparison network (19) between lead (3) and the control/data processing unit (1), etc. By appropriate programming of the control/data processing unit (1) different operating modes of the testing boards (2) can be selected for performing different kinds of tests on a device or circuit connected to the leads (3). <IMAGE>
Description
SPECIFICATION
Improvements in electrical test apparatus
This invention relates to improvements in electrical test apparatus, and particularly though not exclusively relates to apparatus for measuring the electrical parameters of electronic circuits for the purpose of testing the circuit operation. The apparatus according to the invention is particuiarly though riot exclusively suitable for testing electronic circuits during the manufacture of microelectronics devices, for example for performing d.c. measurements and functional tests at extreme test rates upon LSI circuits employed in internal storages and microprocessors.
According to the invention there is provided electrical test apparatus comprising a control unit having outputs connected to control a plurality of electronic testing boards each corresponding to a respective lead of an electronic device or circuit to be tested, each of said electronic testing boards comprising:- four controllable switches; a controllable output switch network arranged to provide for a coupling of one or other of two inputs thereof to a respective lead of an electronic device or circuit under test; a control network having outputs coupled to control inputs of said four controllable switches and of the output switch network and having an input coupled to a first output of the control unit; and two buffer amplifiers; said controllable output switch network having each of its two inputs coupled to a respective one of second and third outputs of the control unit via a respective serial arrangement incorporating a respective one of the buffer amplifiers and a respective one of the said four controllable switches, a fourth output of the control unit being coupled to a second input of one of said buffer amplifiers and a fifth output of the control unit being coupled to a corresponding second input of the other of said buffer amplifiers, and each of said buffer amplifiers having a feedback circuit including a respective one of said four controllable switches connected between the output and a third input thereof.
In an exemplary embodiment of the invention which is hereinafter described, each of said electronic testing boards had a plurality of relays arranged to be switched by the control unit. The output switch network has its output coupled via one of said relays to a first communication line to provide for a coupling to a respective lead of an electronic circuit under test, and its control input is connected to a respective output of the control unit which has another output coupled directly to the first communication line via another relay.A load is connected, via another relay, to a second communication line to provide for coupling of said load to said lead of the test electronic circuit, and a comparison network having an input coupled to the second communication line via yet another relay, has an output coupled to a respective input of the control unit which has another input coupled directly to the second communication line via yet another relay.
The two inputs of the output switch network are each coupled via a respective capacitor to chassis, and also are each coupled to a respective output of the control unit via a serial arrangement of a respective buffer amplifier and a respective residual voltage compensation network. Another output of the control unit is coupled to an input of each buffer amplifier which has yet another input coupled via a respective first resistor to its output.
The control network provides for coupling between a respective output of the control unit and the control input of the output switch network, and has outputs coupled to the control inputs of the four additional controllable switch networks. A first and a second of the latter are each inserted between the output of a respective one of the residual voltage compensation networks and the input of the buffer amplifier connected thereto, and a third and a fourth each provide for a feedback coupling between the output of a respective buffer amplifier and its respective input, being inserted between the output of the respective buffer amplifier and the lead of the first resistor which is coupled, via a serial arrangement of a second resistor and yet another relay, to the second communication line.
The invention will best be understood from consideration of the following detailed description given with reference to the accompanying drawing which illustrates a block diagram of an exemplary embodiment of the invention.
The apparatus of the invention comprises a control/data processing unit 1 which connects to a plurality of electronic testing boards 2 each coupled to a respective lead 3 of the electronic circuit or device under test. The control/data processing unit 1 employs circuitry which provides control signals which determine the coupling of electronic testing boards 2 to respective leads 3 of the electronic circuit under test and which determine the required operating modes for the testing boards 2.
Each electronic testing board 2 comprises a control network 4 having its input coupled to an output 5 of the control/data processing unit 1; an output switch network 6 whose control input is coupled to an output 7 of the control network 4; and switch networks 8, 9, 1 0 and 11 having their control inputs coupled, respectively, to outputs 12, 13, 14 and 15 of the control network 4. Each electronic testing board 2 also comprises buffer amplifiers 1 6 and 16', residual voltage compensation networks 1 7 and 18, a comparison network 19, a load 20, relays 21, 22, 23, 24, 25, 26 and 27 controlled by the control/data processing unit 1, resistors 28, 29, 30 and 31, and capacitors 32 and 33.
The control network 4 utilizes logic gates and produces at its output 12,13, 14 and 15, according to the input signals applied to it, voltage signals applied in a given succession to the control inputs of the switch networks 8, 9, 10 and 11.
The output of the output switch network 6 is coupled, via the relay 21, to a first communication line 34 to provide a coupling to the lead 3 of the electronic circuit under test. An output 35 of the control/data processing unit 1 is coupled, via the relay 22, to the first communication line 34, while an input 36 of the control/data processing unit 1 is coupled via the relay 25 to a second communication line 37. The second communication line 37 is coupled to the lead 3 and is coupled, via the relay 23, to the load 20 and, via the relay 24, to the input of the comparison network 1 9 whose output is connected to an input 38 of the control/data processing unit 1.
An output 39 of the control/data processing unit 1 is coupled to an input 40 of the buffer amplifier 1 6 via a serial arrangement of the residual voltage compensation network 1 7 and the switch network 8, while an output 41 of the control/data processing unit 1 is coupled to an input 42 of the buffer amplifier 16' via a serial arrangement of the residual compensation network 18 and the switch network 10.
An output 43 of the control/data processing unit 1 is coupled to an input 44 of the buffer amplifier 1 6, while an output 45 of the control/data processing unit 1 is coupled to an input 46 of the buffer amplifier 1 6'.
The output of the switch network 9 is coupled, via the resistor 28, to an input 47 of the buffer amplifier 16 and, via the resistor 30 and the relay 26, to the second communication line 37.
The output of the switch network 11 is coupled, via the resistor 29, to an input 48 of the buffer amplifier 16' and, via the resistor 31 and the relay 27, to the second communication line 37.
The output of the buffer amplifier 1 6 is coupled to an input 49 of the output switch network 6, to the input of the switch network 9 and, via the capacitor 32, to chassis.
The output of the buffer amplifier 16' is coupled to an input 50 of the output switch network 6, to the input of the switch network 11 and, via the capacitor 33, to chassis.
The apparatus of the invention provides for d.c.
measurements and dynamic tests, as well as for functional tests, at extreme test rates.
In the case of functional tests at extreme test rates, the relay 21 is closed using a signal delivered from a respective output of the control/data processing unit 1.
To apply voltage signals of the required level to the lead 3 of the test electronic circuit, that lead 3 is coupled to the output of the output switch network 6 via the first communication line 34 and via the relay 21.
When a signal obtainable from the output 5 of the control/data processing unit 1 is applied to the input of the control network 4, the outputs 1 2, 13, 14 and 1 5 produce signals to close the switch networks8,9, and 11.
A high level voltage signal comes to the input 44 of the buffer amplifier 1 6 from the output 43 of the control/data processing unit 1, while a low level voltage signal obtainable from the output 45 of the control/data processing unit 1 is applied to the input 46 of the buffer amplifier 16'.
When the next signal from the output 5 of the control/data processing unit 1 is delivered to the input of the control network 4 the output of the latter provides a signal which tends to close alternately the swiches A and B of the output switch network 6 with the result that the outputs of the buffer amplifiers 1 6, 1 6' are connected in succession to the output of the output switch network 6 depending on the level, high or low, of the voltage to be applied to the lead 3 of the electronic circuit under test.
After a respective switch A or B is closed, the voltage of the corresponding level obtained from the output of buffer amplifier 1 6 or 1 6' is applied to the lead 3 of the electronic circuit under test via the output switch network 6 and the closed relay 21.
As required, the load 20 and the comparison network 19 can be connected during the test process to the lead 3 via the second communication line 37 and via the relays 23 and 24 which can be closed by a signal from the control/data processing unit 1.
In the case of d.c. measurements and-dynamic tests, a respective output of the control/data processing unit 1 delivers a signal to close relay 26 or 27.
The formation of the high level signal is as follows. Depending on the signals from the output 5 of the control/data processing unit 1, the control network 4 provides on its outputs 7, 12, 13, 14 and 1 5 signals that tend to break the switch networks 8 and 9 and the switch B of the output switch -network 6, with the result that the output of the buffer amplifier 16' is disconnected from the relay 21, as well as signals that tend to make the switch networks 10 and 11 and the switch A of the output switch network 6, thereby resulting in the connection of the buffer amplifier 1 6 to the relay 21.
The voltage from the output of the buffer amplifier 1 6 is applied to the lead 3 of the electronic circuit- under test via the closed switch
A of the output switch network 6 and via the relay 21.
The same voltage is applied to the input 47 of the buffer amplifier 1 6 via the second communication line 37, the closed relay 26 and the resistors 30, 28.
Voltage transfer constant K for a path between the input 44 of the buffer amplifier 1 6 and the lead 3 of the test electronic circuit is given by
where R0 is the input impedance of the buffer amplifier 1 6 referred to the feedback circuit;
R28 is the resistance of the resistor 28, and
R30 is the resistance of the resistor 30.
With Ro) R30 +R28, 1.
The feedback circuit therfore provides for compensation of the residuatvoltages that appear across the transistors of the output switch network 6, across the relay 21, and in the first communication line 34.
The error with which the required voltage level is set at the lead 3 for a given operating mode does not exceed 0.1 /0.
When the high level voltage is produced, the residual voltage compensation network 1-7 is switched off by operating the switch network 8.
This is due to the fact that in this case compensation is attained with the help of a feedback circuit incorporating the buffer amplifier 1 6 and the output switch network 9.
At the moment when the switch A of the output switch network 6 is closed, a voltage of a certain level exists across the capacitor 32 part of which is the residual voltage across the transistors of the output switch network 6. This condition is achieved due to the fact that the switch networks 8 and 9 are maintained in the closed state before making the switch A. As a result, the error with which the high level voltage is set at the output of the output switch network 6, at the moment when the switch A of this network is closed, is equal to about 2% and the time within which the voltage is transferred through the feedback circuit is reduced to a few microseconds.
Since the residual voltage compensation network 1 7 is switched on before the high level voltage is formed, and is switched off at the moment when the switch A is closed, the high and low level voltages are produced with'a greater accuracy and the transfer rate between the two levels is high. This transfer rate (the output voltage rise time) is determined by the speed of operation of the switches A and B of the output switch network 6 and can amount to only a few nanoseconds.
The resistor 30 in the feedback circuit serves to eliminate the influence of the low level voltage on the production of the high level voltage.
The low level voltage is produced in a manner similar to that described above. The only difference is that the signals from the outputs 7, 12, 13, 14 and 15 of the control network 4 are used to open the switch networks 10 and 11 and the switch A of the output switch network 6, with the result that the output of the buffer amplifier 1 6 is disconnected from the relay 21, and are also used to make the switch networks 8 and 9 and the switch B of the output switch network 6 so that the output of the buffer amplifier 1 6' is connected to the relay 21.
The resistor 31 in the feedback circuit also serves to eliminate the influence of the high level voltage on the production of the low level voltage.
In the case of d.c. measurements of the voltage across and currents through the lead 3 of the electronic circuit under test, the output 35 and the input 36 of the control/data processing unit 1 are coupled, via the relays 22 and 25 respectively, to the lead 3.
In the case of dynamic tests, the comparison network 1 9 is connected to the lead 3 via the relay 24. Also, the load 20 can be connected to the lead 3 via the-relay 23.
The present invention has an advantage that a voltage of a precise level can be applied concurrently to several leads 3 of the test electronic circuit This provides for8n increase in the test rate during d.-c. measurements and-for better noise immunity of the test process since the means-for forming the precise voltage level are located in close proximity to the lead 3.
Simultaneous connection- of several (or all) leads 3 to the electronic testing boards 2 (the condition which is necessary in conducting d.c.
measurements on some integrated circuits on a complete basis) makes it possible to use effectively the proposed apparatus at extreme test rates for d.c. measurements and functional tests of the integrated circuits of internal storages and microprocessors.
Claims (12)
1. Electrical-test- apparatus comprising a control unit having outputs connected to control-a plurality of electronic testing boards each corresponding to a respective lead of an electronic device or circuit to be tested, each of said electronic testing boards comprising:- four controllable switches; a controllable output switch network arranged to provide for a coupling of one or other of two inputs thereof to a respective lead of an electronic device or circuit under test a control network having outputs coupled to control inputs of said four controllable switches and of the output switch network and having an input coupled to a first output of the control unit; and two buffer amplifiers; said controllable output switch network having each of its two inputs coupled to a respective one of second and third outputs of the control unit via a respective serial arrangement incorporating a respective one of the buffer amplifiers and a respective one of the said four controllable switches, a fourth output of the control unit being coupled to a second input of one of said buffer amplifiers anda fifth output ofthe control unit being coupled to a corresponding second input of the other of said buffer amplifiers, and each of said buffer amplifiers having a feedback circuit including a respective one of said four controllable switches connected between the output and a third input thereof.
2. Apparatus as claimed in claim 1 wherein each.of said electronic testing boards further comprises two residual voltage compensation networks each connected in a respective one of said serial arrangements.
3. Apparatus as claimed in claim 1 or 2 wherein each of said electronic testing boards further comprises a plurality of output switches the condition whereof is controlled by said control unit.
4. Apparatus as claimed in claim 3 wherein said output switches comprise relay switches.
5. Apparatus as claimed in claim 3 or 4 wherein said controllable output switch network has an output connected via a first one of said plurality of output switches to a communication line for providing for said coupling to a respective lead of an electronic device or circuit under test.
6. Apparatus as claimed in claim 5 wherein said control unit has an output coupled directly to said communication line via a second one of said plurality of output switches.
7. Apparatus as claimed in claim 5 or 6 wherein a second communication line is provided for coupling to said lead of the electronic device or circuit under test, a load being connected to said second communication line via a third one of said output switches to provide for the coupling of said load to said lead of the electronic device or circuit under test, a comparison network having an input connected to said second communication line via a fourth one of said output switches and having an output connected to an input of said control unit, and a further input of said control unit being connected directly to said second communication line via a fifth one of said output switches.
8. Apparatus as claimed in any of claims 3 to 7 wherein a respective one of said plurality of output switches is provided for coupling between said lead of the electronic device or circuit under test and the output of each of said controtlable switches included in said feedback circuits.
9. Apparatus as claimed in any of the preceding claims wherein each of the two inputs of said controllable output switch network is coupled via a capacitor to ground potential.
10. Apparatus claimed in any of the preceding claims wherein each of said feedback circuits includes a resistance.
11. Apparatus as claimed in any of the preceding claims wherein said control unit comprises a data processor programmed to control the operation of said testing boards according to the nature of the test or tests to be preformed.
12. Electrical test apparatus substantially as herein described with reference to the accompanying drawing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB7844773A GB2034899B (en) | 1978-11-16 | 1978-11-16 | Electrical test apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB7844773A GB2034899B (en) | 1978-11-16 | 1978-11-16 | Electrical test apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2034899A true GB2034899A (en) | 1980-06-11 |
| GB2034899B GB2034899B (en) | 1982-12-01 |
Family
ID=10501092
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB7844773A Expired GB2034899B (en) | 1978-11-16 | 1978-11-16 | Electrical test apparatus |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2034899B (en) |
-
1978
- 1978-11-16 GB GB7844773A patent/GB2034899B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB2034899B (en) | 1982-12-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| USRE31056E (en) | Computer controlled high-speed circuit for testing electronic devices | |
| US4092589A (en) | High-speed testing circuit | |
| US5617035A (en) | Method for testing integrated devices | |
| EP0364925A1 (en) | Semiconductor integrated circuit having i/o terminals allowing independent connection test | |
| EP0091375A2 (en) | Programmable deskewing of automatic test equipment | |
| EP0650069A2 (en) | Analog multi-channel probe system | |
| US4490673A (en) | Testing an integrated circuit containing a tristate driver and a control signal generating network therefor | |
| US4686627A (en) | Electrical test apparatus | |
| US4694242A (en) | Integrated circuit tester and remote pin electronics therefor | |
| EP0838689B1 (en) | Test of circuits with Schmitt inputs | |
| US5225774A (en) | Semiconductor integrated circuit | |
| JP2000162284A (en) | Semiconductor integrated circuit | |
| GB2034899A (en) | Improvements in electrical test apparatus | |
| JP3555953B2 (en) | Apparatus for testing connections with pulling resistors | |
| US5826004A (en) | Input/output device with self-test capability in an integrated circuit | |
| JP3191791B2 (en) | Probe card | |
| JPS5882346A (en) | Automatic correction for pin electronics interface circuit within electronic tester | |
| US4879661A (en) | Bi-directional circuit to interface between a low current device and high current tester | |
| US5023545A (en) | Circuit probing system | |
| US3599101A (en) | Solid state direct current tester for microcircuits | |
| JPH11304880A (en) | Semiconductor testing device | |
| JPH0650786Y2 (en) | IC test equipment | |
| KR930006962B1 (en) | Semiconductor testing method | |
| US6411115B2 (en) | Apparatus for testing a semiconductor and process for the same | |
| JPS6230971A (en) | Semiconductor integrated circuit device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |