GB2031163A

GB2031163A - Method of testing

Info

Publication number: GB2031163A
Application number: GB7839318A
Authority: GB
Original assignee: MIN RADIOTEKH INST; MOSKOV VYSSHEE TEKH UCHILIS IM
Current assignee: MIN RADIOTEKH INST; MOSKOV VYSSHEE TEKH UCHILIS IM
Priority date: 1978-10-04
Filing date: 1978-10-04
Publication date: 1980-04-16
Also published as: GB2031163B

Abstract

A method of testing a device forming one member of a set of similar devices each of which in use receives signals, comprises the following steps:- (a) a typical device of the set is observed over a period of normal use and the signals that it receives are recorded, (b) various statistical characteristics, including the spectral density, of the recorded signals are calculated, (c) by a rectroactive process, random signals are generated having the same statistical characteristics as those calculated in (b) above, and (d) the generated random signals of (c) above are applied to a device to be tested and its response is analysed. m

Description

SPECIFICATION Method of testing objects for random actions thereon and digital simulator-computer system for effecting same The present invention relates to control computers and more particularly to methods of testing different objects for random actions upon these objects, as well as digital simulator-computer systems for effecting such methods, which systems comprise digital controlled simulators of random actions, operating in conjunction with digital computers.

The present invention essentially consists in providing a method for testing objects for random actions, comprising: recording random actions to which an object is subjected in the course of operation; determining the spectral composition and statistical characteristics of the recorded random actions upon the object; reproducing the random actions in the form of a simulating random pulse process with amplitudes, durations and polarities of pulses, and with intervals between pulses being random parameters adequate to the recorded random actions as regards their spectral and statistical characteristics;; applying the reproduced random actions to the object being tested, whereby, in accordance with the invention, a totality of pulse forms is selected and the simulating random pulse process is formed as a train of pulses of different shapes selected from a predetermined combination of pulse shapes; forming statistically independent random parameters of pulses; analyzing the spectral and statistical characteristics of the reproduced random actions and the response to these actions of the object being tested; correcting the characteristics of the simulating random pulse process by varying its probability characteristics.

It is expedient that pulses of the simulating random pulse process should be modulated by a harmonic signal possessing a statistically independent random amplitude, phase and frequency.

It is also expedient that pulses of the simulating random pulse process should be modulated by a converted combination of harmonic signals possessing statistically independent random amplitudes, phases and frequencies.

It is necessary that a digital simulator-computer system for effecting the foregoing method should comprise: a control computer intended to produce deterministic test signals and to control units of the system; an interface unit intended to conjugate said control computerwith the system's units, whereof one input and one output are connected to said control computer; a main forward channel comprising at least one digital-to-analog converter and connected to another output of the interface unit; a main feedback channel comprising at least one analog-to-digital converter and connected to another input of the interface unit; a test bed intended to transmit test actions to the object being tested and electrically coupled to the forward and feedback channels;; the system further including, in accordance with the invention, an auxiliary forward channel comprising at least one digital controlled simulator of random actions, intended to reproduce random actions upon the object as a simulating random pulse process and connected to the interface unit; an auxiliary feedback channel comprising at least one digital multifunctional statistical analyzer intended to statistically analyze the reproduced random actions right in the course of testing objects and connected to an input of the interface unit, the test bed being electrically coupled to the main-and auxiliary forward channels and the main and auxiliary feedback channels through respective distribution devices.

It is highly desirable that the output of the auxiliary feedback channel should be connected to a respective input of the auxiliary forward channel.

According to the invention, the digital controlled simulator of random actions may include in series: a memory intended for storing codes determining the type and numerical characteristics of distribution functions of random parameters of pulses of the simulating random pulse process, its respective inputs being connected to the output of the interface unit and the output of the additional feedback channel; a random numbers transducer intended to form codes of random numbers corresponding to specific amplitude, duration and polarity values of pulses, as well as durations of intervals between pulses, whose input and output are connected to the respective output and input of the memory;; a control unit intended to synchronize operation of all the units of the digital controlled random actions simulator and ensure an exchange of information between the units of said digital controlled random actions simulator, an input and an output of said control unit being connected to a respective output and a respective input of said memory; a pulse counter intended to store a random code determining the duration of a time interval between pulse signals of the simulating random pulse process and converting that code to a time interval, an input of said pulse counter being connected to a respective output of said random numbers transducer; a generator of variable recurrence frequency pulses, intended to produce a f!ow of clock pulses to fill the pulse counter and set the frequency of the output pulse signal flow of the digital controlled random actions simulator;; a reference voltage source intended to set an amplitude distribution range of pulse signals formed by the digital controlled random actions simulator, which reference voltage source is electrically coupled to a number-to-voltage converter intended to convert the code determining the amplitude of pulse signals to a voltage corresponding to that amplitude and distributed within the amplitude distribution range; ed to a respective input of the control unit, whereas the input of said reversible counter is connected to a respective output of the control unit; a second pulse generator intended to form a flow of clock pulses whose frequency is equal to a maximum frequency at which said reversible counter is filled; a frequency divider intended to set the rate at which the reversible counter is filled with clock pulses, said frequency divider being interposed between the second pulse generator and the input of the reversible counter;; a second register intended to store a code corresponding to the duration of the base of the isosceles triangle-shaped pulse and determining the repetition frequency of clock pulses filling said reversible counter, the output of said second register being connected to the input of the frequency divider, whereas its inputs are connected to the output of the random numbers transducer and the output of the control unit.

According to the invention, the digital controlled simulator of random actions may also include: a cyclic shift register intended for storing a code determining the sequence of changing the polarity sign of a group of pulses at the output of the digital controlled random actions simulator; a cycle length control unit intended for setting the number of pulses in a group of successive pulses at the output of the digital controlled random actions simulator, the input and output of said cycle length control unit being connected to a respective output and a respective input of the reversible counter, whereas the output of said cycle length control unit is also connected to respective inputs of the cyclic shift register, said digital controlled random actions simulator further including a flip-flop, two conjunctors and a disjunctor, intended to ensure separate transmission of codes from the output of the shift register to the polarity modulator, the output of the disjunctor being connected to the input of the polarity modulator, the output of each of the conjunctors being connected to the input of the disjunctor, their first inputs being connected to the output of the flip-flop, whereas their second inputs are connected to the output of the cyclic shift register, the reversible counter being electrically coupled to the second number-to-voltage converter via a second memory intended for storing codes of ordinates of a pulse of a prescribed shape, its input being connected to the output of the reversible counter, said digital controlled random actions simulator still further including a second flip-flop, two conjunctor units and a disjunctor unit, intended to ensure separate transmission of codes from the outputs of the reversible counter and the second memory to the input of the second number-to-voltage converter, the output of the disjunctor unit being connected to the input of the second number-to-voltage converter, the output of each of the conjunctor units being connected to the input of the disjunctor unit, their first inputs being connected to the output of the second flip-flop, a second input of one of said conjunctor units being connected to the output of the reversible counter, whereas a second input of the second conjunctor unit is connected to the output of the second memory, the output of the second memory also being connected to the input of the first conjunctor to ensure separate transmission of codes from said memory to said polarity modulator.

According to the invention, the digital controlled random actions simulator may also include: a second reversible counter intended to form a linearly changing code sequence, its inputs being respectively connected to the output of the random numbers transducer and the output of the control unit, whereas the output of said second reversible counter is connected to'a respective input of the polarity modulator; a digital functional converter intended to convert the linearly changing input code sequence to a non-linear code sequence determining the shape of a signal modulating the envelope of the pulse signal formed by the digital controlled random actions simulator, the input of said digital functional converter being connected to a respective output of the second reversible counter;; one more register intended for setting the amplitude of the modulating signal, its inputs being connected to the output of the random numbers transducer and the output of the control unit, respectively; a third and fourth number-to-voltage converters, each connected with its input to the output of the third register and the output of the digital functional converter, respectively, both number-to-voltage converters being placed in series and interposed betweeen the output of the reference voltage source and the input of the first number-to-voltage converter; a third pulse generator intended to generate clock pulses whose frequency is equal to a maximum frequency at which the second reversible counter is filled; ; a second frequency divider intended to set a frequency at which the second reversible counter is filled with clock pulses, said second frequency divider being interposed between the respective pulse generator and the input of the second reverisble counter; a fourth register intended for storing a code determining the frequency at which the second reversible counter is filled with clock pulses, inputs of said fourth register being connected to a respective output of the random numbers transducer and the output of the control unit, whereas the output of said fourth register is connected to the input of the second frequency divider.

It is preferable that the digital controlled random actions simulator should include: harmonic oscillators intended to set a desired Fourier spectrum of pulses of the simulating random pulse process, their outputs being combined; initial conditions registers intended for storing predetermined initial phases of harmonic oscillations, their outputs being connected to inputs of the respective harmonic oscillators; a first distributor intended for setting frequencies of harmonic oscillations at the outputs of the harmonic oscillators, its groups of outputs being respectively connected to inputs of the respective harmonic oscillators, whereas its separate output is connected to inputs of the harmonic oscillators;; a second distributor intended to enter in the initial conditions registers the codes determining the initial phases of harmonic oscillations, its group of outputs being connected to inputs of the respective initial conditions registers, whereas its outputs are connected to inputs of the harmonic oscillators and the input of the first distributor; a result accumulator intended for non-linear conversion of harmonic oscillations; a synchronization unit, its group of inputs being connected to a respective group of outputs of the result accumulator, its input being connected to the output of the first distributor, whereas its outputs are connected to the input of the first distributor and respective inputs of the result accumulator whose input is connected to the outputs of the harmonic oscillators;; a pulse generator intended to form a first train of clock pulses from a reference train of pulses, the frequency of said first train of clock pulses determining the duration of a pulse at the output of the digital controlled random actions simulator; a first frequency divider intended to form a first train of clock pulses from a reference train of pulses; a second frequency divider intended to form a second train of clock pulses from the reference train of pulses, which second train of clock pulses determines the area of random values of time intervals between the leading edges of adjacent pulses at the output of the digital controlled random actions simulator;; a frequency division factor codes register whose output is connected to one input of each of the two frequency dividers, the output of one of the frequency dividers being connected to a respective input of the result accumulator and the input of the first distributor, whereas the output of the pulse generator is connected to the inputs of the two frequency dividers and the input of the synchronization unit; a first memory intended for storing codes determining the distribution pattern of the random value of the time interval between the leading edges of adjacent pulse at the output of the digital controlled random actions simulator; a random numbers transducer intended to produce random codes with a predetermined distribution function;; a first pulse counter intended to convert the random code to a time interval, the output and the input of the first memory being connected to a respective input and a respective output of the random numbers transducer, another input of said random numbers transducer and the input of the first pulse counter being combined and connected to the output of the first distributor, the outputs of the random numbers transducer also being connected to respective inputs of the initial conditions register and the input of the first pulse counter whose input is connected to the output of the second frequency divider, the output of the first pulse counter also being connected to the input of the second distributor; a decoder intended to additionally enter codes in the initial conditions registers;; a second memory intended for storing codes determining the spectral power density of the random pulse process at the output of the digital controlled random actions simulator; a second pulse counter intended for setting cell addresses of the memories for entering information in said cells; a commutator intended to enter codes in the memories through two independent channels, its inputs being respectively connected to the output of the interface unit and the output of the auxiliary feedback channel, its outputs being connected to the input of the second pulse counter, the input of the frequency division factor codes register, the input of the first memory, the input of the second memory, the input of the second distributor and the inputs of the initial conditions registers, the output of the second pulse counter being connected to the input of the first memory, the input of the second memory and the input of the decoder whose group of outputs is connected to the inputs of the initial conditions registers, whereas its outputs are connected to respective inputs of the second distributor and the input of the frequency division factor codes register, the input of the second memory also being connected to a respective output of the first distributor, whereas its output is connected to the input of the result accumulator; a number-to-voltage converter intended for analog representation of the simulating random pulse process, its output being connected to the input of the first distributor;; an actual process value code register whose output is connected to the input of the number-to-voltage converter, its inputs being connected to the output of the result accumulator, the output of the second distributor, a respective output of the first distributor, and the input of the second distributor.

It is further preferable that each harmonic oscillator of the digital controlled random actions simulator should include: a conjunctor intended to control the harmonic oscillator through two-inputs; a reversible counter intended to form a linearly changing code sequence; a code converter intended to convert the linearly changing code sequence to a sinusoidally changing sequence, and a multiplexer intended to combine the outputs of the harmonic oscillators, the inputs of the conjunctor being connected to the outputs of the first distributor, the output of the conjunctor being connected to the input of the reversible counter which is also connected to the initial conditions registers and the second distributor, the output of the reversible counter being connected to the input of the code converter whose output is connected to the input of the multiplexer which is also connected to the output of the first distributor, the output of the multiplexer being connected to the input of the result accumulator.

It is advisable that the first distributor of the digital controlled random actions simulator should include: a shift register intended to produce a system of potentials to control the frequencies of the harmonic oscillators; a fli-flop, three conjunctors and a disjunctor, the input of the shift register being combined with the input of the first conjunctor, the output of the shift register being connected to the inputs of the harmonic oscillators and the input of the first conjunctor, the outputs of the first and second conjunctors being respectively connected to the inputs of the disjunctor one of whose inputs is connected to the output of said distributor, whereas the output of the disjunctor is connected to the input of the flip-flop;; a pulse counter intended for form a code setting the number of a harmonic oscillator, its input being connected to the combined inputs of the shift register and the first conjunctor, as well as to the output of the third conjunctor connected to the inputs of the harmonic oscillators, the input of the third conjunctor being connected to the output of the flip-flop and the output and input of the synchronization unit, the inputs of the second conjunctor being connected to the output of the result accumulator, the output of the second distributor, the input of the shift register, the output of the flip-flop and the input of the pulse counter;; a decoder intended to produce signals to control the multiplexer, its input being connected to the output of the counter and the input of the second memory, whereas the outputs of the said decoder are connected to the inputs of the harmonic oscillator.

It is desirable that the second distributor of the digital controlled random actions simulator should include: a pulse counter; a first conjunctor and a decoder intended to form signals for entering information in the initial conditions registers, its inputs being connected to the output of the first conjunctor and the output of the pulse counter, whereas the output of said decoder is connected to the inputs of the initial conditions register; a register intended for storing a code determining the duration of a pulse of the random pulse process at the output of the digital controlled random actions simulator; a comparison circuit intended to set an instant of time corresponding to the trailing edge of the pulse of the random pulse process at the output of the digital controlled random actions simulator;; a first flip-flop whose output is connected to a respective input of the first conjunctor, one input of the flip-flop and one input of the register being combined and connected to the output of the commutator, another input of the register being connected to the output of the decoder of the digital controlled random actions simulator, inputs of the comparison circuit being connected to the output of the register and the output of the pulse counter, another input of the first flip-flop being connected to the output of the decoder of the digital controlled random actions simulator;; a second flip-flop, two more conjunctors and a disjunctor, inputs of the second conjunctor being connected to the output of the pulse counter of the digital controlled random actions simulator and the output of the second flip-flop, whereas the output of the said second conjunctor is connected to the input of the disjunctor and the inputs of the harmonic oscillators, the inputs of the third conjunctor being connected to the output of the comparison circuit, the input of the first conjunctor, the input of the pulse counter and the output of the first distributor, whereas the output of said third conjunctor is connected to the input of the actual process value code register and the input of the disjunctor whose output is connected to the input of the second flip-flop whose output is also connected to a respective input of the first conjunctor, the input of the counter and the input of the first distributor.

It is advisable that the result accumulator of the digital controlled random actions simulator should include: a first register for storing codes of actual amplitude values of harmonic oscillations; an arithmetic logical unit intended for non-linear conversion of codes of the harmonic oscillators;; a second register intended for storing intermediate results of non-linear conversion, the inputs of the first register being connected to the outputs of the harmonic oscillators and the output of the synchronization unit, its output being connected to the input of the arithmetic logical unit whose output is connected to one of the inputs of the second register whose two other inputs are connected to the output of the synchronization unit and the output of the first frequency divider, whereas its output is connected to the input of the arithmetic logical unit and the input of the actual process value code register; a first flip-flop intended for storing the polarity sign code ofthe harmonic oscillation; a second flip-flop intended for storing the sign code of the factor by which the amplitude of the harmonic oscillation is multiplied; ; a modulo two adding circuit intended to form an attribute of an operation performed by the arithmetic logical unit, the inputs of the first register being connected to the input of the first register, a respective input of the second flip-flop and the output of the synchronization unit, the inputs of the modulo two adding circuit being respectively connected to the outputs of the two flip-flops, whereas the output of said modulo two adding circuit is connected to the input of the arithmetic logical unit; One more register intended for storing the code of a factor by which the harmonic oscillation amplitude is multiplied, its inputs being connected to the inputs of the second flip-flop and the output of the second memory, whereas its outputs are connected to respective inputs of the synchronization unit.

It is further advisable that the synchronization unit of the digital controlled simulator of random actions should include: two flip-flops and two conjunctors intended to form two non-overlapping pulse trains; a first disjunctor whose output is connected to the input of the first flip-flop connected with its output to the input of the second flip-flop and a respective input of the first disjunctor, the output of the second flip-flop being connected to the first inputs of the first and second conjunctors whose other inputs are combined and connected to the input of the second flip-flop, the output of the first conjunctor being connected to the input of the result accumulator; a shift register intended to form a sequence of control potentials;; one more conjunctor and a second disjunctor intended to form signals to control operation of the result accumulator, the output of said conjunctor being connected to the input of the first distributor, whereas its input is connected to one of the inputs of the shift register whose second input is connected to the output of the first flip-flop, the output of the second conjunctor, the input of the first disjunctor and the input of the result accumulator, the outputs of the shift register being respectively connected to the inputs of the second disjunctor, the input of the third conjunctor and the input of the first disjunctor, the inputs of the second disjunctor also being connected to the outputs of the result accumulator, while the latter's output is connected to the input of the first conjunctor;; four more conjunctors and one more flip-flop, the output of the fourth conjunctor being connected to the input of the second flip-flop, whereas one input of said fourth conjunctor is connected to the input of the second fiip-flop, the input of the third flip-flop being connected to the input of the fifth conjunctor and the output of the first flip-flop, the output of the fifth conjunctor being connected to a respective input of the first disjunctor, the input of the sixth conjunctor being connected to the input of the fourth conjunctor and the output of the pulse generator, the input of the seventh conjunctor being connected to the input of the third flip-flop, the input of the fifth conjunctor and the output of the sixth conjunctor, the input of the seventh conjunctor being connected to the output of the third flip-flop whose output is connected to the input of the fifth conjunctor, the inputs of the sixth conjunctor being connected to a respective input of the seventh conjunctor, the output of the first flip-flop and the output of the first distributor, the output of the seventh conjunctor being connected to the input of the result accumulator.

The present invention makes it possible to simplify the control and test equipment; it speeds up and facilitates tests of objects, carried out in actual operating conditions; it provides for a simpler control of characteristics of reproduced random actions; finally, the invention makes it possible to automate testing procedures and make the testing conditions more compatible with the actual operating conditions of objects being tested.

A better understanding of the present invention may be had from a consideration of the following detailed description of a preferred embodiment thereof, taken in conjunction with the accompanying drawings, wherein: Figure lisa block diagram of a digital simulator-computer system in accordance with the invention; Figure 2 is a block diagram of a digital controlled random actions simulator in accordance with the invention, which ensures the formation of pulse signals of an arbitrary shape; Figure 3 is a block diagram of a digital controlled random actions simulator in accordance with the invention, which ensures the formation of pulse signals modulated by either harmonic signals with a random and statistically independent amplitude, phase and duration, or a combination of harmonic signals;; Figure 4 is a block diagram of an alternative embodiment of the digital controlled random actions simulator in accordance with the invention; Figure 5 is a block diagram of a harmonic oscillator in accordance with the invention; Figure 6 is a block diagram of the first distributor in accordance with the invention; Figure 7 is a block diagram of the second distributor in accordance with the invention; Figure 8 is a block diagram of a result accumulator in accordance with the invention; Figure 9 is a block diagram of a synchronization unit in accordance with the invention; Figure 10 is an illustration of a simulating random pulse process with isosceles triangle-shaped pulses having a random amplitude A, a random duration X and a random polarity, as well as random intervals T between pulses.

The proposed simulator-computer system comprises a control computer 1 (Figure 1) and an interface unit 2 whose input 3 and output 4 are connected to the control computer 1. The system further includes a forward channel comprising at least one digital-to-analog converter 5 connected to a second input 6 of the interface unit 2, and a feedback channel comprising at least one analog-to-digital converter7 connected to a third input of the interface unit 2.

The system still further includes a test bed 9, an auxiliary forward channel comprising at least one digital controlled simulator 10 of random actions, whose input 11 is connected to a second output of the interface unit 2, and an auxiliary feedback channel comprising at least one digital multifunctional statistical analyzer 12 connected to an input 13 of the interface unit 2.

The system also includes a distribution device 14 whose output is connected to an input 15 of the test bed 9, whereas inputs 16 and 17 of said distribution device 14 are connected to outputs of the digital-to-analog convertor 5 and the digital controlled random actions simulator 10, respectively. The system then includes a second distribution device 18 whose input 19 is connected to an output of the test bed 9, while its outputs are connected to an input 20 of the digital multifunctional statistical analyzer 12 and an input 21 of the analog-to-digital converter 7, respectively. An input 22 of the digital controlled random actions simulator 10 is connected to another output of the digital muitifunctional statistical analyzer 12.

The digital controlled random actions simulator 10 (Figure 2) comprises in series a memory 23, a random numbers transducer 24, a control unit 25, a pulse counter 26, and a pulse generator 27. An input 28 and an output of the memory 23 are respectively connected to an output and an input 29 of the random numbers transducer 24. An input 30 and an output of the memory 23 are respectively connected to an output and an input 31 of the control unit 25. Inputs of the memory 23 are the inputs 11 and ?2, respectively, of the digital controlled random actions simulator 10.

An input 32 and an output of the random numbers transducer 24 are respectively connected to an output and an input 33 of the control unit 25. An output and an input 34 of the control unit 25 are respectively connected to an input 35 and an output of the pulse counter 26 whose input 36 is connected to an output of the pulse generator 27.

The digital controlled random actions simulator 10 further includes a reference voltage source 37, a number-to-voltage converter 38 whose input 39 is connected to an output of the reference voltage source 37, a number-to-voltage converter 40 whose input 41 is connected to an output of the number-to-voltage converter 38, and a polarity modulator 42 whose input 43 is connected to an output of the converter 40. An input 44 of the modulator 42 is connected to the output of the source 37, whereas its output is the output of the digital controlled random actions simulator 10 which still further includes a register 45 whose first output is connected to an input 46 of the converter 38, while its second output is connected to the input 47 of the polarity modulator 42.An input 48 of the register 45 is connected to another output of the random numbers transducer 24, whereas its input 49 is connected to another output of the control unit 25. The simulator 10 also includes a reversible counter 50. One of the latter's outputs is connected to ;In input 51 of the control unit 25. Another output of the control unit 25 is connected to an input 52 of the reversible counter 50. The simulator 10 then includes a pulse generator 53, a frequency divider 54, and a register 55 whose output is connected to an input 56 of the frequency divider 54 whose input 57 is connected to an output of the pulse generator 53, whereas its output is connected to an input 58 of the reversible counter 50. An input 59 of the register 55 is connected to an input 60 of the pulse counter 26.An input 61 of the register 55 is connected to a respective output of the control unit 25.

The reversible counter 50 is electrically coupled to the number-to-code converter 40 via a memory 62, a flip-flop 63, conjunctor units 64 and 65 and a disjunctor unit 66. An input 67 of the conjunctor unit 64 is connected to another output of the reversible counter 50 and an input 68 of the memory 62, an input 69 of said conjunctor unit 64 being connected to an output of the flip-flop 63, whereas its output is connected to an input 70 of the disjunctor unit 66 whose output is connected to an input 71 of the number-to-voltage converter 40. An input 72 of the conjunctor unit 65 is connected to a respective output of the memory 62, an input 73 of said conjunctor unit 65 being connected to another output of the flip-flop 63, whereas an output of said conjunctor unit 65 is connected to an input 74 of the disjunctor unit 66.The digital controlled random actions simulator 10 further includes a cyclic shift register 75 and a cycle length control unit 76 whose input 77 is connected to a respective output of the reversible counter 50, whereas two of its outputs are connected to inputs 78 and 79 of the cyclic shift register 75, its third output being connected to an input 80 of the reversible cou'nter 50. The simulator 10 further includes a flip-flop 81, conjunctors 82 and 83 and a disjunctor 84. An input 85 of the conjunctor 82 is connected to a respective output of the memory 62, its input 86 being connected to an output of the flip-flop 81, whereas its output is connected to an input 87 of the disjunctor 84 whose output is connected to an input 88 of the polarity modulator 42.An input 89 of the conjunctor 83 is connected to the output of the flip-flop 81, its input 90 being connected to an output of the cyclic shift register 75, whereas its output is connected to an input 91 of the disjunctor 84.

Figure 3 illustrates an embodiment of the digital controlled random actions simulator 10 which comprises a reversible counter 92 whose input 93 is connected to a respective output of the random numbers transducer 24. An input 94 of said reversible counter 92 is connected to a respective output of the control unit 25, whereas one of its outputs is connected to an input 95 of the polarity modulator 42. The simulator 10 also includes a digital functional converter 96 whose input 97 is connected to an output of the reversible counter 92.The simulator 10 further incorporates a register 98 whose input 99 is connected to a respective output of the random numbers transducer, while its output 100 is connected to a respective output of the control unit 25, The simulator 10 further includes a number-to-voltage converter 101 whose input 102 is connected to an output of the reference voltage source 37, while its input 103 is connected to an output of the register 98. The simulator 10 still further includes a number-to-voltage converter 104 whose input 105 is connected to an output of the number-to-voltage converter 101, its input 106 being connected to an output of the digital functional converter 96, whereas its output is connected to the input 39 of the number-to-voltage converter 38.

The digital controlled random numbers simulator 10 also comprises a pulse generator 107 and a frequency divider 108 whose input 109 is connected to an output of the pulse generator 107, whereas its output is connected to an input 110 of the reversible counter 92. The simulator 10 then contains a register 111 whose input 112 is connected to a respective output of the random numbers transducer 24, its input 113 being connected to a respective output of the control unit 25, while its output is connected to an input 114 of the frequency divider 108.

According to another preferred embodiment, the digital controlled random actions simulator 10 comprises harmonic oscillators 1151, 1152 . . ., 11 58 (Figure 4) having combined outputs, and initial conditions registers 1161, 1162 . ~ ., 1168 168 whose outputs are connected to inputs l17i, 1172 .. .,11781178 of the respective harmonic oscillators 115, 1152 ~~ ~r 1 ...,1158. The simulator 10 also includes a distributor 118 of which a first group of outputs is connected to inputs 1 l9i, 1192 1198 of the respective harmonic oscillators llSi, 1152 1158, whereas a second group of outputs is connected to inputs l2Oi, 1201,1202..., 1208 . .,1208 of the respective harmonic oscillators 1151, 1152, . ..,1158, whereas a separate output of said distributor 118 is connected to inputs 1211, 1212, ...,1218 of the harmonic oscillators 1151, 1152,... 1158.

The simulator 10 also includes a distributor 122, whereof a group of outputs is connected to inputs 1231, 1232 1 . ., 1238 of the respective registers 11 6i, 1162 . . 1 1688 one of its outputs being connected to inputs l24i, 1242 . . ., 1248 1248 of the harmonic oscillators 1 15i, 1152 . . 1158, whereas its other output is connected to an input 1241 of the distributor 118. The simulator 10 further includes a result accumulator 125 and a synchronization unit 126, whereof a group of inputs 1 27i, 1272 1278 is connected to a respective group of outputs of the result accumulator 125.Outputs of the synchronization unit 126 are connected to inputs 128, 129 and 130, respectively, of the result accumulator 125 whose input 131 is connected to the outputs of the harmonic oscillators 1 15i, 1152 . . ., 1158. An output of the synchronization unit 126 is connected to an input 132 of the distributor 118, whereas an input 133 of the synchronization unit 126 is connected to the output of the distributor 118. The simulator 10 also includes a pulse generator 134, a frequency divider 135, a frequency divider 136 and a frequency division factor codes register 137. An output of the pulse generator 134 is connected to inputs 138 and 139, respectively, of the frequency dividers 135 and 136 and to an input 140 of the synchronization unit 126. An output of the register 137 is connected to inputs 141 and 142, respectively, of the dividers 135 and 1 36.An output of the frequency divider 135 is connected to an input 143 of the result accumulator 125 and an input 144 of the distributor 118.

The simulator 10 further includes a memory 145, a random numbers transducer 146 and a pulse counter 147. An output and an input 148 of the memory 145 are respectively connected to an input 149 and an output of the random numbers transducer 146. An input 1 50 of the random numbers transducer 146 and an input 151 of the counter 147 are combined and connected to the output of the distributor 122. Another output of the random numbers transducer 146 is connected to an input 152 of the counter 147 whose input 153 is connected to an output of the frequency divider 136. An output of the counter 147 is connected to an input 154 of the distributor 122. The simulator 10 further comprises a decoder 155, a memory 156, a pulse counter 157 and a commutator 158 whose inputs are connected to the inputs 11 and 22, respectively, of the simulator 10.A first output of said commutator 158 is connected to an output 159 of the counter 157, whereas its second output is connected to an input 1 60 of the register 137, an input 161 of the memory 145, and input 162 of the memory 156, and inputs 163 and 164i, 1642 1648 of the distributor 122 and the registers 1161,1162, 1168, respectively. An output of the counter 157 is connected to an input 156 of the memory 145, an input 166 of the memory 156 and an input 1 67 of the decoder 155 whose group of outputs is connected to inputs 1 68i, 1682 . . ., 1688, respectively, whereas two separate outputs of said decoder 155 are connected to inputs 169 and 170 of the distributor 122, still another output of said decoder 155 being connected to an input 171 of the register 137.An input 172 of the memory 156 is connected to a respective output of the distributor 118.

An output of the memory 156 is connected to an input 173 of the result accumulator 125. The last output of the random numbers transducer 146 is connected to inputs l74i, 1742 1748 of the registers 116a, 1162, ....

1168.

The simulator 10 further includes a number-to-voltage converter 175 whose output is connected to the output of the simulator 10, and an actual process value code register 176 whose output is connected to an input 177 of the converter 175. An input 178 of the register 176 is connected to th# e output of the result accumulator 125, an input 179 of said register 176 is connected to a respective ot tput of the distributor 122, and its input 180 is connected to a respective output of the distributor 118 and an input 181 of the distributor 122.

Each of the harmonic oscillators 11 Si, 1152 .. ~ 1 158 comprises a conjunctor 18.? (Figure 5), a reversible counter 183, a code converter 184 and a multiplexer 185. Inputs of the conjunctor 182 are connected, for example, to the inputs 1 191, 121, of the harmonic oscillator 11 so. An output of the conjunctor 182 is connected to an input 186 of the reversible counter 183 whose inputs are connected to the inputs 124i and 1 171, respectively, of the harmonic oscillator 1151.An output of the reversible counter 183 is connected to an input 187 of the code converter 184 whose output is connected to an input 188 of the multiplexer 185 whose input is the input 1207 of the harmonic oscillator 11 5i, whereas an output of said nultiplexer 185 is the output of said harmonic oscillator 1151.

The distributor 118 (Figure 6) comprises a shift register 189, a flip-flop 190, conjunctors 191, 192 and 193 and a disjunctor 194. An input 195 of the register 189 is connected to an input 196 oftheconjunctor 191.

Outputs of the register 189 are connected to a respective group of outputs of the distributor 118. One output of the register 189 is connected to an input 197 of the conjunctor 191. Outputs of the conjunctors 191 and 192 are connected to inputs 198 amd 199 of the disjunctor 194. The input 198 of the disjunctor 194 is also connected to a respective output of the distributor 118. An output of the disjunctor 194 is connected to an input 200 of the flip-flop 190.

The distributor 118 further includes a pulse counter 201 whose input 202 is connected to the input 195 of the register 189, the input 196 of the conjunctor 191 and the output of the conjunctor 193 connected to the output of the distributor 118. An input 203 of the conjunctor 193 is connected to an output 204 of the flip-flop 190 and the output of the distributor 118. One input of the conjunctor 193 is connected to the input 1 32 of the distributor 118. An input 205 of the counter 201, an input 206 of the conjunctor 192 and an input 207 of the register 189 are combined and connected to a respective output of the flip-flop 190. One input of the conjunctor 192 is connected to the input 144 of the distributor 118; another input of said conjunctor 192 is connected to the output 124' of the distributor 118.The latter still further includes a decoder 208 whose input 209 is connected to an output of the counter 201 and a respective output of the distributor 118. Outputs of the decoder 208 are connected to a respective group of outputs of the distributor 118.

The distributor 122 (Figure 7) comprises a conjunctor 210, a decoder 211, and a pulse counter 212. An input 213 of the decoder 211 is connected to an output of the conjunctor 210. An input 214 of said decoder 211 is connected to an output of the pulse counter 212. Outputs of the decoder 211 are connected to a group of outputs of the distributor 122 which further includes a register 215, a comparison circuit 126 and a flip-flop 217 whose output is connected to an input 218 of the conjunctor 210. An input 129 of the flip-flop 217 and one input of the register 215 are combined and connected to the input 163 of the distributor 122. Another input of the register 215 is connected to the input 170 of the distributor 122. An input 220 of the comparison circuit 216 is connected to an output of the register 215.An input 221 of said comparison circuit 216 is connected to an output of the pulse counter 212. An input of the flip-flop 217 is connected to the input 169 of the distributor 122 which also includes a flip-flop 222, conjunctors 223 and 224 and a disjunctor 225. One input of the conjunctor 223 is connected to the input 154 of the distributor 122. An input 226 of said conjunctor 223 is connected to a respective output of the flip-flop 222. An output of the conjunctor 223 is connected to an input 227 of the disjunctor 225 and a respective output of the distributor 122. An input 228 of the conjunctor 224 is connected to the output of the comparison circuit 216. An input 229 of saja conjunctor 224 is connected to an input 230 of the conjunctor 210, an input 321 of the pulse counter 212 and the input 181 of the distributor 122.

An output of the conjunctor 224 is connected to an input 232 of the disjunctor 225 and a respective output of the distributor 122. An output of the disjunctor 225 is connected to an input 233 of the flip-flop 222 whose other output is connected to an input 234 of the conjunctor 210, an input 235 of the counter 212 and a respective output of the distributor 122.

The result accumulator 125 (Figure 8) comprises a register 236, an arithmetic logical unit 237 and a register 238. Inputs of the register 236 are connected to the inputs 131 and 129, respectively, of the result accumulator 125. An output of said register 236 is connected to an input 239 of the arithmetic logical unit 237 whose output is connected to an input 240 of the register 238 whose inputs are connected to the inputs 143 and 130, respectively, of the result accumulator 125. An output of the register 238 is connected to an input 241 of the arithmetic logical unit 237 and an output of the result accumulator 125 which further includes a flip-fiop 242, a flip-flop 243 and a modulo two adding circuit 244.An input of the flip-flop 242 is connected to an input of the flip-flop 243, a respective input of the register 236 and the input 128 of the result accumulator 125. Inputs 245 and 246 of the circuit 244 are respectively connected to outputs of the flip-fiops 242 and 243, whereas an output of said circuit 244 is connected to an input 247 of the arithmetic logical unit 237.

Another input of the flip-flop 242 is connected to the input 131 of the result accumulator 125 which still further includes a register 248 whose inputs are connected to the inputs 128 and 173, respectively, of the result,accumulator 125.

Outputs of the register 248 are respectively connected to outputs of the result accumulator 125.

The synchronization unit 126 (Figure 9) comprises flip-flops 249 and 250, conjunctors 251 and 252 and a disjunctor 153 whose output is connected to an input 254 of the flip-flop 249. An output of said flip-flop 249 is connected to an input 255 of the flip-flop 250. Another output of said flip-flop 249 is connected to an input 256 of the disjunctor 253.

Outputs of the flip-flop 250 are connected to inputs 257 and 258 of the conjunctors 251 and 252, respectively. Inputs 259 and 260 of said conjunctors 251 and 252, respectively, are combined and connected to an input 261 of the flip-flop 250. An output of the conjunctor 251 is connected to a respective output of the synchronization unit 126 which further includes a shift register 262, a conjunctor 263 and a disjunctor 264.

An output of the conjunctor 263 is connected to a respective output of the synchronization unit 126. An input 265 of said conjunctor 263 is connected to an input 266 of the register 262, an output of the conjunctor 252, an input 267 of the disjunctor 253 and the output of the synchronization unit 126.

Outputs of the register 262 are connected to inputs 268" 2682 ..., 2688 of the disjunctor 264. One output of the register 262 is connected to an input 269 of the conjunctor 263 and an ir out 270 of the disjunctor 253.

Other inputs of the disjunctor 264 are connected to the inputs 127" 1272,... 1278 of the synchronization unit 126, whereas an output of said disjunctor 264 is connected to an input 271 e the conjunctor 251. An input 272 of the register 262 is connected to an output of the flip-flop 249.

The synchronization unit 126 further includes conjunctors 273 and 274 and a fiip-flop 275. An input 276 of the conjunctor 273 is connected to an output of the flip-flop 249. An output of the conjunctor 273 is connected to the input 261 of the flip-flop 250.

An input 277 of the flip-flop 275 is connected to an input 278 of the conjunctor 274 and a respective output of the flip-flop 249. An output of the conjunctor 274 is connected to an input 279 of the disjunctor 253.

The synchronization unit 126 still further includes conjunctors 280 and 281. An input of the conjunctor 280 is connected to a respective input of the conjunctor 273 and the input 140 of the synchronization unit 126.

An input 282 of the conjunctor 281 is connected to an input 283 of the flip-flop 275 and an input 284 of the conjunctor 274, as well as an output of the conjunctor 280. An input 285 of the conjunctor 281 is connected to an output of the flip-flop 275 whose second output is connected to an input 286 of the conjuntor 274. An input 287 of the conjunctor 280 is connected to an input 288 of the conjunctor 281 and a respective output of the flip-flop 249. Another input of the conjunctor 280 is connected to the input 133 of the synchronization unit 126. An output of the conjunctor 281 is connected to a respective output of the synchronization unit 126.

The proposed digital simulator-computer system makes it possible to test objects and articles for reliability, durability, survival and other parameters when subjected to the effects of random, deterministic or mixed actions similar to those that are encountered in the course of operation.

Prior to testing, random actions, whereto an object is subjected in the course of operation, are recorded on an information carrier. The volume of information on the recorded actions is determined by the desired accuracy of reproducing the spectral and statistical characteristics while simulating these actions. The information on the recorded actions is entered in the control computer 1 (Figure 1) in order to determine the spectral composition and statistical characteristics of these actions. The calculated spectral composition and statistical characteristics of the recorded actions serve as the initial data for calculating the parameters for adjusting the digital controlled random actions simulator 10 incorporated in the auxiliary forward channel.

The control computer 1 can select any operating mode for the digital controlled random actions simulator 10, which makes it possible: to simulate a random pulse process, wherein the amplitude, duration and polarity of pulses and the duration of intervals between pulses are random parameters whose spectral and statistical characteristics are adequate to those of the recorded random actions; to simulate a random pulse process as a train of pulses of an arbitrary shape with random and independent pulse signal parameters; to simulate a random pulse process as a train of pulses modulated by harmonic signals with a random end statistically independent amplitude, phase and frequency; to simulate a random pulse process as a train of pulses modulated by a combination of harmonic signals with a random and statistically independent amplitude, phase and frequency.

Upon adjusting the digital controlled random actions simulator 10, the random pulse process is applied via the switching device 14 to the input of the test bed 9. In order to adjust the random actions' characteristics, the simulating random pulse process is applied from the output of the test bed 9 via the distribution device 18 to the input of the auxiliary feedback channel which performs the spectral and statistical analysis of the random process. The results of the spectral and statistical analysis are applied from the output of the auxiliary feedback channel via the interface unit 2 to the control computer 1 and serve to correct the adjustment of the digital controlled random actions simulator 10, which operation is carried out by the auxiliary forward channel.In some cases, it is possible to adjust the digital controlled random actions simulator 10 right from the output of the multifunctional statistical analyzer 12 incorporated in the auxiliary feedback channel.

Thus by varying the probability characteristics at the input of the test bed 9, it is possible to adjust the characteristics of the simulating pulse process at the output of said test bed 9.

Operation of the proposed digital simulator-computer system will be considered with reference to the following three basic modes: reproduction of deterministic actions upon an object; reproduction of random actions upon an object; reproduction of mixed actions upon an object.

In the course of operation of the proposed digital simulator-computer system, a number of closed control loops are brought into play.

The first closed control loop is intended to reproduce deterministic actions and comprises the control computer 1, the interface unit 2, the main forward channel 5, the first distribution device 14, the test bed 9, the second distribution device 18, the main feedback channel 7, the interface unit 2 and the control computer 1.

The second closed control loop is intended to reproduce random actions and comprises the control computer 1,the interface 2, the auxiliary forward channel comprising at least one digital controlled random actions simulator 10, the first distribution device 14, the test bed 9, the auxiliary feedback channel comprising at least one digital multifunctional statistical analyzer 12, the interface unit 2 and the control computer 1.

The third closed control loop is intended to reproduce random actions and comprises the auxiliary forward channel comprising at least one digital controlled random actions simulator 10, the first distribution device 14, the test bed 9, the second distribution device 18 and the auxiliary feedback channel comprising at least one digital multifunctional statistical analyzer 12.

The fourth closed control loop is intended to reproduce mixed actions upon an object being tested end comprises all the units of the digital simulator-computer system in accordance with the invention.

Deterministic actions can be reproduced, for example, by argument quantization of a preset time function, coding the samples values of the preset time function and representing this function as a sequence of codes formed or stored by the control computer.

When simulating a preset time function, the code sequence is transmitted via the interface unit 2 to the forward channel 5 which converts it, for example, to voltage levels which are applied by the distribution device 14 to the input of the test bed 9. Units (not shown) of the test bed 9 convert the voltage levels to signals which approximately, but with a desired accuracy, reproduce the predetermined time function.

Signals of control and measuring instruments (not shown) of the test bed 9 are applied via the distribution device 18 to the feedback channel 7 which converts them to code sequences transmitted by the interface unit 2 to the control computer 1.

Thus deterministic loads are fully reproduced by the first closed control loop of the proposed digital simulator-computer system.

Referring to the simulation of random actions, consider first operation of the second closed control loop in the case of reproducing a non-stationary random process with the distribution density of the simulating random pulse process changing over equal periods of time.

At the beginning of each of the equal periods of time, the control computer 1 readjusts, through the interface unit 2, the digital controlled random actions simulator 10, which operation is carried out by the auxiliary forward channel. As a result, the simulating random pulse process has a desired distribution density during each of the equal periods of time. The output signals of the auxiliary forward channel are transmitted by the distribution device 14 to the input of the test bed 9. From the output of the test bed 9, the signals are applied via the distribution device 18 to the input of the auxiliary feedback channel which performs a preliminary statistical analysis of the supplied information and sends the results of the preliminary analysis to the control computer 1 via the interface unit 2.The use of the multifunctional statistical analyzer 12 in the auxiliary feedback channel speeds up the analysis, which, in turn, extends the frequency range of processes subject to analysis and thus expands the functional potentialities of the system.

If necessary, the control computer 1 can, on the basis of the results of the preliminary statistical analysis, adjust the characteristics of the output process of the auxiliary forward channel.

Thus random actions are fully reproduced by the second closed control loop of the proposed digital simulator-computer system.

Consider operation of the third closed control loop of the system, which is intended to switch off the control computer 1 for the testing period. Let it be assumed that in the course of simulating random actions there is formed a train of triangular pulses having random amplitudes, durations and polarities and recurring over random time intervals. All the foregoing parameters possess a desired distribution function.

After the digital controlled random actions simulator 10 has been adjusted by the auxiliary forward channel, the digital simulator-computer system starts reproducing random actions with the third closed control loop working off-line.

Under such operating conditions, the auxiliary feedback channel transmits the results of the analysis to the auxiliary forward channel, which makes it possible to automatically adjust the p.irameters of the simulating random pulse process at the output of the auxiliary forward channel and bring them closer to the rated values, for example, a minimum peak load, random actions dispersion, mathematical expectation period and other parameters.

While performing tests, the commonest operating mode of the system is the reproduction of random actions by the third control loop, when the control computer 1 is disconnected from the digital simulator-computer system for the off-line operation period of the third control loop. This also helps to raise the utilization factor of the proposed digital simulator-computer system.

The reproduction of complex test programs including areas of deterministic actions, stationary random actions and non-stationary random actions, for example, in cases of a variable mathematical expectation period of the simulating random pulse process, calls for the use of all the units incorporated in the digital simulator-computer system. When reproducing deterministic and stationary random actions, the system operates in the first and second modes, respectively. Consider therefore the reproduction of a simulating random pulse process with a controlled mathematical expectation mi(t) set as a time function.The control computer 1 calculates adjustment parameters of the digital controlled random actions simulator 10, which is done by the auxiliary forward channel; the parameters to be calculated are selected so that the output random process of said simulator 10 should have a constant mathematical expectation, m2(t) = m2 = const Via the interface unit 2, the control computer 1 then adjusts the digital controlled random actions simulator 10 and forms a deterministic time function m3(t) = m1 (t) - m2. Subsequent operation of the digital simulator-computer system is fully in correspondence and stationary random actions upon an object being tested; signals from the outputs of both forward channels are added together by the first distribution device 14 from whose output to the input of the test bed 9 there is applied a non-stationary random process with a predetermined variation of the mathematical expectation mt(t).

Thus the proposed digital simulator-computer system reproduces mixed actions.

The proposed digital simulator-computer system makes the testing conditions more compatible with the actual operating conditions of objects subjected to testing, as compared to other systems intended to serve similar purposes, which is due to the use of the digital controlled random actions simulator 10 and the digital multifunctional statistical analyzer 12. The units 10 and 12 reproduce with a desired accuracy the statistical and spectral characteristics of the simulating random pulse process and recorded random actions under actual operating conditions.

The testing of objects in operating conditions is made faster and easier by making the testing conditions, simulated by the proposed digital simulator-computer system, more compatible with the actual operating conditions of objects being tested.

The control of parameters of reproduced actions upon an object being tested is simplified by forming statistically independent random parameters of pulses of the simulating random pulse process, as well as by the use in the simulating random pulse process of pulses of different shapes selected from a preset combination of pulse shapes.

Thus the proposed digital simulator-computer system provides for a high effectiveness of testing, as well as a high utilization factor of the control and testing equipment.

Consider now operation of different embodiments of the digital controlled random actions simulator 10.

Prior to the start of operation of the digital controlled random actions simulator 10, a sequence of codes is entered in the first memory 23 (Figure 2), which codes determine the type and numerical characteristics of random parameters distribution functions of pulses of the simulating random pulse process.

Each operational cycle of the digital controlled random actions simulator 10 starts with forming a group of random numbers which set the amplitude and duration values of pulses, as well as the value of intervals between pulses. At this stage, the control unit 25, intended to synchronize operation of and ensure interaction between all the units of the system, successively connects the random numbers transducer 24 to different regions of the first memory 23. First, the random numbers transducer 24 is connected to the region for storing codes for setting the pulse amplitude distribution pattern, then to the region for storing codes for setting the pulse duration distribution pattern, and, finally, to the region for storing codes for setting the distribution pattern for intervals between pulses.The first number of the group of random numbers determines the amplitude A (Figure 10) of the pulse signal being formed, and is entered, by a signal from the control unit 25, in the first register 45.

The second random number determines the duration of the pulse signal and is entered, by a signal from the control unit 25 (Figure 2), in the register 55. The third random number determines the duration T (Figure 10) of intervals between the formed pulse signals and is entered, by a signal from the control unit 25 (Figure 2), in the pulse counter 26.

First, at the output of the reference voltage source 37 there is set a voltage level equal to a maximum amplitude value of the formed pulse signals. According to the code of the random numbers entered in the first register 45, at the output of the first number-to-voltage converter 38 there are formed voltage levels ranging from zero to the maximum value set at the output of the reference voltage source 37.

In the initial state, the reversible counter 50 contains zero code. As the reversible counter 50 is filled from zero to the maximum value, at the output of the second converter 40 there is formed a leading edge of a triangular pulse signal. The reversible counter 50 is filled at a constant frequency of input pulses, so the increments in the output voltage of the second converter 40 are also constant, hence, the leading edge of the formed triangular pulse signal is shaped as a slanted straight line.

As soon as there is a unity code at each position of the reversible counter 50, the latter starts counting in reverse. At this instant the formation of the leading edge of the pulse signal is ended; the voltage at the output of the number-to-voltage converter 40 is equal to the initial voltage.

The countdown frequency of the reversible counter 50 is equal to the forward count frequency; hence, the duration of the trailing edge of the signal being formed is equal to the duration of its leading edge. Thus the reversible counter 50 forms a code sequence which linearly rises to reach a maximum value and then linearly drops so that the pulse signal is shaped as an isosceles triangle.

The polarity modulator 42 passes the pulse signal from the output of the number-to-code converter 40 to the input of the digital controlled random actions simulator 10; as this takes place, the polarity is not changed, or is changed, depending upon the code entered in the first register 45. For example, if the register 45 contains a code determining the amplitude value of the pulse signal, and if the value of said code corresponds to the negative subregion of the region for determining the distribution function of random signal amplitudes, the polarity modulator 42 changes the signal polarity.

The output pulse signals arriving at the input of the polarity modulator 42 from the second number-to-voltage converter 40 are shaped as stepped isosceles triangles because of the discrete increments in the amplitude; for that reason, the polarity modulator 42 also smoothes the leading edges of the pulse signals.

The random number, entered in the register 55, sets a required scaling factor of the frequency divider 54.

This means that with each duration value T (Figure 10) of the formed pulse signal, the reversible counter 50 (Figure 2) is filled at a respective frequency resulting from the division of the pulse flow arriving via the frequency divider 54 to the reversible counter 50 from the second pulse generator 53. The purpose of thus controlling the rate of filling of the reversible counter 50 is to enable said reversible counter 50 (Figure 2) to complete a double cycle, i.e. to count from zero to maximum value and in reverse, with any value of the duration T (Figure 10) of the formed pulse signal. This accounts for a strictly symmetrical isosceles triangle shape of the pulse signal regardless of a combination of its amplitude A (Figure 10) and duration T.

With the aid of the first pulse generator 27 (Figure 2) and the pulse counter 26, the random code stored in the pulse counter 26 is converted to a time interval between pulses being formed. As the formation of the time interval between pulses is completed, the control unit 25 takes care of a new operating cycle of the digital controlled random actions simulator 10.

Thus the digital controlled random actions simulator 10 forms isosceles triangle-shaped pulse signals; the amplitude and duration of these pulses, as well as the intervals between them, are random and distributed according to a specified pattern.

Consider operation of the digital controlled random actions simulator 10 in the case of forming pulse signals of an arbitrary shape.

The process of producing triangular pulses is identical with what is described above. To ensure this operating mode, the flip-flop 63 is set in advance, and the enabling signal is applied from its first output to the conjunctor unit 64. The flip-flop 81 is reset in advance, and the enabling signal is applied from its second output to the conjunctor 83. At this stage, the cyclic shift register 75 contains zero code, whereas the cycle length control unit 76 contains the code 00 ... 01, which means it operates in the mode of producing a single pulse signal.

The interaction between the cycle length control unit 76 and the cyclic shift register 75 makes it possible to form a predetermined number of pulses in a group of successively recurring pulses at the output of the digital controlled random actions simulator 10.

Upon completing the formation of a single pulse signal the reversible counter 50 discontinues counting pulses by a signal from the control unit 76.

A group of successively following pulses with a predetermined sequence of polarity changes is formed as follows. First, in the cycle length control unit 76 there is entered a code which sets the number of pulse signals in the group; in the first positions of the cyclic shift register 75, whose number is determined by that of pulse signals in the group, there is entered a sequence of binary digits which determine the order of changing the polarity of pulse signals in the group. By a signal from the second output of the cycle length control unit 76, the cyclic shift register 75 switches the internal feedback circuit from its output to the input of a position whose number is indicated by the code of the number of pulse signals in the group of pulses.

From the output of the cyclic shift register 75, the signal is applied via the conjunctor 83 and disjunctor 84 to the input 88 of the polarity modulator 42 and determines the sign of the pulse signal at the output of the digital controlled random actions simulator 10. The end of a complete operating cycle of the reversible counter 50, which includes forward count from zero to a maximum code value and counting in reverse, corresponds to the end of each pulse. At the end of each pulse, a signal arriving from the output of the cycle length control unit 76 shifts by one digit the code stored in the cyclic shift register 75. Upon completing the formation of the group of pulses, the cyclic shift register assumes its initial state by switching back the feedback circuit. The cycle length control unit 76 produces an end of operation signal for the reversible counter 50.

As the flip-flop 63 is reset, the enabling signal is applied from its output to the second conjunctor unit 65. A sequence of ordinates codes of the time function, which determines the shape of the output pulse signal of the digital controlled random actions simulator 10, is entered in advance in the memory 62. These codes arrive from the output of the memory unit 62 via the conjunctor unit 65 and disjunctor unit 66 to the input of the number-to-voltage converter 40.Sequential selection of codes from the memory 62 is carried out by signals from the output of the reversible counter 50. Under such operating conditions, at the output of the digital controlled random actions simulator 10 there are formed pulse signals of a desired shape, the polarity and the number of said signals in the group being determined by signals arriving from the outputs of the register 45 and the cyclic register 75.

As th,e flip-flop 81 is set in advance, the enabling signal is applied from its output to the first conjunctor 82; as codes are selected from the memory 62, signals are applied from its output via the conjunctor 82 and disjunctor 84 to the inputs of the polarity modulator 42.

Consider operation of the digital controlled random actions simulator 10 in the case of forming pulse signals modulated by harmonic signals.

The interaction between the second flip-flop 81, the first and second conjunctors 82 and 83, respectively, and the disjunctor 84 ensures separate transmission of codes from the outputs of the memory 62 and the cyclic shift register 75 to the polarity modulator 42.

Thus the digital controlled random actions simulator 10 makes it possible to produce pulse signals of arbitrary shapes, which, in turn, makes it possible for the digital simuiator-compu er system to reproduce a broader range of spectral and statistical characteristics of random actions.

For the sake of simplicity, the time function determining the shape of the output signal of the digital controlled random actions simulator 10 is represented as follows: Q(t) = U1(t)U2(t)U3(t)U4(t)U5(t) (1), where U1(t), U2(t), U3(t), U4(t) are transfer functions of the number-to-voltage converters38, 101 (Figure 3) and 104, respectively, and U5(t) is the transfer function of the polarity modulator 42.

The mode, whereby the transfer functions of the number-to-voltage converters 101 and 104 are equal to unity, ensures the formation of a flow of pulses of opposite polarities with random and independent - parameters distributed in accordance with a specified pattern.

The formation of pulses of a predetermined shape is described above.

This mode is set by applying a control signal from the control unit 25 to the input 94 of the reversible counter 92. As a result, the reversible counter 92 and register 98, and, consequently, the digital functional converter 96 and number-to-voltage converters 101 and 104 are found in a steady state, whereby the output potential of the reference voltage source 37 is applied to the input of the first number-to-voltage converter 38 without any scale conversion.

The formation of a random pulse flow with a predetermined spectral power density is based upon the known principle, whereby the spectrum of the standard pulse signal is transferred to the high-frequency range by multiplying this signal by a harmonic oscillation.

Let it be assumed that in (1) the respective transfer functions of the number-to-voltage converters 101 and 104 are as follows: U3(t) = Bk (2) U4(t) = cos e0k(t) (3), where Bk is the amplitude of the k-th harmonic of the harmonic signal; k=1,2 r; and o,k is the frequency at which the standard pulse signal is filled with harmonic oscillations.

U4(t) according to (3) is formed to a desired accuracy with the aid of the digital functional converter 96 which ensures the conversion of the linearly changing input code sequence, formed at the output of the reversible counter 92, to a non-linear code sequence which determines the shape of the signal modulating the envelope of the pulse signal at the output of the digital controlled random actions simulator 10.

With wk = 1, the positive half period of the harmonic oscillation /see (3)/ is quantized for ii clock cycles, and the values of U4(ti) with i = 0, 1' .. . (#- 1) are represented at the output of the digital functional converter 96 as an n-digit code. By appropriately selecting the values of v and n, one can attain any desired accuracy of conversion. t determines the digit capacity S of the second reversible counter 92; S # log2# (4) The negative half period of the harmonic oscillation /see (3)/ is formed by changing the polarity of the output signal of the digital controlled random actions simulator 10 by a signal from the output of the reversible counter 92, applied to the input 95 of the polarity modulator 42.

From the pulse generator 107, pulses are applied via the frequency divider 108 to the input of the reversible counter 92. The codes arriving from the output of the reversible count( r 92 are converted by the digital functional converter 96 to codes which control the output voltage of the fo ~mirth number-to-voltage converter 104, whereby the U4(t) signal is produced. A change in the frequency is effected by setting a desired scaling factor of the second frequency divider 108, which in accordance with the code formed by the random numbers transducer 24.

The multitude of the amplitudes Bk and frequencies wk is calculated from the predetermined spectral power density of the simulating random pulse process and the known spectral power density of the pulse modulated by the harmonic oscillation. Codes of the amplitudes Bk and frequencies wk are formed by the random numbers transducer 24 with probabilities set according to the desired distribution pattern, and entered in advance in the memory 23.

The codes of the amplitudes Bk and frequencies tok are transmitted from the output of the random numbers transducer 24 to the registers 98 and 111, respectively, which is done by signals arriving from the control unit 25.

Thus in the above operational mode, the output signal of the digital controlled random actions simulator 10 is expressed by the following time function: a1(t) = U(t)U2(t)U5(t)Bkcos~k (S).

The spectral power density of the output process is a superposition of spectral power densities of a pulse of a preselected shape.

The reproduced spectral power density function of the random process approximates the predetermined arbitrary spectral power density function to any desired degree of accuracy. In order to ensure a uniform distribution of the random initial phase of the signal coS#k, the random numbers transducer 24 forms equiprobable random codes which are entered, prior to forming another pulse, in the second reversible counter 92. This is done by a signal applied from the control unit 25 to the input of the reversible counter 92.

Thus the digital controlled random actions simulator 10 forms a random pulse process with a required spectral power density function by modulating pulses with harmonic signals.

The digital controlled random actions simulator 10 (Figure 4) is intended to produce a random process of a pulsed nature, which is a train of pulse signals of a random or predetermined shape, recurring through random or predetermined time intervals.

The digital controlled random actions simulator 10 operates in two modes. The first mode presupposes an adjustment to predetermined statistical characteristics of random actions, whereby in the memories 145 and 156, the pulse distributor 122 and the registers 116 and 137 there are entered binary codes which determine the statistical characteristics of random actions. The second mode consists in producing random actions.

The first mode is auxiliary and invariably precedes the second mode during which at the output of said digital controlled random actions simulator 10 there is a random pulse process.

The data recording process is carried out as follows. To one of the inputs of the commutator 158, there is applied a sequence of binary codes; there are also applied signals which synchronize the instances of the appearance of said binary codes. From the first output of said commutator 158, the binary codes are applied to the inputs 161 and 162 of the memories 145 and 156 and the inputs ....... 1648 of the registers 1 .. ..

1 16s; the pulses which synchronize the instances of appearance of the binary codes are applied from the second output of said commutator 158 to the input 159 of the pulse counter 157. The binary code, entered in the counter 157, determines the record address of the binary code. The record address of the binary code is applied to the address inputs 165 and 166 ofthe memories 145 and 156. in order to enterthe binary codes in the registers 11 6i . . .,1168, the record address code is decoded by the decoder 155, at whose outputs there are produced write signals. The data recording process is carried out in a certain order. First, information is entered in the memories 145 and 156, then in the pulse distributor 122 and, finally, in the registers 116 and 137.To the input 163 of the distributor 122 (Figure 7) two binary codes are successively applied; the first code is entered in the flip-flop 217 by a signal at the input 169, whereas the second code is entered in the register 215 by a signal at the input 170. In the registers 11 6i 11 6s (Figure 4), information is entered from the inputs 1641, ...,1648 164sby signals at the inputs 174i ...,1748. 17#.In the register 137, information is entered from the input 160 by a signal at the input 171; this ends the data loading process.

The generation of a random pulse process includes the performance of four operating cycles by different units of the simulator 10, namely, a cycle of producing a random time interval, a pulse forming cycle, a cycle of generating an actual pulse signal value, and a multiplication cycle. The cycle of forming a random time interval and the pulse forming cycle alternate with time. The cycles of forrr ing an actual pulse signal value are performed only within the pulse forming cycle. The multiplication cycles are performed within the cycle offorming an actual pulse signal value.

Consider the process of generating a random pulse process beginning with an instant of time when the formation of a pulse signal is over. This instant is the beginning of forming a random time interval and is marked by the appearance of an "end of pulse" signal at the output of the pulse cistributor 122. At this stage, the flip-fiop 222 (Figure 7) of the pulse distributor 122 and the flip-flop 190 (Figure 6) of the potential distributor 118 are in the off state. From the output of the distributor 122 (Figure 4), the "end of pulse" signal is applied to the respective input of the register 175. As a result, the latter is reset, which state determines the presence of zero voltage across the output of the number-to-voltage converter 176.The "end of pulse" signal is also applied to the input 151 of the pulse counter 147, whereby the latter is reset, and to the input 150 of the random numbers transducer 146, which sets the instant of producing a random number. The random number is produced according to the distribution pattern determined by the binary codes stored in the memory 145. To the input 148 of the memory 145, there are applied binary codes which set addresses of information being stored. To the input 149 of the random number transducer 146 there is applied the stored information. Upon the end of producing a random number, to the input 152 ofthe pulse counter 147 there is applied a respective binary code, which code is stored by said counter 147.The pulse counter 147 operates in the countdown mode, so signals of the second clock sequence, applied from the output of the frequency divider 136 to the input 153 of the pulse counter 147, successively and over predetermined time intervals reduce the contents of said pulse counter 147 by unity until the counter 147 is zeroized. At this instant, the cycle of forming a random time interval is ended, and at the output of the pulse counter 147 there appears an "onset of pulse" signal which sets the beginning of a pulse formation cycle. The frequency division factor of the divider 136 is determined by the contents of the high-order group of digits of the register 137, so a variation in this state leads to a change in the scale of the conversion of the random number to a time interval.Besides, the scale of the conversion is also determined by the repetition frequency of pulses of the reference pulse train applied to the input 139 of the divider 136 from the output of the pulse generator 134.

In the general case, the time interval T between the appearance of the "end of pulse" signal and the instant the "onset of pulse" signal is formed is derived from the following equation: T=M(N+ 1) At (6), where M is the value of the random number; N is the code stored by the high-order group of digits of the register 137; and At is the interval between pulses of the reference train of pulses.

Consider a cycle of generating a pulse whose onset is the "onset of pulse" signal applied from the output of the pulse counter 147 to the input 154 of the pulse distributor 122. The appearance of the "onset of pulse" signal is preceded by the next state of the pulse distributor 122 and the potential distributor 118. The fiip-flop 222 (Figure 7) of the pulse distributor 122 is in its off state; at the input 226 of the conjunctor 223 there is an enabling signal; at the input 234 of the conjunctor 210 there is an inhibiting signal which is applied to the input 235 of the counter 212 to reset the latter. There are no signals at the respective outputs of the decoder 211, sine there is no passage of signals via the conjunctor 210 to the gating input 213 of the decoder 1. A signal from the respective output of the pulse distributor 122 is applied to the input 124' of the potential distributor 118 (Figure 6) and inhibits the passage of signals from The input 144 via the conjunctor 192. The flip-flop 190 of the potential distributor 118 is in the off state, which means that at the input 206 of the conjunctor 192 there is an enabling signal; at the input 207 of the shift register 189 there is a reset signal, which corresponds to the presence of a signal at only one of its outputs, corresponding to the lowesterder digit of said register; at the input 205 of the pulse counter 202 there is a reset signal; at the input 203 of the conjunctor 193 there is an inhibiting signal which is also applied to the input 133 (Figure 4) of the synchronization unit 126 and, through a respective input, inhibits the passage of signals via the conjunctor 280 (Figure 9).

The appearance of the "onset of pulse" signal at the input 154 (Figure 4) of the pulse distributor 122 results in an appearance of an "initial conditions setting" signal at the respective output of the pulse distributor 122, which signal is applied to the inputs 1241, ..., 124a, whereby the binary codes are transferred from the initial conditions registers 116" ...,1168 via the inputs 117r, ...,1178 to the respectivle harmonic oscillators 11 Si 1158; this means that the "initial conditions setting" signal is applied to a respective code write input of the reversible counter 183 (Figure 5).Besides, the flip-fiop 222 (Figure 7) is switched on, whereby the passage of signals via the conjunctor 223 is inhibited, whereas signals are enabled to pass through the input 234 via the conjunctor 210, and the reset signal is removed from the pulse counter 212; the appearance of a signal at the respective output of the pulse distributor 122 enables the potential distributor 118 (Figure 6) to operate in the cyclic mode, i.e. atthis instant there begins the process of cyclic generation of pulse signal current values; the end of a cycle is marked by the appearance of an "end of cycle" signal at the respective output of the potential distributor 118, which signal is applied to the input 181 (Figure 7) of the pulse distributor 122 and increases the contents of the counter 212 by unity.The pulse generating cycle is ended when the state of the counter 212 coincides with that of the register 215, whereby at the output of the comparison circuit 216 there is produced a signal to enable the passage of the "end of cycle" signal via the conjunctor 224 and disjunctor 255; the flip-flop 222 is brought to the off state, and there appears an end of pulse" signal at the respective output of the pulse distributor 122.

In the course of the pulse generating cycle, the pulse counter 212 counts the number of completed cycles of generating current pulse signal values, whose maximum. number is set by the binary code stored by the register 215. Thus by changing the value of the code stored by the register 215, one can set the desired duration of the pulse ir, which is derived from the following equation: X = kAt2 (7), where kisthe binary code stored by the register 215; and At2 is the duration of the cycle of generating current pulse signal values.

The appearance of signals at the respective outputs of the pulse distributor 122 is determined by the state of the flip-flop 217; if the flip-flop 217 is in the "on" state, the signal applied from its output to the input 218 of the conjunctor 210 enables the passage of the "end of cycle" signal from the input 234 to the output of said conjunctor 210 and on from the input 213 of the decoder 211 to a respective output. The number of this output, at which the "end of cycle" signal is produced, is set by the variable code of the counter 212 whose output is connected to the input 214 of the decoder 211.

Accordingly, when the flip-flop 217 is in the "on" state, the "end of cycle" signal successively appears at the respective outputs of the pulse distributor 122, which are connected to the inputs 123 (Figure4) of the respective initial conditions registers 1 16i 1 . .,1168, and controls the writing into said registers, through the inputs 174, of random numbers arriving from the output of the random numbers transducer 146. When the flip-flop 217 is in the "off" state, no signals are applied to the respective outputs of the pulse distributor 122, whereas the initial conditions registers 116r, ...,1168 (Figure 4) continue to store the original codes.

The pulse generating cycle is followed by the random time interval generating cycle, and this sequence of cycles is repeated throughout the entire course of the random pulse process. The cycles of generating actual current pulse values can only take place within the pulse generation cycle, when the flip-flop 222 (Figure 7) is in the on state, so that there is an enabling signal at the input 1241 (Figure 6) of the potential distributor 118, and, accordingly, at the input of the conjunctor 192. The beginning of the cycle of generating the actual pulse signal value is set by the "onset of cycle" signal applied from the output of the frequency divider 135 (Figure 4) to the input 144 (Figure 6) of the distributor 118.

The flip-flop 190 is in the "off" state; the "onset of cycle" signal passes via the conjunctor 192 and disjunctor 194 and switches the flip-flop 190 on; as this takes place, from the input 207 of the shift register 189 and the input 205 of the pulse counter 202 there is removed a set signal; at the same time from the input 206 of the conjunctor 192 there is removed a signal which enables the passage of signals to the output of said conjunctor 192. Besides, as the flip-flop 190 is brought to the on state, at the respective output of the potential distributor 118 there is produced a signal to perform multiplication cycles and enable the passage of signals through the conjunctor 193.The synchronization unit 126 (Figure 4) starts to perform multiplication cycles, the end of each cycle being accompanied by an "end of multiplication" signal applied from the respective output of the synchronization unit 126 to the input 132 (Figure 6) of the potential distributor 118. The flip-flop 193 is on, so from the respective input of the conjunctor 193, the "end of multiplication" signals are passed to its output and applied to the input 203 of the counter 202, the shift input 195 of the shift register 189, and the respective output of the potential distributor 118. Thus each multiplication cycle increases the contents of the counter 202 by unity and shifts the informaton stored by the register 189. The shifting of information storage locations in the register 189 is effected so that with a shift of unity from a lower to a higher order digit, unity is also written in the lower order digit.

The cycle of producing the actual pulse signal value is ended upon the appearance of a signal at the higher order location of the shift register-189 (Figure 6), as well as the appearance at the respective output of the synchronization unit 126 (Figure 4) of an "end of multiplication" signal which is applied to the input 132 of the potential distributor 118 and is further applied via the conjunctors 193 and 191 and the disjunctor 194 to the flip-flop 190, whereby the latter is brought to the off state. As this takes place, at the respective output of the potential distributor 118 (Figure 4) there appears an "end of cycle" signal which is applied to the input 180 of the register 176, whereby from the result accumulator 125 to said register 176 there is transferred a binary code corresponding to the actual value of the random process.In the course of generating the actual pulse signal value, to the input 120 (Figure 5) of the harmonic oscillators 115 there are successively applied potentials arriving from the respective outputs of the potential distributor 118, which potentials enable the passage of signals from the output of the code converter 184 (Figure 5) to the outputs of the harmonic oscillators 115. The code at the outputs of the decoder 208 (Figure 6) is changed upon the arrival of the "end of multiplication" signal, so during each new multiplication cycle the next harmonic oscillator is connected to the input 131 of the result accumulator 125 (Figure 4).Thus during the cycle of generating the actual pulse signal value, to the input 131 of the result accumulator 125 there are successively connected all the harmonic oscillators 11571 ~~~ .1158. Besides, in the course of the cycle of generating the actual pulse signal value, the "end of multiplication" signal, applied from the synchronization unit 126 to the input 132 of the potential distributor 118, passes via the conjunctor 193 (Figure 6), is applied to the respective output of the potential distributor 118 and on to the combined inputs 121 (Figure 4) of the harmonic oscillators 1 11 ..., S# 1158, which are connected to one of the inputs of the conjunctor 182 (Figure 5).The other inputs of said conjunctor 182 are the inputs 119 of the harmonic oscillators, connected to the respective outputs of the potential distributor 118 (Figure 4), so the passage of signals via the conjunctor 182 (Figure 51 to the input 186 of the reversible counter 183, and the number of these signals occurring during the cycle of generating the actual pulse signal value are dependent upon digit location number of the register 189 (Figure 6), whereto the respective harmonic oscillator is connected.During the cycle of generating the actual pulse signal value, through the conjunctor 182 (Figure 5) to the input 186 of the reversible counter 183 there successively pass 1,2,3 8 signals; to the iesser number corresponds the harmonic oscillator connected to the higher-order digit location of the shift register 189 (Figure 6).

By each signal arriving at its input 186, the code state of the reversible counter 183 (Figure 5) is changed by a unity; following the arrival of a plurality of input signals, there is brought about a linear change with time in the state of said reversible counter 183. From the output of the reversible counter 183, the linearly changing sequence of binary codes is applied to the input 187 of the code converter 184, at whose output there is a respective sequence of binary codes which changes linearly with time. Thus during the pulse generation cycle, at the outputs of the harmonic oscillators 1151, there are harmonically changing code sequencies with multiple frequencies.

Consider now the way the multiplication cycle is performed by the synchronization unit 126 (Figure 4) and the result accumulator 125. The multiplication cycle is found within the cycle of generating the actual pulse signal value in the presence of an enabling signal at the input 133 of the synchronization unit 126. The multiplication cycle is preceded by the appearance of a signal applied from the output of the frequency divider 135 to the input 143 of the result accumulator 125, whereby the register 238 (Figure 8) is reset.

At this stage, the flip-flop 249 (Figure 9) of the synchronization unit 126 is in the on state, so that there is an enabling signal at the input 256 of the disjunctor 253, the input 278 of the conjunctor 274;the input 277 of the flip-flop 275, and the'input 288 of the conjunctor 281 Upon the appearance of an enabling signal at the input 133 of the synchronization unit 126, signals of the pulse generator 134 (Figure 4) pass via the conjunctor 280 (Figure 9) and the conjunctor 281, due to the presence of an enabling signal at the latter's input 285; these signals are applied to the input 128 (Figure 8) of the result accumulator 125, whereby information is entered in the register 236 and the flip-flop 242; the information is also applied to the input 131 of the result accumulator 125; also, information is entered in the register 248 and the flip-flop 243 and is applied to the input 173 of the result accumulator 125. Said information write signal is applied to the combined inputs of the respective registers and flip4lops. Upon the end of said signal at the output of the conjunctor 280 (Figure 9); the state of the flip-flop 275 is changed, and the next signal is passed from the input 140 of the synchronization unit 126 via the conjunctor 280, the conjunctor 274, and the disjunctor 253, whereby the state of the flip-flop 249 is changed; an inhibiting signal is produced at the input 287 of the conjunctor 280.The change of the state of the flip-flop 249 produces an enabling signal at the input 276 of the conjunctor 273, whereas with the flip-flop 249 being in its previous state, the state of the flip-flop 250 corresponds to the presence of an enabling signal at the input 257 of the conjunctor 251 ; through the input 272, in the register 262 there is entered zero binary code with the exception of the lowest-orderdigit. The next signal, arriving at the input 140 of the synchronization unit 126, is passed via the conjunctor 273, and the conjunctor 251, provided there is an enabling signal at its input 271, and is applied to the input 130 (Figure 8) of the result accumulator 125, which input 130 is connected to the respective write input of the register 238. Upon the end of this signal, in the register 238 there is entered a binary code arrriving from the output of the arithmetic logical unit 237 at the input 240 of the register 238, whereby the state of the flip-flop 250 (Figure 9) is changed.

The binary code at the output of the arithmetic logical unit 237 (Figure 8) is formed according to the states of the flip-flops 242 and 243, which correspond to the sign digits of the binary codes stored in the registers 236 and 238, respectively. The outputs of said flip-flops are connected to the input of the modulo two adding circuit 244; if the states of the flip-flops 242 and 243 coincide, there is a signal at the output of said circuit 244; there is no signal if the states of said flip-flops 242 and 243 differ. Thus in the presence of a signal at the input 247 of the arithmetic logical unit 237, at the latter's output there is formed a code equal to the sum total of the codes arriving at the inputs 239 and 241 of said unit 237.In the absence of a signal at the output 247 of the arithmetic logical unit 237, at its output there is formed a code equal to the difference between the binary codes arriving at its inputs 239 and 241. Upon the arrival of the next signal at the input 140 of the synchronization unit 126 (Figure 9), said signal is passed via the conjunctors 273 and 252 and applied to the input 266 of the shift register 262, whereby the binary code stored in said register 262 is shifted one digit towards the higher-order digits. Upon the end of this signal, the flip-flop 250 reassumes its previous state.

The states of the flip-fiop 250 are changed, and information is shifted in the register 262 as described above until the appearance of an enabling signal at the highest-order digit location of the register 262. This signal is applied to the input 270 of the disjunctor 253, so upon the arrival of the next signal from the output of the conjunctor 252, it is applied to the input 254 of the flip-flop 249, whereby the latter's state is reversed.

This ends the multiplication, as indicated by the appearance of a signal at the output of the conjunctor 263 and the respective output of the synchronization unit 126.

According to the foregoing sequence of operational cycles of the simulator 10 (Figure 4), at its output there is formed a random process which is a train of pulse signals, each having a random or predetermined shape and recurring over both random and predetermined time intervals; the statistical characteristics of the random pulse process are determined by the arrays of binary codes stored in the memories and registers of the simulator.

The structure and composition of the proposed system and the proposed testing method guarantee effective testing of different objects for random actions. The system of the present invention is a closed system providing for automatic control of its units by instructions issued by a digital computer. These factors and the presence of a special unit, i.e. the digital controlled random actions simulator, provide for a maximum compatibility of the testing conditions with the actual operating conditions and make it possible to produce extreme testing conditions with a view to studying the behaviour of objects being tested.

Claims

1. A method of testing objects for random actions, which method comprises: recording random actions to which an object is subjected in the course of operation; determining the spectral composition and statistical characteristics of the recorded random actions, whereto the object is subjected; reproducing the random actions as a simulating random pulse process, wherein the amplitudes, durations and polarities of pulses, as well as intervals between pulses are random parameters with predetermined probability characteristics adequate to the recorded random actions with regard to the spectral and statistical characteristics; applying the reproduced random actions to the object being tested; selecting a combination of pulse shapes; forming the simulating random pulse process as a train of pulses of different shapes from the selected combination of pulse shapes;; forming statistically independent random parameters of pulses; analyzing the spectral and statistical characteristics of the reproduced random actions and the response of the object being tested to these actions; correcting the spectral and statistical characteristics of the simulating random pulse process by varying its probability characteristics.

2. A method as claimed in claim 1, whereby pulses of the simulating random pulse process are modulated by a harmonic signal possessing a random and statistically independent amplitude, phase and frequency.

3. A method as claimed in claims 1 or 2, whereby pulses of the simulating random pulse process are modulated by a converted combination of harmonic signals possessing random and statistically independent amplitudes, phases and frequencies.

4. A digital simulator-computer system for effecting the method set forth in claims 1,2 and 3, comprising: a control computer intended to form deterministic test signals and control units of the system; an interface unit of the control computer, intended to conjugate the control computer with the units of the system, an input and an output of the interface unit being connected to the control computer; a main forward channel comprising at least one digital-to-analog converter and connected to another output of the interface unit; a main feedback channel comprising at least one analog-to-digital converter and connected to another input of the interface unit; a test bed intended to transmit test actions to the object and electrically coupled to the forward and feedback channels;; an auxiliary forward channel comprising at least one digital controlled random actions simulator intended to reproduce random actions, to which the object is subjected, as a simulating random pulse process and connected to the interface unit; an auxiliary feedback channel comprising at least one digital multifunctional statistical analyzer intended to statistically analyze the reproduced random actions right in the course of testing objects and connected to an input of the interface unit, the test bed being electrically coupled to the main and auxiliary forward channels and the main and auxiliary feedback channels via respective distribution devices.

5. A system as claimed in claim 4, wherein the output of the digital multifunctional statistical analyzer is connected to the input of the digital controlled random actions simulator.

6. A system as claimed in claims 4 and 5, wherein the digital controlled random actions simulator comprises in series: a memory intended for storing codes determining the type and numerical characteristics of distribution functions of random parameters of pulses of the simulating random pulse process, its respective inputs being connected to the output of the interface unit and the output of the auxiliary feed-back channel;; a random numbers transducer intended for forming codes of random numbers corresponding to the specific values of amplitudes, durations and polarities of pulses,'as well as intervals between adjacent pulses, whose input and output are connected to the respective output and input of the memory, a control unit intended to synchronize operation of all the units of the digital controlled random actions simulator and ensure an exchange of information between the units of the digital controlled random actions simulator, an input and an output of the control unit being connected to a respective output and a respective input of the memory;; a pulse counter intended for storing a random code determining the duration of a time interval between pulse signals of the simulating random pulse process, and converting this code to a time interval, its input being connected to a respective output of the random numbers transducer; a generator of variable recurrence frequency pulses, intended to generate a flow of clock pulses to fill the pulse counter and set the frequency of the output pulse signal flow of the digital controlled random actions simulator;; a reference voltage course intended to set an ampitude distribution range of pulse signals formed by the digital controlled random actions simulator, which reference voltage source is electrically coupled to a number-to-voltage converter intended to convert the code, determining the amplitude of pulse signals, to voltage corresponding to that amplitude and distributed within the amplitude distribution range; a second number-to-voltage converter intended for voltage conversion of codes whose sequence determines the shape of pulse signals formed by the digital controlled random actions simulator;; a polarity modulator intended to ensure a prescribed probability of producing positive and negative pulses, its additional input being connected to a respective output of the reference voltage source, whereas its output is connected to the input of the first distribution device, both number-to-voltage converters and the polarity modulator being placed in series; a register intended for storing a code which determines the amplitude and polarity of the next pulse of the simulating random pulse process, its output being connected to the input of the first number-to-voltage converter and another input of the polarity modulator, whereas its inputs are connected to the output of the random numbers transducer and the output of the control unit;; a reversible counter intended to form a linearly rising and dropping code sequence, whereby an isosceles triangle-shaped pulse is produced, its output being electrically coupled to the input of the second number-to-voltage converter and connected to a respective input of the control unit, whereas its input is connected to a'respective output of the control unit; a second pulse generator intended to generate a flow of clock pulses whose frequency is equal to a maximum frequency at which the reversible counter is filled; a frequency divider intended to set the rate of filling the reversible counter with clock pulses and interposed between the second pulse generator and the input of the reversible counter;; a second register intended for storing a code corresponding to the'duration of the base of the isosceles triangle-shaped pulse and determining the repetition frequency of clock pulses filling the reversible counter, an output of the second register being connected to the input of the frequency divider, whereas its inputs are connected to the output of the random numbers transducer and the output of the control unit.

7. A system as claimed in claims 4. 5 and 6, wherein the digital controlled random actions simulator comprises: a cyclic shift register intended for storing a code which determines the sequence of changing the polarity sign of the group of pulses at the output of the digital controlled random actions simulator; a cycle length control unit intended to set the number of pulses in a group of successive pulses at the output of the digital controlled random actions simulator, an input and an output of the cycle length control unit being connected to a respective output and a respective input of the reversible counter, whereas outputs of the cycle length control unit are connected to respective inputs of the cyclic shift register; ; a flip-flop, two conjunctors and a disjunctor, intended to ensure separate transmission of codes from the output of the shift register to the polarity modulator, the output of the disjunctor being connected to the input of the polarity modulator, the output of each of the two conjunctors being connected to the input of the disjunctor, the first input of each of the two conjunctors being connected to the output of the flip-flop, the second input of one of the two conjunctors being connected to the output of the cyclic shift register, the reversible counter being electrically coupled to the second number-to-voltage converter via a second memory intended for storing ordinates codes of pulses of predetermined shapes, the input of the second memory being connected to the output of the reversible counter;; a second flip-flop, two conjunctor units and a disjunctor unit, intended to ensure separate transmission of codes from the outputs of the reversible counter and the second memory to the input of the second number-to-voltage converter, the output of the disjunctor unit being connected to the input of the second number-to-voltage converter, the output of each of the two conjunctor units being connected to the input of the disjunctor unit, the first input of each of the two conjunctor units being connected to the output of the second flip-flop, the second input of one of the two conjunctor units being connected to the output of the reversible counter, the second input of the other conjunctor unit being connected to the output of the second memory, the output of the second memory also being connected to the input of the first conjunctor to ensure separate transmission of codes from this second memory to the polarity modulator.

8. A system as claimed in claims 4 through 7, wherein the digital controlled random actions simulator comprises: a second reversible counter intended to form a linearly changing code sequence, its inputs being connected to the output of the random numbers transducer and the output of the control unit, whereas its output is connected to a respective input of the polarity modulator; a digital functional converter intended to convert the linearly changing input code sequence to a non-linear code sequence which determines the shape of a signal modulating the evenlope of the pulse signal formed by the digital controlled random actions simulator, the input of the digital functional converter being connected to a respective output of the second reversible counter;; a third register intended for setting the amplitude of the modulating signal, its inputs being connected to the output of the random numbers transducer and a respective output of the control unit; third and fourth number-to-voltage converters, each being connected with its input to the output of the third register and the output of the digital functional converter, respectively, both number-to-voltage converters being placed in series and interposed between the output of the reference voltage source and the input of the first number-to-voltage converter; a third pulse generator intended to form clock pulses recurring at a frequency equal to a maximum frequency at which the second reversible counter is filled;; a second frequency divider intended to set a frequency at which the second reversible counter is filled with clock pulses, and interposed between the respective pulse generator and the input of the second reversible counter; a fourth register intended for storing a code determining the frequency at which the second reversible counter is filled with clock pulses, the inputs of the fourth register being connected to a respective output of the random numbers transducer and the output of the control unit, whereas the output of the fourth register is connected to the input of the second frequency divider.

9. A system as claimed in claims 4 and 5, wherein the digital controlled random actions simulator comprises: harmonic oscillators intended to set a desired Fourier spectrum of pulses of the simulating random pulse process, outputs of the harmonic oscillators being combined; initial conditions registers intended for storing predetermined initial phases of harmonic oscillations, their outputs being connected to the inputs of the respective harmonic oscillators; a first distributor intended for setting the frequencies of harmonic oscillations at the outputs of the harmonic oscillators, groups of outputs of the first distributor being connected to the inputs of the respective harmonic oscillators, whereas its separate output is connected to the inputs of the harmonic oscillators;; a second distributor intended to enter in the initial conditions registers codes which determine the initial phases of harmonic oscillations, its group of outputs being connected to the inputs of the respective initial conditions registers, whereas its outputs are connected to the inputs of the harmonic oscillators and the input of the first distributor; a result accumulator intended for non-linear conversion of harmonic oscillations; a synchronization unit, its group of inputs being connected to a respective group of outputs of the result accumulator, its input being connected to the output of the first distributor, whereas its outputs are connected to the input of the first distributor and respective inputs of the result accumulator whose input is connected to the outputs of the harmonic oscillators;; a pulse generator intended to form a first train of clock pulses from a train of reference pulses, the frequency of the first train of clock pulses determining the duration of a pulse at the output of the digital controlled random actions simulator; a first frequency divider intended to form a first train of clock pulses from a train of reference pulses; a second frequency divider intended to form a second train of clock pulses from a train of reference pulses, which second train of clock pulses determines the area of random values of time intervals between the onsets of adjacent pulses at the output of the digital controlled random actions simulator;; a frequency division factor codes register whose output is connected to inputs of the two frequency dividers, an output of one of the frequency dividers being connected to a respective input of the result accumulator and the input of the first distributor, the output of the pulse generator being connected to the inputs of the two frequency dividers and the input of the synchronization unit; a first memory intended for storing codes which determine the pattern of distribution of random values of the time interval between the onsets of adjacent pulses at the output of the digital controlled random actions simulator; a random numbers transducer intended to produce random codes with a predetermined distribution function;; a first pulse counter intended to convert the random code to a time interval, the output and input of the first memory unit being connected to a respective input and output of the random numbers transducer, a second input of the random numbers transducer and the input of the first pulse counter being combined and connected to the output of the second distributor, the outputs of the random numbers transducer also being connected to respective inputs of the initial conditions registers and the input of the first pulse counter whose input is connected to the output of the second frequency divider, the output of the first pulse counter also being connected to the input of the second distributor; a decoder intended to enter additional codes in the initial conditions registers;; a second memory intended for storing codes which determine the spectral power density of the random pulse process at the output of the digital controlled random actions simulator; a second pulse counter intended for setting cell addresses of the memories to enter information in these cells; a commutator intended to enter codes in the memories through two independent channels, its inputs being respectively connected to the output of the interface unit and the output of the auxiliary feedback channel, its outputs being connected to the input of the second pulse counter, the input of the frequency division factor codes register, the input of the first memory, the input of the second memory, the input of the second distributor and the inputs of the initial conditions registers, the output of the second pulse counter being connected to the input of the first memory, the input of the second memory and the input of the decoder whose group of inputs is connected to the inputs of the initial conditions registers, whereas its outputs are connected to respective inputs of the second distributor and the input of the frequency division factor codes register, the input of the second memory also being connected to a respective output of the first distributor, whereas the output of the second memory is connected to the input of the result accumulator; a number-to-voltage converter intended for analog representation of the simulating random pulse process, its output being connected to the input of the first distributor;; an actual process value code register whose output is connected to the input of the number-to-voltage converter, whereas its inputs are connected to the output of the result accumulator, the output of the first distributor and the input of the second distributor.

10. A system as claimed in claims 4, 5 and 9, wherein each harmonic oscillator of the digital controlled random actions simulator comprises: a conjunctor intended to control the harmonic oscillator through two inputs; a reversible counter intended to form a linearly changing code sequence; a code converter intended to convert the linearly changing code sequence to a sinusoidally changing sequence;; a multiplexer intended to interconnect the outputs of the harmonic oscillators, the inputs of the conjunctor being connected to the outputs of the first distributor, the output of the conjunctor being connected to the input of the reversible counter which is also connected to the initial conditions registers and the second distributor, the output of the reversible counter being connected to the input of the code converter whose output is connected to the input of the multiplexer which is connected to the output of the first distributor, the output of the multiplexer being connected to the input of the result accumulator.

11. A system as claimed in claims 4, 5, 9 and 10, wherein the first distributor of the digital controlled random actions simulator comprises: a shift register intended to produce a system of potentials to control the frequencies of the harmonic oscillators; a flip-flop, three conjunctors and a disjunctor, the input of the shift register being combined with the input of the first conjunctor, whereas the output of the shift register is connected to the inputs of the harmonic oscillators and the input of the first conjunctor, the outputs of the first and second conjunctors being respectively connected to the inputs of the disjunctor, one of whose inputs is connected to the output of the first distributor, whereas the output of the disjunctor is connected to the input of the flip-flop;; a pulse counter intended to form a code which sets the number of a harrronic oscillator, the input of the pulse counter being connected to the combined inputs of the shifts register and the first conjunctor, as well as to the output of the third conjunctor connected to the inputs of the harmonic oscillators, the input of the third conjunctor being connected to the output of the flip-flop and the output and input of the synchronization unit, the inputs of the second conjunctor being connected to the output of the result accumulator, the output of the second distributor, the input of the shift register, the output of the flip-flop and the input of the pulse counter; ; a decoder intended to produce signals to control the multiplexer, its input being connected to the output of the counter and the input of the second memory, whereas its outputs are connected to the inputs of the harmonic oscillators.

12. A system as claimed in claims 9, 10 and 11, wherein the second distributor of the digital controlled random actions simulator comprises: a pulse counter; a first conjunctor and a decoder intended to form signals for writing information in the initial conditions registers, its inputs being connected to the output of the first conjunctor and the output of the pulse counter, whereas its output is connected to the inputs of the initial conditions registers; a register intended for storing a code which determines the duration of a pulse of the random pulse process at the output of the digital controlled random actions simulator; a comparison circuit intended to set an instant of time corresponding to the end of th pulse of the random pulse process at the output of the digital controlled random actions simulator;; a first flip-flop whose output is connected to a respective input of the first conjunctor, an input of the flip-flop and an input of the register being combined and connected to the output of the commutator, a second input of the register being connected to the output of the decoder of the digital controlled random actions simulator, inputs of the comparison circuit being connected to the output of the register and the output of the pulse counter, a second input of the first flip-fiop being connected to the output of the decoder of the digital controlled random actions simulator;; a second flip-flop, two more conjunctors and a disjunctor, inputs of the second conjunctor being connected to the output of the pulse counter of the digital controlled random actions simulator and the output of the second flip-flop, whereas an output of the second conjunctor is connected to the input of the disjunctor and the inputs of the harmonic oscillators, inputs of the third conjunctor being connected to the output of the comparison circuit, the input of the first conjunctor, the input of the pulse counter and the output of the first distributor, whereas the output of the third conjunctor is connected to the input of the actual process value code register and the input of the disjunctor whose output is connected to the input of the second flip-flop whose output is also connected to a respective input of the first conjunctor, the input of the pulse counter and the input of the first distributor.

13. A system as claimed in claims 4,5 and 9 through 12, wherein the result accumulator of the digital controlled random actions simulator comprises: a first register intended for storing codes of actual amplitude values of harmonic oscillations; an arithmetic logical unit intended for non-linear conversion of codes of the harmonic oscillators;; a second register intended for storing intermediate results of non-linear conversion, inputs of the first register being connected to the outputs of the harmonic oscillators and the output of the synchronization unit, its output being connected to the input of the arithmetic logical unit whose output is connected to an input of the second register, two other inputs of the latter being connected to the output of the synchronization unit and the output of the first frequency divider, its output being connected to the input of the arithmetic logical unit and the input of the actual process value code register; a first flip-flop intended for storing a polarity sign code of harmonic oscillations; a second flip-flop intended for storing a sign code of a factor by which the harmonic oscillation amplitude is multiplied;; a modulo two adding circuit intended to form an attribute of an operation performed by the arithmetic logical unit, inputs of the first flip-flop being connected to the input of the first register, a respective input of the second flip-flop and the output of the synchronization unit, inputs of the modulo two adding circuit being connected to the outputs of the two flip-flops, whereas the output of the modulo two adding circuit is connected to the input of the arithmetic logical unit; one more register intended for storing a code of factors by which the harmonic oscillations amplitude is multiplied, its inputs being connected to the input of the second flip-flop and the output of the second memory, whereas outputs of this last register are connected to the respective inputs of the synchronization unit.

14. A system as claimed in claims 4,6 and 9 through 13, wherein the synchronization unit of the digital controlled random actions simulator comprises: two flip-flops and two conjunctors intended for forming two non-overlapping pulse trains; a first disjunctor whose output is connected to the input of the first flip-flop whose output is connected to the input of the second flip-flop and a respective input of the first disjunctor, the output of the second flip-flop being connected to first inputs of first and second conjunctors whose second inputs are combined and connected to the input of the second flip-flop, the output of the first conjunctor being connected to the input of the result accumulator; a shift register intended to form a sequence of control potentials;; one more conjunctor and a second disjunctor, intended for forming signals to control operation of the result accumulator, the output of this conjunctor being connected to the input of the first distributor, its input being connected to an input of the shift register whose other input is connected to the output of the first flip-flop, the output of the second conjunctor, the input of the first disjunctor and the input of the result accumulator, the outputs of the shift register being respectively connected to the inputs of the second disjunctor, the input of the third conjunctor and the input of the first disjunctor, the inputs of the second disjunctor also being connected to the outputs of the result accumulator, whereas its output is connected to the input of the first conjunctor;; four more conjunctors and one more flip-flop, the output of the fourth conjunctor being connected to the input of the second flip-flop, the input of the third flip-flop being connected to the input of the fifth conjunctor and the output of the first flip-flop, the output of the fifth conjunctor being connected to a respective input of the first disjunctor, the input of the sixth conjunctor being connected to the input of the fourth conjunctor and the output of the pulse generator, the input of the fourth conjunctor being connected to the output of the first flip-flop, the input of the seventh conjunctor being connected to the input of the third flip-flop, the input of the fifth conjunctor and the output of the sixth conjunctor, the input of the seventh conjunctor being connected to the output of the third flip-flop whose output is connected to the input of the fifth conjunctor, the inputs of the sixth conjunctor being connected to a respective input o the seventh conjunctor, the output of the first flip-flop and the output of the first distributor, the output of the seventh conjunctor being connected to the input of the result accumulator.

15. A method of testing objects for random actions as set forth in the preceding claims and substantially as hereinbefore described with reference to the accompanying drawings.

16 A digital simulator-computer system, substantially as hereinbefore described with reference to the accompanying drawings.