GB2029658A - Digital-to-analog converter - Google Patents
Digital-to-analog converter Download PDFInfo
- Publication number
- GB2029658A GB2029658A GB7921789A GB7921789A GB2029658A GB 2029658 A GB2029658 A GB 2029658A GB 7921789 A GB7921789 A GB 7921789A GB 7921789 A GB7921789 A GB 7921789A GB 2029658 A GB2029658 A GB 2029658A
- Authority
- GB
- United Kingdom
- Prior art keywords
- leads
- mosfets
- control signal
- voltage divider
- mosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000004044 response Effects 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 47
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 20
- 229910052814 silicon oxide Inorganic materials 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229960002050 hydrofluoric acid Drugs 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- ZLMUYRIFFZDBSE-UHFFFAOYSA-H chromium hexafluoride Chemical compound F[Cr](F)(F)(F)(F)F ZLMUYRIFFZDBSE-UHFFFAOYSA-H 0.000 description 1
- 229910021567 chromium(VI) fluoride Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
- Analogue/Digital Conversion (AREA)
- Attenuators (AREA)
Abstract
In a digital-to-analog converter, one of junctions P1 to P8 between voltage divider resistors R1 to R8 is selected by enhancement mode MOSFETs E11 to E32, Figure 3, or E1 to E8, Figure 8, turned on or off in response to the input digital signal at T11-T32 or T1 to T8, and depletion mode MOSFETs D11 to D32 or D2 to D87, which are permanently on, are arranged as shown to provide improved operation. The circuit can be produced on an integrated circuit of small area with a simple connection arrangement (some process details given). <IMAGE>
Description
SPECIFICATION
Voltage divider
The present invention relates to a voltage divider whose voltage division ratio can be varied in response to an input digital signal. More particularly, it relates to a voltage divider which employs Metal-Oxide Semiconductor field-effect transistors (hereinafter abbreviated to "MOSFETs").
Analog-digital converts are known, for example, one of a construction disclosed on pages 154 and 155 in a
publication entitled 'IEEE International Solid-State Circuits Conference (1976)'. This analog-digital converter
comprises a digital-analog converter which provides an analog voltage as an output formed from fixed reference voltage divided in response to an input digital signal, a comparator which compares an analog signal, to be converted into a digital signal, with the output of the digital-analog converter, and a control logic circuit which receives an output of the comparator and which provides the output digital signal in response thereto. The output of the control logic circuit is applied to the digital-analog converter to form the input digital signal.The digital-analog converter employed in such analog-digital converter has the same function as that of a voltage divider which divides a predetermined reference voltage in response to an input digital signal and which delivers the divided voltage as an output. Hence, the voltage divider of the present invention may be used as the digital-analog converter as described above. However, there are various other uses, and this invention is applicable to the wide variety of uses.
The voltage divider for use as the digital-analog converter, described in the above referred to publication, is made up of a large number of resistance elements which are connected in series, and a large number of switches which are connected in leads connecting the ends of the respective resistance elements to an output terminal. The input digital signal is used to provide switching control signals for the switches. If such a voltage divider is produced using a MOS integrated circuit, a method is known wherein diffused layers formed in a semiconductor substrate are employed as the resistance elements, while MOSFETs formed in the same substrate are employed to form the switches. With such a method, there is the problem of wiring control signal lines so that they are electrically connected to the gate electrodes of the MOSFETs.For example, in the case where the control signal lines are formed in a region separate from the diffused resistance layers and the MOSFETs, there is the disadvantage that the area of the semiconductor chip continuing the integrated circuit becomes large. A method wherein an insulating layer is formed on the surface of a semiconductor in which the diffused resistance layers and the MOSFETs are formed is also known, the control signal line being formed on the insulating layer and the insulating layer being cut away only in required places so as to connect the control signal lines and the gate electrodes of the MOSFETs.
With this method, however, an undesired Metal-Oxide-Semiconductor (hereinafter abbreviated to MOS) structure is formed between the control signal line and the semiconductor substrate. The structure is usually called the parasitic MOS. There is the possibility that the voltage divider will not perform its desired function due to the parasitic MOS.
According to the present invention there is provided a voltage divider comprising: a series circuit in which a plurality of impedance elements are connected in series; a reference voltage source for applying a reference voltage across both ends of said series circuit; an output terminal for deriving an output voltage by dividing said reference voltage; a plurality of leads for electrically connecting series connection points of the respective impedance elements and said output terminal; a plurality of control signal lines which are each arranged so as to intersect with at least one of the plurality of leads and to which control input signals for determining a voltage division ratio are applied; and MOSFETs which are arranged in at least one of the intersections between the respective leads and the respective control signal lines and which have their source electrodes and drains connected to said leads and their gate electrodes connected to said control signal lines; said MOSFETs being enhancement mode MOSFETs in the intersecting portions in which signals
of said leads are to be turned "on" and "off" in response to said control input signals, and being depletion
mode MOSFETs in the intersecting portions in which the signals of said leads are to be turned "on" at all times irrespective of said control input signals.
In a first embodiment of the present invention, the MOSFETs are arranged in all intersections between the respective leads and the respective control signal lines and the enhancement mode MOSFETs and the depletion mode MOSFETs are arranged alternately.
According to a second embodiment, the plurality of leads are formed into M stages (M being an integer), the leads of the first stage being connected to connection points of the impedence elements and each lead of the second to M-th stages are connected to pairs of leads to the immediately preceding stage.
In such an embodiment, the control lines are provided in pairs for each stage and each control line is arranged so as to intersect with all the leads of the respective stage, one line of each pair of control lines having a digital control signal applied thereto and the other line of the pair having the inverted signal of the digital signal applied thereto. Pairs of the MOSFETs are then connected to each lead of each stage, one of the pair of MOSFETs being an enhancement mode MOSFET and the second being a depletion mode MOSFET.
According to a third embodiment of the present invention, each lead has an enhancement mode MOSFET, each MOSFET being connected to a respective control signal lead. Depletion mode MOSFETs are arranged in all other intersections between the control signal lines and the leads. Also, in such an embodiment, a plurality of input terminals are provided, one connected to each of the control signal lines and located outside the interconnection portion of the leads, control signals being applied to the terminals.
The present invention will now be described in greater detail, by way of example, with reference to the accompanying drawings, wherein:
Figure 1 is a schematic view showing the structure of a MOSFET;
Figures 2A and 2B are graphs showing drain electrode current versus source to gate voltage characteristics of a depletion mode MOSFET and an enhancement mode MOSFET, respectively;
Figure 3 is a circuit diagram showing a first embodiment of a voltage divider according to the present invention;
Figure 4A is a diagram showing an interconnection pattern of a part of the circuit of Figure 3;
Figure 4B is a sectional view taken along the line X - X' in Figure 4A;
Figures 5A to 5H show stages in the manufacturing process for the embodiment of the voltage divider shown in Figure 3;;
Figure 6 is a diagram showing an interconnection pattern of a voltage divider according to the first embodiment of the present invention, when formed as an integrated circuit;
Figures 7A and 7B are diagrams showing "on" resistance characteristics of MOSFETs in the embodiment illustrated in Figure 6; and
Figure 8 is a circuit diagram of a voltage divider according to a second embodiment of the present invention.
Before describing a first embodiment of a voltage divider according to the present invention, a MOSFET of the depletion mode and a MOSFET of the enhancement mode will be explained with reference to Figures 1, 2A and 2B to facilitate understanding of the present invention.
In Figure 1 showing the structure of the MOSFET, a silicon substrate 1 of P-conductivity type has a source region 2 of N+ -conductivity type which is formed in the P-type substrate 1, a drain region 3 of N+ -conductivity type. On the surface of the silicon substrate 1 a silicon oxide (SiO2) film 4 is formed, on which a gate electrode 5 is formed. A source electrode 6 and a drain electrode 7 are formed directly onto the source region 2 and the drain region 3 respectively, without the intervention of an oxide film. Electrons tend to accumulate on the interface between the P-type silicon substrate 1 and the silicon oxide film 4 to change the conductivity type of the silicon into N-type semiconductor. If the resistance value of the P-type silicon substrate 1 is high, there are a few mobile holes.Hence, the surface region underneath the oxide film 4turns into N-type semiconductor, and a thin channel layer 8 develops on the interface. Depending upon a voltage
VGS applied between the gate and source electrodes, a drain current ID flows in accordance with the characteristic curve illustrated in Figure 2A. More specifically, this MOSFET has a characteristic in which the
FET turns "on" when the voltage VGS is zero, the drain current ID decreases gradually as the voltage VGS is increased in the negative direction, and the FET reaches a cut off state at a predetermined threshold value
VthD. The MOSFET having such a characteristic is called a MOSFET of the depletion mode.In contrast to the above, if the resistance value of the P-type silicon substrate 1 is low, the tendency to turn into N-type semiconductor diminishes. For this reason, the characteristic of the drain current 1D versus the gate-source voltage VGs is represented by the curve illustrated in Figure 2B. More specifically, the drain current ID does not flow at voltages below a predetermined threshold value VthE, and it increases with the voltage VGS for voltages equal to and greater than the value VthE. A MOSFET having a characteristic as shown in Figure 2B is called a MOSFET of the enhancement mode.
A first embodiment of a voltage divider according to the present invention will now be described with reference to Figure 3. In the figure, resistors R1 to R8 are connected in series across the terminals of a reference voltage source Er. Although eight resistors are used in this embodiment, it is clear that the number of resistors can be selected arbitrarily. When eight resistors are used, output voltages with the reference voltage Ear varied in eight stages between zero and Er can be generated. In order to change the voltage division ratio, control signals of 3 bits (A, B, C) are used. It is clear that as the number of resistors increases, the required number of bits of the control signals increases accordingly.Leads L1 to L7 are respectively taken out from the connections P1 to P8 between the resistors R1 to R8 connected in series, and a pair of MOSFETs are inserted in each lead to provide switching elements. In this embodiment, one of the pair of MOSFETs is of the depletion mode, and the other is of the enhancement mode and each are arranged alternately in successive leads L1 to L8. For example, in the lead L1, an enhancement mode MOSFET E11 and a depletion mode MOSFET D1, are connected in series. For the sake of convenience in the description, leads L1 to L8 (lead
L8 is connected to the terminal of the resistor R8 remote from the resistor R7) shall be termed the first stage of leads, and the MOSFETs connected in the leads L1 to L8 shall be termed the first stage of MOSFETs.
The gate electrodes of MOSFETs on one side of the paired MOSFETs connected in series with the respective leads L1 to L8 (the left hand side in Figure 3) are connected to a control signal line 811 while the gate electrodes of the MOSFETs on the other side are connected to a control signal line S12. The control signal lines S11 and S12 are connected to control signal input terminals T11 and T12 respectively. It may be noted that, because the enhancement mode MOSFETs and the depletion mode MOSFETs are alternately connected to each control signal line and with the control signal line S11 is taken as an example, it is clear that the enhancement mode MOSFETs E11, E13. E15 and E17 and the depletion mode MOSFETs Da2, Da4, D16 and D18 are alternately connected thereto. A control signal A is applied to the control input terminal T, while a control signal A, which is the signal A inverted, is applied to the terminal T12. Thus, when a signal of logic level "1" is applied to the terminal T11, a signal of logic level "0" is applied to the terminal T12. Conversely, when the signal of logic level "0" is applied to the terminal T11, the signal of logic level "1 " is applied to the terminal T12.
Pairs of the first stage of leads L1 to L8 are connected together to form a second stage of leads M1 to M4.
That is, the leads L1 and L2 are both connected to a lead M1 in the second stage, the leads L3 and L4 are both connected to a lead M2, the leads L8 and L6 are both connected to a lead M3, and leads L7 and L8 are both connected to a lead M4. A pair of MOSFETs are connected in series to each of the second stage of leads M1 to
M4. Similarly to the first stage, one of the pair of MOSFETs is of the enhancement mode, and the other is of the depletion mode and are arranged alternately in successive leads M1 to M8. For example, an enhancement mode MOSFET E21 and a depletion mode MOSFET D21 are inseted in series in the lead Ml, and a depletion mode MOSFET D22 and an enhancement mode MOSFET E22 are connected in series in the lead M2.The gate electrodes of MOSFETs on one side of the paired MOSFETs (the left hand side in Figure 3) connected to the second stage of leads M1 to M4 are connected to a control signal line S21, while the gate electrodes of the
MOSFETs on the other side are connected to a control signal line S22 The control signal lines S21 and S22 are connected to control signal input terminals T21 and T22 respectively. The control signal B is applied to the terminal T21, while the inverted signal B of the signal B is applied to the terminal T22.
Further, the second stage of leads M1 and M2 are connected together and to a lead N1 in a third stage, and the leads M3 and M4 are connected together and to a lead N2 in the third stage. An enhancement mode
MOSFET E31 and a depletion mode MOSFET D31 are inserted in series in the lead N1, and a depletion mode
MOSFET D32 and an enhancement mode MOSFET E32 in the lead N2. The gate electrodes of the MOSFETs E31 and D32 are connected to a control signal line S31, and the gate electrodes of the MOSFETs D31 and E32 to a control signal line S32.The control signal C is applied to a terminal T31 to which the control signal line 53i is connected, while the inverted control signal C of the signal C is applied to a terminal T32 to which the control signal line S32 is connected. The third stage of leads N1 and N2 are connected together and then connected to an output terminal Tol. Since, in this embodiment, the voltage division ratio of the voltage divider circuit consisting of the eight resistors is controlled by the three bits of digital control signals (A, B, C), the group of
MOSFETs are formed in three stages. It is obvious, however, that the number of stages of MOSFETs increases with an increase in the number of resistors.
A suitable magnitude, which is greater than the threshold voltage VthE illustrated in Figure 2B, is selected as the voltage of the digital control signals (A, B, C) corresponding to the logic level "1", and a voltage of substantially zero volts is selected as the voltage corresponding to the logic level "0". Hence, the depletion mode MOSFETs D11 to D32 of the MOSFETs shown in Figure 3 are in conductive or "on" state at all times irrespective of whether the control input signals applied to their gate electrodes are of the logic level "1 " or the logic level "0". However, the enhancement mode MOSFETs are in the conductive or "on" state when the voltages applied to the gates are of the logic level ,whereas they are in the non-conductive or "off" state when the applied voltages are of the logic level "0".
Consider now a case where the control input signals (A,B,C) are (0,0,0). In this case, the signals of logic level "0" are applied to the terminals T11, T21 and T31, and the signals of logic level "1 " are applied to the terminals T12, T22 and T32. In consequence, all the MOSFETs D18, E18, D24, E24, D32 and E32 turn "on", so that the potential of a voltage division point P8 in the resistance circuit appears at the output terminal Tol.
In the case where the control input signals (A, B, C) are (1, 0, 0), the signals of the logic level "1" are applied to the terminals T11, T22 and T32, and the signals of logic level "0" are applied to the terminals T12, T21 and T31.
At this time, the enhancement mode MOSFET E18 is turned "off" by the logic level "0" signal applied to the terminal T12, so that the circuit between the voltage division point P8 and the output terminal Tol becomes "off". On the other hand, all the MOSFETs E17, D17, D24, E24, D32 and E32 turn "on", so that the potential of a voltage division point P7 appears at the output terminal To1. In the same way, voltages indicated in Table 1 below are obtained between output terminals Tol and T02 in correspondence with the changes of the control input signals (A, B, C). In the following table, the potentials of voltage division points
P1 to P8 are denoted by the same symbols P1 to P8 in order to simplify the explanation.
Table 1
(C, B, A) Output
(0,0,0) P8
(0,0,1) P7
(0,1,0) P6 (0,1,1) P5 1,0,0) P4
(1,0,1) P3
(1,1,0) P2 (1, 1, 1) P1 As is apparent from the above description, according to the embodiment shown in Figure 3, the voltages
obtained by dividing the voltage of the reference voltage source Er by the different voltage division ratios are
provided from the output terminal Tol in response to the digital signals applied to the control signal input
terminal T11, T12, T21, T22, T31 and T32.
Figure 4A shows the MOS structure pattern of a part of the circuit when the circuit of the voltage divider
shown in Figure 3 is formed from a MOS integrated circuit. Figure 4B is a sectional view taken along line X
X' in Figure 4A.
Referring to Figure 4B, a semiconductor substrate 10 of P-conductivity type is made of, for example,
silicon. In the substrate 10, a diffused resistance layer 12 of the N±conductivity type is formed in a portion corresponding to the interconnection patterns of the resistors R1 to R8 and the leads L1 to L8, M1 to M4 and N1 to N2. Thus, a part of the diffused resistance layer 12 is used to form the resistors R1 to R8, and the other part
is used to form the leads for deriving the divided voltages to the output terminal. Parts in which the
resistance layer 12 and the control signal lines (for example, S11 and S12) intersect become the switches.
More specifically, silicon oxide films 14 are formed on the surfaces of those regions in the semiconductor substrate 10 which correspond to the intersecting portions, and polycrystalline silicon layers 16 are formed
on the oxide film 14. In this structure, parts of the diffused resistance layer 12 serve as source and drain
electrodes, and the regions underneath the silicon oxide films 14 serve as channels, so that MOSFETs are
formed. The polycrystalline silicon layers 16 are used as the gate electrodes ofthe MOSFETs, and are also
used as the control signal lines (for example, S11 and S12) for applying the switching control input signals to the MOSFETs.An insulating layer 18 made of, for example, phospho-silicate glass is formed to cover the
surfaces of the diffused resistance layer 12 and the polycrystalline silicon layers 14.
Since, in the embodiment described above, the resistors R1 to R8 and the leads L1 to L8, M1 to M4 and N1 to
N2 are formed from the same diffused resistance layer 12, the leads have resistance values which are not
negligible. However, in the case where the input impedance of a device connected to the output terminals Tol and To2, (for example, a comparator) is sufficiently greater than the resistance values, voltages which are
determined by the voltage division ratios based on the resistors R1 to R8 are obtained as outputs irrespective
of the resistance values of the leads.
Now, an example of a manufacturing method for the voltage divider shown in Figures 3, 4A and 4B will be
described with reference to Figure 5.
As illustrated in Figure 5(A), a semiconductor substrate 10 of P-conductivity type, made of silicon (Si), is
heated to form a silicon oxide (SiO2) film 11 on the surface thereof. Subsequently, a photoresist layer 13 is
applied onto the silicon oxide film 11 corresponding to a region which is the intersecting portion between a
lead and a control signal line in the voltage divider, that is, a region in which a MOSFET isto be formed. The
part of the silicon oxide film 11 which is not coated with the photoresist layer 13 is then removed with an etchant consisting of, for example, fluoric acid and chromium hexafluoride.In the region of the
semiconductor substrate 10 from which the silicon oxide film 11 has been removed, boron (B) is diffused into
the semiconductor substrate 10 by the use of ion implantation, diffusion techniques or similar methods.
Thus, a P±conductivity type layer 15 is formed in the surface layer of the semiconductor substrate 10 (Figure
5(B)). The P+ layer 15 is used for electrically insulating the MOSFET from other circuit elements.
The silicon oxide film 11 and the photoresist layer 13 shown in Figure 5(B) are removed, and a mask layer
17 made of silicon nitride (SiN3) of a similar substance is formed on the removed part (Figure 5(C)). The semiconductor substrate 10 is then heated. Except for the part covered by the mask layer 17, the surface of the semiconductor substrate 10 is thus oxidized, and a comparatively thick silicon oxide film 19 is formed.
The mask layer 17 is then removed by etching (Figure 5(D). When the semiconductor substrate 10 is further heated, a thin silicon oxide film 14 is formed, as shown in Figure 5(E). From above the silicon oxide film 14, phosphorus (P) or boron (B) is ion-implanted. Normally, phosphorus is employed to make a depletion mode
MOSFET, and boron to make an enhancement mode MOSFET. In this way, a channel layer 20 is formed underneath the silicon oxide film 14. Subsequently, a polycrystalline silicon layer is formed on the surface of the thin silicon oxide film 14. That part of the polycrystalline silicon layer which corresponds to the gate region of the MOSFET is coated with a photoresist layer, whereupon the polycrystalline silicon layer is etched with an etchantwhich consists of fluoric acid and nitric acid (NH3).As a result, as shown in Figure 5(F), a polycrystalline silicon layer 16 is formed only at the part of the silicon oxide film 14 corresponding to the gate electrode of the MOSFET. Further, those areas of the silicon oxide film 14 which correspond to the source and drain of the MOSFET are removed with an etchant which consists of fluoric acid and chromium hexaiuoride. At the next step, phoshorus (P) is diffused or ion-implanted from the surface of the semiconductor substrate 10 in the parts having had the silicon oxide film 14 removed, to form N+#conductivity type layers 12 in the semiconductor substrate 10 in the vicinity of the surface (Figure 5(G)).
One of the two N±conductivity type layers 12 serves as the source electrode, and the other serves as the drain electrode, with the channel layer 20 formed between them. An insulating layer 18 which is made of phospho-silicate glass in then formed on the surface of the resultant semiconductor substrate 10.
In the semiconductor device formed as described above, the N±conductivity type layer 12 is used as the source and drain electrodes of the MOSFETs, and simultaneously, its parts are used as the resistors R1 to R8 and the leads L1 to L8, M1 to M4 and N1 and N2. Of the MOSFETs those of the enhancement mode are employed as the switches for turning "on" and "off" the signals of the leads, and those of the depletion mode turn "on" at all times and are employed as signal transfer paths being parts of the leads. In addition, the polycrystalline silicon layer 16 is used as the gate electrode of the MOSFET, and simultaneously as the control signal line for supplying the controlling input signal to the gate electrode. The thick silicon oxide layer 19 and the P+ layer 15 are used for the insulation between the plurality of MOSFETs.
A voltage divider according to the first embodiment of the present invention as described above with reference to Figures 3, 4A, 4B and 5 has several advantages.
Firstly, the control line pattern is not formed in any part of the semiconductor other than the MOSFETs and the diffused resistance pattern which forms the leads, but both the patterns are formed on over the other.
Therefore, the area of the semiconductor chip that is required can be reduced.
Secondly, no insulating layer intervenes between the control line pattern and the gate electrodes of the
MOSFETs, and parts of the control line pattern are also used as the gate electrodes. Therefore, contacts for electrically connecting the control line pattern to the gate electrodes become unnecessary, and the semiconductor chip area can be reduced by an area otherwise required for forming the contacts. Also, in the case where the control line pattern are formed on the semiconductor substrate through the insulating layer, it is possible that a parasitic MOS will be formed to cause malfunction of the voltage divider. According to this embodiment, this malfunction cannot occur.
Thirdly, the insulating layer is formed to cover the control signal line pattern and the surface of the semiconductor substrate, and any interconnection for the voltage divider does not exist on the surface of the insulating layer, so that an interconnection for another purpose can be located on the insulating layer. By way of example, in the case where a conductive layer of aluminium is formed on the entire surface of the insulating layer and where it is held at the earth potential, the voltage divider is shielded and the induction of external noise is prevented.In the case (for example in a comparator) where a voltage divider and a control logic circuit are to be formed on a single semiconductor chip and where the voltage divider is arranged on the central part of the chip and the comparator and control logic circuit are arranged on either side of the chip, a signal line between the comparator and the control logic circuit can be formed on the insulating layer.
Figure 6 is an interconnection pattern diagram which shows the first embodiment of a voltage divider according to the present invention when formed as an integrated circuit. In the figure, the same reference symbols as in Figures 3 and 4A denote similar elements. As the number of stages of the switch columns of the voltage divider increases, the number of the leads decreases by a half each stage, so that a margin develops in the chip area. Thus, the dimensions of the switching MOSFETs are increases with an increase in the number of stages, whereby the "on" resistances of the MOSFETs are lowered.
In Figure 6, the width of the lead pattern L1 to L8 in the first stage is designed to be wl, the width of the lead pattern M1 to M4 in the second stage is designed to be w2, and the width of the lead pattern N1 to N2 in the third stage is designed to be W3. Here, the relationship w < w2 < w3 holds for the widths wl, w2 and w3.
However, the width of the control signal line patterns S11 and S12 in the first stage is designed to bey1, that in the second stage is designed to be Z3. In this embodiment, these widths are equal so thatz1 = z2 = Z3. Hence, the relationship~ W2 ~ 3holds.
zi Z2 z3
In general, the resistance RON at the time when a MOSFET turns "on" is expressed by the following equation: 1 (1)
RON where ss denotes the channel conductance constant, z the channel length of the MOSFET, wthe channel width of the MOSFET, VGS the gate-source voltage of the MOSFET, and Vth the threshold voltage of the
MOSFET. As is apparent from equation (1), the "on" resistance RON of the MOSFET is inversely proportional to (channel width/channel length). It is thus clear that, in case of the embodiment shown in Figure 6, the
MOSFETs of the higher stage have a lower "on" resistance.
Figure 7A shows characteristics curves with the values w/z on the axis of the abscissa and the "on" resistances of MOSFETs on the axis of the ordinate. The curve a is the characteristic of an enhancement mode MOSFET, and the curve b is the characteristic of a depletion mode MOSFET. in the graph, rEl, rE2, and r83 denote the "on" resistances of the enhancement mode MOSFETs in the first stage, second stage and third stage, respectively, and rD1, rD2 and rl, denote the "on" resistances of the depletion mode MOSFETs in the first stage, second stage and third stage, respectively. Thus, the summation of the "on" resistances of the
MOSFETs from the first stage to the higher stages is expressed as shown in Figure 7B.In this figure, the axis of the abscissa represents the number of stages, while the axis of the ordinate represents the summaton of the "on" resistances of the MOSFETs. As is clear from the graph, in the case where the group of switches constructed from MOSFETs are formed into any desired number (j) of stages, the summation TRON of the "on" resistances of the MOSFETs from the first stage to the j-th stage of this embodiment is expressed by the following equation::
Alternatively, in the case where the ratio wlz between the width w of the lead patterns and the width z of the control signal line patterns from the first stage to the j-th stage is made equal to the ratio w11z1 in the first stage, the summation of the "on" resistances of the MOSFETs from the first stage to the j-th stage becomes j.(rE1 + rD1). Hence, when the present embodiment is compared to this case, the summation of the "on" resistances decreases to the amount of:
This decrease of the summation of the "on" resistances of the MOSFETs from the first stage to the j-th stage means that the impedances of the paths, which extend from the respective voltage division points of the voltage dividing resistors R1 to R8 to the output terminal of the voltage divider, lower.The voltage of each voltage division point is divided by the above impedance and the input impedance of a device connected to the output terminal of the voltage divider, and then appears at the output terminal. Therefore, the lowering of the impedances between the respective voltage division points of the resistors R1 to R8 and the output terminal of the voltage divider has the effect that the voltage division outputs can be obtained without being affected by the input impedance of the device connected to the output terminal of the voltage divider.
Figure 8 shows a second embodiment of a voltage divider according to the present invention. It differs from the embodiment of Figure 3 in the pattern of the MOSFETs connected between the voltage division points P1 to P8 of the voltage dividing resistors R1 to R8 and the output terminal T01 and in the lead patterns.
More specifically, in the third embodiment, leads K1 to K8 are connected in parallel between the respective voltage division points P1 to P8 and the output terminal To1. A single MOSFET is connected in the lead K1, two series MOSFETs are connected in the lead K2, three series MOSFETs are connected in the lead K3, and eight series MOSFETs are connected in the lead K3, and eight series MOSFETs are connected in the lead K8. A single enhancement-mode MOSFET (one of E1 to E8) is connected in each of the leads K1 to K8 and all the other MOSFETs are of the depletion mode. Using the lead K4 as an example, one enhancement-mode
MOSFET E4 and three depletion-mode MOSFETs D41, D42 and D43 are connected in series therein.
Also, control signal lines S, to S8 are respectively connected to control signal input terminals T, to T8. The gate electrodes of eight MOSFETs are connected to the control signal line So, the gate electrodes of seven
MOSFETs to the control signal line S2, the gate electrodes of six MOSFETs to the control signal line S3, and the gate electrode of one MOSFET to the control signal line Ss. In each of the control signal lines Si to S8, a single enhancement-mode MOSFET (one of Ea to E8ì is connected, and all the other MOSFETs are of the depletion mode.For example, the control signal line S5 has the gate electrodes one one enhancement-mode
MOSFET E5 and three denletion-mode MOSFETs D65, D75 and D88 connected thereto.
The operation of the second embodiment will now be described. Consider the case where a control signal of logic "1" is applied to the terminal T1 and where control signals of logic "0" are applied to all the other terminals T2 to T8. In this case, the enhancement mode MOSFETs E1 turns "on", and the other enhancement mode MOSFETs E2 to E8 turns "off". Thus, the potential of the voltage division point P1 appears at the output terminal iol. In the case where the signal of logic "1" is applied to the terminal T2 and where the signals of logic "0" are applied to the other terminals T, and T3 to T8, the enhancement mode MOSFET E2 turns on and the other enhancement mode MOSFETs E1 and E3 to E5 turn "off". As previously stated, the depletion mode MOSFETs turn "on" at all times irrespective of whether the signals applied to their gates are logic "1" or the logic "0". Therefore, the potential of the voltage division point P2 appears at the output terminal Tol through the MOSFETs D2 and E2.In this manner, outputs as indicated in the following Table 2 are obtained in response to signals applied to the terminals T1 toT8: Table 2
(T1, T2, T3, T4, T5, T6, T7, T8) Output
(1, 0, 0, 0, 0, 0, 0, O,) P1
(0, 1, 0, 0, 0, 0, 0, 0,) P2
(0, 0, 1, 0, 0, 0, 0, 0,) P3
(0, 0, 0, 1, 0, 0, 0, 0,) P4
(0, 0, 0, 0, 1, 0, 0, 0,) P5
(0, 0, 0, 0, 0, 1, 0, O,) P8 (0, 0, 0, 0, 0, 0, 1, 0,) P7
(0, 0, 0, 0, 0, 0, 0, 1,) P8
Hence, output voltages divided in response to the digital signals of the control inputs are obtained as in the embodiment illustrated in Figure 3. Although the second embodiment requires a larger number of MOSFETs than first embodiment shown in Figure 3, it has the advantage that the logics of the control input signals are simpler as is clear from Table 2.
Three embodiments of this invention have been described above, various modifications are possible within the scope of the present invention. For example, the number of the voltage dividing resistors R1 to R8 can be arbitarily selected. The method of manufacturing the voltage divider according to this invention as illustrated in Figure 5 is an example, and the voltage divider can, of course, be fabricated by other methods.
Although MOSFETs having the N-channels only have been referred to, it is also possible to employ
P-channel MOSFETs.
As is clear from the above description, according to the present invention, MOSFETs are formed in all the intersecting portions between control signal line patterns and lead patterns for deriving output voltages. In the case where the intersecting portion is to perform the switching function, the MOSFET is of the enhancement mode, and in the case where the intersecting portion does not perform the switching function, the MOSFET is of the depletion mode. Thus, it becomes possible to use parts of the control signal line patterns as the gate electrodes of the MOSFETs. As a result, the size of the control signal line patterns can be reduced and a structure which has no parasitic MOS between the control signal line and the semiconductor substrate is obtained.
Claims (10)
1. A voltage divider comprising: a series circuit in which a plurality of impedance elements are connected in series; a reference voltage source for applying a reference voltage across both ends of said series circuit; an output terminal for deriving an output voltage by dividing said reference voltage; a plurality of leads for electrically connecting series connection points of the respective impedance elements and said output terminal; a plurality of control signal lines which are each arranged so as to intersect with at least one of the plurality of leads and to which control input signals for determining a voltage division ratio are applied; and MOSFETs which are arranged in at least one of the intersections between the respective leads and the respective control signal lines and which have their source electrodes and drains connected to said leads and their gate electrodes connected to said control signal lines; said MOSFETs being enhancement mode MOSFETs in the intersecting portions in which signals of said leads are to be turned "on" and "off" in response to said control input signals, and being depletion mode MOSFETs in the intersecting portions in which the signals of said leads are to be turned "on" at all times irrespective of said control input signals.
2. A voltage divider according to claim 1, wherein; said plurality of leads are formed into M stages (M being an integer), the leads of the first stage being connected to connection points of the impedance elements and each lead of the second to M-th stages are connected to pairs of leads of the immediately preceding stage; said control lines are provided in pairs for each stage and each control line is arranged so as to intersect with all the leads of the respective stages, one line of each pair of control lines having a digital control signal applied thereof and the other line of the pair having the inverted signal of the digital signal applied thereto; and pairs of said MOSFETs are connected to each lead of each stage, one of the pair of
MOSFETs being an enhancement mode MOSFET and the second being a depletion mode MOSFET.
3. A voltage divider according to claim 2, wherein the pairs of MOSFETs are arranged in all intersections between the respective leads and the respective control signal lines, the enhancement mode MOSFET and the depletion mode MOSFET of each pair being arranged alternately in the leads.
4. A voltage divider according to claim 1, wherein: each lead has an enhancement mode MOSFET, each
MOSFET being connected to a respective control signal lead; depletion mode MOSFETs being arranged in all other intersections between said control signal lines and said leads.
5. A voltage divider according to any one of the preceding claims, wherein a plurality of input terminals are located outside the interconnection portion of the leads, one of said terminals being connected to each of said control signal lines, and control signals being applied to said terminals.
6. A voltage divider according to any one of the preceding claims 1 to 5 wherein said impedance elements, the connection lines thereof and said leads are made up of a diffused resistance layer which is formed in a semiconductor substrate.
7. A voltage divider according to any one of the preceding claims 1 to 5, wherein each MOSFET arranged in intersections between the control signal line and the lead includes source and drain regions which are formed in regions spaced from each other in a semiconductor substrate, a channel layer which is formed between said source and drain regions, and a gate electrode which is formed on said channel layer through an insulating film, said gate electrode being used simultaneously as a part of said control signal line.
8. A voltage divider according to any one of the preceding claims 1 to 5, wherein each MOSFET arranged in the intersections portion between the control signal line and the lead includes source and drain regions which are formed in regions spaced from each other in a semiconductor substrate, and a channel layer which is formed between said source and drain regions, a part of said lead being used simultaneously as said source and drain regions.
9. A voltage divider according to any one of claims 2 to 4, wherein a ratio wto z between a width w of the lead of an N-th stage (N being an integer which satisfies the relationship 1 < N6M) and a width z of the control line is made greater than the corresponding ratio in the immediately preceding stage.
10. A voltage divider substantially as herein described with reference to Figure 3, or Figures 4A, 4B and 6, or Figure 8 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9043478A JPS5518016A (en) | 1978-07-26 | 1978-07-26 | Voltage divider |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2029658A true GB2029658A (en) | 1980-03-19 |
Family
ID=13998493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB7921789A Withdrawn GB2029658A (en) | 1978-07-26 | 1979-06-22 | Digital-to-analog converter |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS5518016A (en) |
| DE (1) | DE2930375A1 (en) |
| FR (1) | FR2432241A1 (en) |
| GB (1) | GB2029658A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4354175A (en) * | 1980-05-01 | 1982-10-12 | Mostek Corporation | Analog/digital converter utilizing a single column of analog switches |
| EP0065022A1 (en) * | 1981-05-16 | 1982-11-24 | Deutsche ITT Industries GmbH | Integrated voltage divider with selection circuit in IGFET technique, a modification thereof and its use in a DA converter |
| US9607569B2 (en) | 2014-09-05 | 2017-03-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, electronic component, and electronic device |
| US9780779B2 (en) | 2015-08-07 | 2017-10-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, electronic component, and electronic device |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3026361A1 (en) * | 1980-07-11 | 1982-02-04 | Siemens AG, 1000 Berlin und 8000 München | ELECTRICAL RESISTANCE FOR INTEGRATED SEMICONDUCTOR CIRCUITS MADE OF AT LEAST TWO MONOLITICALLY SUMMARY MIS FIELD EFFECT TRANSISTORS |
| JPS58117726A (en) * | 1982-01-05 | 1983-07-13 | Matsushita Electric Ind Co Ltd | Signal switching circuit |
| JPS5980010A (en) * | 1982-10-27 | 1984-05-09 | テクトロニツクス・インコ−ポレイテツド | Programmable attenuator |
| JP2931440B2 (en) * | 1991-06-05 | 1999-08-09 | 旭化成マイクロシステム株式会社 | Multi-channel D / A converter |
| JP3922261B2 (en) | 2004-03-08 | 2007-05-30 | セイコーエプソン株式会社 | Data driver and display device |
| JP2005072609A (en) * | 2004-09-27 | 2005-03-17 | Fujitsu Ltd | Semiconductor device |
| US8669781B2 (en) | 2011-05-31 | 2014-03-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| JP6882861B2 (en) * | 2016-07-14 | 2021-06-02 | キヤノン株式会社 | Semiconductor devices, liquid discharge heads, liquid discharge head cartridges and recording devices |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5228851A (en) * | 1975-08-29 | 1977-03-04 | Nat Semiconductor Corp | Converter circuit |
-
1978
- 1978-07-26 JP JP9043478A patent/JPS5518016A/en active Granted
-
1979
- 1979-06-22 GB GB7921789A patent/GB2029658A/en not_active Withdrawn
- 1979-06-26 FR FR7916394A patent/FR2432241A1/en not_active Withdrawn
- 1979-07-26 DE DE19792930375 patent/DE2930375A1/en not_active Ceased
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4354175A (en) * | 1980-05-01 | 1982-10-12 | Mostek Corporation | Analog/digital converter utilizing a single column of analog switches |
| EP0065022A1 (en) * | 1981-05-16 | 1982-11-24 | Deutsche ITT Industries GmbH | Integrated voltage divider with selection circuit in IGFET technique, a modification thereof and its use in a DA converter |
| US4511881A (en) * | 1981-05-16 | 1985-04-16 | Itt Industries, Inc. | Integrated voltage divider with selection circuit |
| US9607569B2 (en) | 2014-09-05 | 2017-03-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, electronic component, and electronic device |
| US9780779B2 (en) | 2015-08-07 | 2017-10-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, electronic component, and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2432241A1 (en) | 1980-02-22 |
| DE2930375A1 (en) | 1980-02-07 |
| JPS6157710B2 (en) | 1986-12-08 |
| JPS5518016A (en) | 1980-02-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3855610A (en) | Semiconductor device | |
| US3339128A (en) | Insulated offset gate field effect transistor | |
| JP2681192B2 (en) | Field effect transistor | |
| US5023688A (en) | Transfer gate with the improved cut-off characteristic | |
| KR890003147B1 (en) | Gate array | |
| GB1561903A (en) | Fild effect transistors | |
| US4178605A (en) | Complementary MOS inverter structure | |
| US3586930A (en) | High frequency,high power igfet with interdigital electrodes and plural looped gate | |
| GB2029658A (en) | Digital-to-analog converter | |
| US3246173A (en) | Signal translating circuit employing insulated-gate field effect transistors coupledthrough a common semiconductor substrate | |
| KR950007353B1 (en) | Synapse mos transistor | |
| US4326136A (en) | Threshold circuit using complementary field effect transistors | |
| US4352092A (en) | Digital to analog converter | |
| US3333168A (en) | Unipolar transistor having plurality of insulated gate-electrodes on same side | |
| US3333115A (en) | Field-effect transistor having plural insulated-gate electrodes that vary space-charge voltage as a function of drain voltage | |
| US4627082A (en) | Semiconductor device for obtaining an accurate threshold voltage adjustment | |
| US4384300A (en) | Negative resistance device | |
| US4001612A (en) | Linear resistance element for lsi circuitry | |
| US4157557A (en) | Control circuit for signal transmission | |
| US4547681A (en) | Semiconductor device having contacting but electrically isolated regions of opposite conductivity types | |
| NL8203424A (en) | VARIABLE MISS RESISTANCE. | |
| US5309009A (en) | Integrated electrically adjustable analog transistor device | |
| JPS6111009B2 (en) | ||
| US3296508A (en) | Field-effect transistor with reduced capacitance between gate and channel | |
| JPH0444273A (en) | Insulated-gate field-effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |