GB2025182A

GB2025182A - Integrated frequency divider

Info

Publication number: GB2025182A
Application number: GB7921506A
Authority: GB
Original assignee: Ebauches SA
Current assignee: Ebauches SA
Priority date: 1978-07-06
Filing date: 1979-06-20
Publication date: 1980-01-16
Also published as: GB2025182B; JPS607860B2; DE2921511A1; FR2430696A1; JPS5537094A; CH631596GA3; DE2921511C2; CH631596B; FR2430696B1

Abstract

The frequency divider allows division of the frequency of two signals in phase opposition 01(t) and 02(t). A shift register 10 comprises an assembly of transistors and capacitors which form a plurality of cells connected one after the other, each cell being constituted by two identical stages T1T1' and T2T2' which are connected in series and are supplied respectively by the periodic signals. Means for detecting particular states of the register comprise the MOS transistor T8, T9, and T10. Means for producing a signal with a frequency which is a sub- multiple of that of the said periodic signals comprise the transistors T11 and T12, the transistor T13, the capacitor C7 and the capacitor C9. The divider is especially suitable for use in quartz oscillator watches. T13 normally conducts thus grounding the output point g, only when b, d, f are all high is T13 turned off and signal x, via C7, connected both to the output and to the shift register input to recirculate a charge packet. <IMAGE>

Description

SPECIFICATION Integrated frequency divider The present invention relates to an integrated frequency divider of very low consumption.

Such a circuit has a particularly interesting application in any type of small-size portable device, powered by a battery which is required to have a life time of up to several years. As is known, the energy consumption problem occurs particularly acutely when the frequency to be divided is high, as in the case, for example, in chronometric high performance quartz oscillator watches, in which the frequency of the oscillator can be as much as few MHz.

Attempts have been made to reduce energy consumption in frequency dividers by using C MOS intregated binary-circuits. Most quartz oscillator watches are currently equipped with such circuits. In this instance, consumption is essentially determined by the charging and discharging of capacitances presented by each stage of the shift register with the periodicity of its output signal. The consumption of each stage is consequently proportional to the value of its capacitances and to the frequency of its output signal. In a high frequency quartz oscillator watch, then, it is the first stages, that is to say, those that divide the highest frequencies, which are determinative of the consumption of the electronics. In order to lower the capacitances of these stages, various manufacturing techniques have been used, such as those known by the name of Sigate or SOS, (Silicon on sapphire).However, to keep consumption within acceptable limits, the dimensions of the integrated circuitsffiave to be reduced to such a point that, in the modern state of the art, the cost of their manufacture becomes prohibitive.

To lower consumption, high frequency dividers, a large part of whose capacitances form part of a resonant circuit, have also been proposed. A system of this type, for example, is described in Swiss patent No. 558 111. In this instance, the energy periodically stored in the capacitances is recovered. The system makes use of a shift register of a known type realised in integrated form and designated an IGFET (insulated gate FET) bucket brigate register. This register is ring connected and a single charge packet is transferred from one cell to the other. Each cell comprises firstly two IGFET's in series and two capacitors connected between the respective transistor control electrodes and drains. The control electrodes are connected alternately to two lines supplied by a push-pull quartz oscillator producing two alternating voltages in phase opposition.Means are additionally provided to bias the crystalline substrate in which the circuits are integrated. Devices, placed at various places on the register, form voltage pulses on passage of the charge. Another device is controlled by these latter pulses to supply a voltage whose frequency is a sub-multiple of the oscillator's and which is intended to control a relatively low frequency divider.

The assembly of the cells of the register described above presents a low capacitive load to the oscillator and the reactive current due to this capacitance causes a very small loss in the quartz. The principal real power which has to be supplied by the oscillator is that dissipated in the transistor through which the charge transfer from one stage to the other is effected. The mode of functioning of the register (a detailed description of which will be found in the article of C.N. Berglund et al, "Fabrication and Performance Considerations of Charge-Transfer Dynamic Shift Registers", Bell Sys. Techn. Journal, Vol. 51, No.

3, March 1972) is such that the current passes through the transistor for about 1/4 period and that the source-drain voltage of the latter during this time passes practically from the value Vp to 0, Vp being the peak-topeak value of the phase supply voltage supplied by the oscillator. Consequently, the power supplied by the oscillator, expressed by the general relation Pt = 2/tJO jD (t) VSD (t). dt, in which 1D (t) and VSD (t) are the instantaneous values respectively of the drain current and the source-drain voltage of the transistor, T being the oscillation period, then becomes PT = (Vp + vm)2. C.f.

In this expression, C is the capacitance connected to the transistor, fis the oscillator frequency, and vm represents the mean control voltage which exceeds the transistor threshold voltage. The voltage vm is normally a few tenths of a volt, while Vp is a few volts.

Taking a typical example with the values Vp = 2V, vm = 03V,C = Ol pF and f = 4 2 MHz, a value of 2 211 W is obtained for T Consequently, it is because of the high voltage necessary for the transfer of the charge packet from one cell of the register to the other that the power supplied by the oscillator is relatively high.

The principal object of the present invention is to provide a frequency divider with a very low consumption, allowing, for example, the realisation of a high frequency wrist watch with a life of several years.

According to the present invention, there is provided a frequency divider circuit for two periodic signals in phase opposition compris ing, integrated in a semi-conductor substrate, a first shift register comprising an assembly of transistors and capacitors which form a plurality of cells connected one after the other, each cell being constituted by two identical stages which are connected in series and are sup plied, in use, by the two periodic signals respectively, first detection means for detecting a particular state of the register, and first production means, responsive to the detecting of the said state to produce a first signal with a frequency which is a sub-multiple of that of said periodic signals, and wherein each stage of the shift register comprises an MOS transistor structure which has two principal electrodes respectively forming the input and output of the stage and two control electrodes, one of which is, in operation, connected to a bias source and the other of which is connected to the output principal electrode, and a capacitor, one plate of which is connected to the said output electrode and the other plate of which receives one of the said periodic signals.

The detection means can comprise a plurality of MOS transistors connected in series, these transistors being equal in number to that of the register cells and having their control electrodes respectively connected to the output electrodes of the cells (which are the output electrodes of the second stage of each cell). Because of this arrangement, the transistors in series are simultaneously on for the duration of one period of the periodic signals to be scaled, and this is reproduced with a periodicity equal to (n + 1) times the period of these signals, n being the number of register cells. It is in response to this turning on of the transistors in coincidence that an output signal is produced with a frequency which is a sub-multiple of that of the signals in phase opposition.

The production means which allow production of this output signal, comprises two MOS transistors mounted in series with the detection means transistors and with their control electrodes respectively connected to receive the periodic signals to be scaled, a third MOS transistor whose control electrode is connected to the connection of the detection means transistors with the two aforesaid transistors, a first additional capacitor in series with the third transistor and connected to receive one of the periodic signals, and a second additional capacitor connected to the connection of the two aforesaid transistors.Through this arrangement, the turning on of the transistors of the detection means in coincidence causes the appearance, on the connection between the third transistor and the first additional capacitor, of an output signal whose frequency is that of the periodic signals divided by (n + 1). This output signal is also transmitted to the control electrode of the first stage of the shift register to enable the introduction of a new charge packet in the latter.

According to another advantag#eous embodiment of the invention, two divider circuits similar to that described above can be coupled to form a circuit with a division factor equal 2(n + 1), n being the number of links in each shift register. In this instance, the output signals of the dividers alternately put into one or other of its stable stages a bistable circuit whose outputs apply respective control signals to the detection circuits of the two dividers.

As will appear later, the frequency divider according to the invention has a very low consumption which makes it particularly well adapted to dividing high frequency signals.

The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which: Figure 1 represents a first embodiment of a frequency divider according to the invention; Figure 2 is a diagram serving to explain the r functioning of the divider in Fig. 1; Figure 3 represents another embodiment of a divider with duplicate structure according to the invention; and Figure 4 is a diagram serving to explain the functioning of the divider in Fig. 3.

In Fig. 1, at 10, there has been represented diagrammatically the equivalent circuit of an integrated shift register with three cells of the type which is described in the patent application filed this day by the Applicant for "#nte- grated shift register" and to which reference will be made for a detailed description.

The first cell of the register 10 is constituted by the double transistor MOS structure T,-T'l and the capacitor C, for the first stage, and by the double transistor MOS structure T2-T'2 and the capacitor C2 for the second stage. In the same way, the capacitors C3 and C4 and the double structures T3-T'3 and T4-T'4 form the second cell of the register, while the capacitors C5 and C6 and the double structures T5-T'5 and T6 and T'6 constitute its third cell.In this series of cells connected one after the other, each cell is constituted by two identical stages, connected in series, each stage comprising MOS transistor structure which has two principal electrodes respectively forming the input (that of the transistor T2, for example) and the output (that of the transistor T'2, for example) of the stage, and two control electrodes, one of which (that of the transistor T2, for example) is connected to a bias source and the other of which (that of the transistor T'2, for example) is connected to the output principal electrode (that of the same transistor T'2). Each stage also comprises a capacitor, one plate of which is connected to this output principal electrode and the other of which is intended to receive one or other of the two supply signals coming respectively through the lines X (for example, for C1) and Y (for example, for C2). At the ends of the series of cells, the control electrode of the transistor T, of the first stage is intended to receive the pulse through which a charge packet is introduced into the register, and the charge comes from the latter via transistor T7 connected to the output of the last cell and with its control electrode con nected to its drain.

The system is controlled by a push-pull oscillator (not represented), such as that described, for example, in Swiss patent No. 580 837, which supplies on the lines X and Y two sinusoidal voltages in phase opposition, ~,(t) and Ç)2 (t) respectively. The divider represented in Fig. 1 is assigned the task of dividing the frequency of these periodic signals. Additionally, by means of a voltage multiplier (not represented), such as, for example, that described in Swiss patent No.

553 481, the oscillator biases the crystalline substrate of the assembly negatively in relation to a reference ground M. Similarly, a line P is negatively biased in relation to M. The source of the input transistor T, and the control electrodes of the transistors T2 to T7 of the register 10 are connected to this line which constitutes the bias source.

Analysis shows, when expressed in the same terms as those used previously for a shift register of the "IGFET bucket brigade" type, that the power to be supplied by the oscillator for the transfer of the charge packet is then: PT = 1 8 Vp . vm . C.f.

Assuming the same typical values as previously, a power of 0#45#W is obtained. This power was 2 2yW with the "IGFET bucket brigade" register. It is consequently clear that the register used in the invention allows the power which has to be supplied by the oscillator to be considerably reduced. Additionally, as is evident from the patent application mentioned above, the voltage established on each of the contacts a-b-c-d-e-f- when the charge contained in the register passes through the MOS structure to which the contact concerned belongs, and then through the subsequent structure (for example, the structures T1-T'1 and T2-T'2 for the contact a), is considerably smaller than the voltage established when no transfer occurs.It is precisely this feature of the register 10 which is advantageously used in the present invention for the realisation of a frequency divider circuit with very low consumption.

Reference will first by made to the diagrams in Figs. 2a, 2b and 2c, which represent the variation, as a function time, of the voltages Vb, vd and Vf established at the output of each cell at the points b, dand f respectively, when a charge packet shifts in the register. The figures show that, from the instant to the signals Vb, vd and v, have, in coincidence, one high value for the duration of one period T of the oscillator and that the coincidence is repeated with a period equal to 4T.Reference will again be made to Fig. 1 to describe the circuits 20 connected to the register 10, which have the task of detecting this coincidence of high values for the voltages at the outputs b, dand fof the cells and of producing, in response, an output signal with a frequency which is a sub-multiple of that of the signals in phase opposition applied by the oscillator to the lines X and Y.

In the circuits 20 in Fig. 1, the detection of the coincidence is effected by three MOS transistors T8, T9 and T10, while the production of the output signal is ensured by three MOS transistors T11, T12 and T13 and by two capacitors C7 and Cg. The five MOS transistors T8 to T12 are mounted in series at the terminals of a supply voltage source (battery) V. The control electrodes of the transistors T8, T9 and T10 are respectively connected to the register outputs b, d and f, while the control electrodes of the transistors T11 and T12 are respectively connected to the lines Y and X.The point i common to the transistors T10 and T11 is connected to the control electrode of the transistor T,3, connected between the reference gound M and a point g, while the capacitor C9 is connected between M and the point kcommon to the transistors T11 and T,2.

The point g is connected, on the one hand to the line X by the capacitor C7 and, on the other hand, to the control electrode of the transistor T,, by a capacitor C8. A last MOS transistor T14 with its control electrode connected to the line P, is connected between the latter and a point h located between the capacitor C9 and the transistor T1. Finally, a decoupling capacitor C10 connects the line P to the reference ground M.

The functioning of the frequency divider represented in Fig. 1 can be described in the following way. Firstly, it must be indicated that the transistors T11 and T12 being controlled by the two voltages in phase opposition O1(t) and O2(t) respectively, one or other of these transistors is blocked at each instant.

Consequently, when the input capacitance of the transistor T13 is, as will appear later, discharged by the transistors T8, T9 and T10 which are, because of the indirect connection between their control electrodes and the line Y, controlled by a voltage derived from the phase voltage O2(t), the recharging of this capacitance is afterwards delayed by one period of the phase voltage ~1(t). Since at this moment the voltage vat the point i is (Fig.

2d) at such a level that the transistor T13 is blocked, a voltage pulse v9 appears at the point g (Fig. 2e).

To return now to the three transistors T8, T9 and T10 in series, a comparison of Figs. 2a, 2b and 2c shows that these transistors are turned on in coincidence by the signals Vb, vd and Vf for the duration of a period T of the oscillator and that this is reproduced with a period of 4 T. The current which passes through the three transistors in coincidence causes the discharging of the input capacitance of the transistor T13, as well as that of the capacitor Cg. As previously indicated, the appearance of a pulse v9 at the point g (Fig.

2e) results from this.

It will be noted in passing that the particu lar structure of the register 10 allows what constitutes an important property of this type of register, namely, the disposing of relatively high signals and of a duration of one period at the time of coincidence. This is what allows the discharging of a relatively large capacitance by a current which has to pass through several transistors in series.

The pulse v9 appearing at the point g is transmitted by the capacitor C8 to the control electrode of the first MOS structure of the shift register, the transistor T14 having the task of defining the potential of this control electrode. Consequently it is through this that a new charge packet is introduced into the register to leave again through the transistor T7 between the instants t1 and t2 (Fig. 2f).

It should be noted that the register 10 has to be biased negatively in relation to the reference ground M so that the transistors T8, T9 and T10 stay entirely blocked during the time when there is no coincidence of the signals Vb, vd and v, at their high value. The value of this bias, applied on the line P, and derived according to the teaching of Swiss patent No. 553 481 already cited, must be greater than half of the control voltage of a double transistor MOS structure, necessary for the transfer of a charge packet. For example, this bias is of the order of 2 to 3 tenths of a volt.

Thus it is clear, by reference to Figs. 2d, 2e and 2f, that the divider according to the invention allows the signals vj, v9 and vk, obtained on the points i, gand krespectively to have a periodicity of 4T. There is thus realised, with a register with three cells, a division of the oscillator frequency by four. It is easy to see, more generally, that with a shift register with n cells, a divider with a division factor of n + 1 is obtained.

The signal obtained at the point g and available on an output terminal S is very suited to, for example, the control of a binary divider, like that described in Swiss patent No. 592 331, which contains transistors of the same type and capacitors. The divider according to the invention can thus form, 'with a chain of binary dividers according to the patent above, an integrated assembly on one single substrate. Thanks to the use of the divider according to the invention, the consumption of the assembly is very greatly reduced for the highest frequencies.

The particular type of shift register used in the present invention allows the realisation of a large variety of frequency dividers. Reference will now be made to Fig. 3 in which another advantageous embodiment of a fre quency divider according to the invention has been represented, this time using two shift registers of the above type. Such a-divider is particularly suitable for controlling a C-MOS divider of lower frequency and conventional type. In this instance, the push-pull oscillator supplying the two voltages in phase opposition and the frequency divider form a unit which can, for example, be integrated in a p region independent of the p regions used for the N-MOS transistors of the divider with complementary transistors.

It should also be noted that, to obtain a good functioning of the circuit 20 in Fig. 1, the number of transistors in series having their control electrodes respectively connected to the outputs of the shift register links need < be no more than 5 or 6. This means that the register need have only 5 or 6 cells, which allows a maximum division factor of 6 or 7.

The double divider represented in Fig. 3 represents a useful solution for easily obtaining a division factor equal to 12 or 14.

In the double divider represented in Fig. 3, a bistable circuit 30 is set alternately in one or other of its stable states by two dividers similar to that in Fig. 1, the first being formed by the shift register 32 and the circuits 34 and the other by the register 32' and the circuits 34'.

The bistable 30, of known type, is controlled by the voltage (11(t) and connected to a supply source (not represented) which supplies the voltage V, the line M constituting the system's reference ground. The two stages of the bistable 30 are formed one by the MOS transistors T15, T16 and T17 and the capacitors C15 and C16, and the other by the transistors T'a5, T'16, and T'17 and the capacitors Ci15 and , .

C 16 The shift registers 32 and 32' and the associated circuits 34 and 34' compriseele ments which are also present in the register 10 and its circuit 20 in Fig. 1. Consequently, in Fig. 3, these elements have been designated by the same references as in Fig. 1 as far as the divider 32-34 is concerned, the references of the divider elements 32'-34' bearing the signs. It will be noted that, for simplicity, the registers 32 and 32' comprise only two cells whose outputs are connected to the transistors T8 and T9 of the circuit 34 and to the transistors TX8 and TX9 of the circuit 34' respectively. It is, however, evident that the number of cells can be considerably larger.

The divider in Fig. 3 differs from that in Fig. 1 in that the circuits 34 and 34' comprise, mounted in series with the transistors T8-T8 and Tx8-Tx9 respectively, two additional MOS transistors T19 and TX19 respectively, with their control electrodes respectively connected to the points m and m' of the bistable 30, which constitute the two outputs of the latter.

Another, but not essential difference, as will appear later, consists in the presence of two transistors T15 and TX15 connected respectively between the points kand m' and the points k" and m. The two transistors also have their control electrodes connected to the points m' and m respectively In addition, the point g of the circuit 34 is connected to the capacitor CX8 of the circuit 32' (and no longer to the capacitor C6 of its circuit 32) and to the control electrode of the transistor T17 of the bistable 30.Similarly, the point gt of the circuit 34' is connected to the capacitor C6 of the circuit 32 and to the control electrode of the transistor T117 of the bistable. The control electrodes of the transistors T17 and T'17 will be considered to be the control inputs of the bistable 30.

The functioning of the frequency divider in Fig. 3 will now be described with reference also to the explanatory diagrams in Fig. 4. It will initially be assumed that the input capacitance of the transistor T16 is charged. There is consequently practically no alternating voltage relative to M at the point h of the bistable 30.

As the transistor T'15 is blocked, an alternating voltage superposed on a direct voltage with the value of its amplitude is disposed at the point hi. In this instance, the transistor T19 is turned on by the control signal it receives from the output m of the bistable, while the transistor T16 is blocked. Consequently, the capacitance of the transistor T13 is discharged and a voltage pulse v6 appears on the drain of this transistor, according to the technique already described, when the signals vb and vd coming from the register have, in coincidence, a a high value.This pulse is transmitted by the capacitance Ct6 to the control electrode of the first MOS structure of the register 32'. Consequently, a new charge packet is introduced into this register. As the transistor T17 is also controlled by this pulse, the input capacitance of the transistor T15 of the bistable 30 is discharged by the current passing through T17 The bistable then switches into its other state, for which there is a voltage relative to M M at the point m', but no voltage at the point m. Because no charge packet is introduced into the shift register 32 at that instant, the output signals of the latter stay in coincidence. This is allowable because the transistor T19 is now blocked.The transistor TX19 is now turned on by the control signal it receives from the output m' of the bistable. Because of the charge packet then passing through the register 32', the transistors TX6 and TX6 are blocked one after the other. The coincidence of the turning on of these two transistors occurs only on expulsion of this charge packet, afterwards causing the appearance of a voltage pulse Vxg at the drain of the transistor To13. This output pulse of the circuit 34' makes the bistable switch back into its first stable stage for which there is a voltage present at the point m, while a charge packet is introduced into the shift register 32, and so forth.

As previously indicated, the transistors T16 and TX16 are not essential for ensuring the functioning of the frequency divider according to the invention. These transistors allow the value of the capacitance of the storage capacitor C9 (see Fig. 1) to be reduced. In fact, as is evident in the diagrams in Fig. 4, the initial recharging of the input capacitance of the transistor T13 or TX13 is in this case made not by a partial discharging of the storage capacitor but by a current which passes through the transistor T16 or TX16 at this moment. Thus, it is, in practice, only the input capacitance of the transistor T13 or TX13 which has to be recharged with the periodicity of the divided signal of the oscillator.By using the transistors T16 and TX16 with a very low capacitance, only the transistors T"-T,2 and Tx1,-Tx,2 serve to ensure the starting of the divider when it is latched.

Fig. 4 shows very clearly that the output signals obtained at the points g and gx respectively available at the output terminals S and sx have a period of 6T, which consequently corresponds to a division factor equal to 6. To generalize, the division factor obtained by the double divider is equal to 2 (n + 1), n being the number of cells in each shift register. If, for example, one cell were added to each of these registers, whose output would control an additional transistor in series with the transistors T6-T6 and TX8-Tx9 respectively, the division factor would become equal to 8.

It should be mentioned that the four confi gurations formed respectively by the transistor T13 with the capacitor C7, the transistor TX13 with the capacitor CX7, the transistor T,5 with the capacitor C,5 and the transistor T',5 with the capacitor C',5 can be regarded as dynamic inverters. For a detailed description of the functioning of these dynamic inverters, reference can be made to the article of J. Luscher et al, "1 966 International Solid State Circuits Conference, Digest of Technical Papers", pp.

116- 117.

As in the integrated system described in Swiss patent No. 558 111 already cited, the frequency divider which has just been described can advantageously form a unit with the push-pull oscillator supplying the phase voltages ~,(t) ~2(t).

The load presented to the oscillator by the frequency divider has a real component and a reactive component, the latter being provided by the capacitance CD which the divider presents to the oscillator. The reactive current which passes through this capacitance causes a certain dissipation of power PQ in the quartz crystal of the oscillator. This power is about P0 2(.Vp .qT.f)2 CO . CD . Rt with CO = capacitance parallel to the quartz due to its static capacitance and to that of the properly so-called oscillator circuit, R5 = series resistance of the quartz.

The power which has to be supplied by the oscillator owing to the real component of its load is, firstly, the power PT necessary to ensure the transfer of the charge packet into the shift registers and, additionally, the power P1 dissipated in the four dynamic inverters T13-C7, Tx,3-Cx7, T,5-C15 and T'15-C',5 when the transistor of these is turned on. The equation allowing the determination of PT has been given already. As for the power Pl, this can be determined in the following way.

The resistance presented by a transistor which is on is far lower than the reactance presented by the capacitor C in series with this. The alternating current which passes through it is consequently practically sinusoidal, its amplitude being i = Vp 7r f C.

For the resistance Ro of a transistor which is on, whose threshold voltage is practically 0, the calculation: Ro = 1 /2K Ve can be carried out with K = slope of the transistor in A/V2, Ve = input direct voltage.

It follows that the power dissipated in the transistor of an invertor when it is on can be expressed by the equation: (P = Vp7Tf C)2/4k Ve Supposing the aforesaid four dynamic inverters to be of the same dimensions and to have the same control voltage (in their on state), and taking into account that each inverter transistor of the bistable circuit (T16 and T'16) is on for a half-period per period of the output signal of the divider, the total power Pl dissipated in these transistors becomes about:: Px = (VptlTf C)2/k Ve With an efficiency r of the circuit maintaining the oscillator (see Swiss patent No. 580 837 already cited) and a battery voltage V, the consumption jA, due to losses caused by the alteinating currents at the frequency of the oscillator supplying the divider, can be expressed as follows:: i, = PQ + PT + P1/m To this consumption is added the consumption i, which is directly supplied by the battery, that is to say, the current necessary for the recharging of the capacitances associated with the points i, it, m and m'with the periodicity of the output signal of the divider, as mentioned above. In the present instance, these capacitances are in practice charged to the same voltage Ve which is, typically, of the order of 1V. This consumption then becomes: ; Ce Ve( f/2(n + 1)) in which Ce represents the whole of the capacitances associated with the points i, 2 and m, ml.

To divide a frequency of 4'2 MHz, for example, while assuming an oscillator whose output voltage peak-to-peak per phase is 2V, adequate values for a divider of this type are: C18 = C'15 = C7 = C7 = 0 1 pF.

A same value can be provided for all the shift register capacitors. The slope kof the transistors T15, T116,T116, T13, T*13, can then be of the order of 2 10-5 A/V2. Such a value for k is obtained, for example, for an n type transistor, whose effective channel length is 8ym and its width about 10 m.

A value of about 50# can be assumed as series resistance for a quartz crystal of this frequency. An oscillator of the type mentioned, whose capacitance CO does not exceed 3pF is entirely feasible. With the values of the capacitors mentioned for the divider, the capacitance presented by their per phase becomes about 0 8 pF, that is to say that the capacitance CD parallel to the quartz crystal due to the divider is 0 4 pF. Consequently, an approximate value of 0 08yW is obtained for PQ. With an input voltage V of the dynamic inverter transistors equal to 1V, an approximate value of 0 26yW is obtained for P,.

About 0 6yW must be taken into account for the power PT due to the charge packet transfer. Finally, the current for maintaining the oscillator can easily be dimensioned so that its efficiency may be 08. Consequently, value of about 0-81l A can be obtained for #A, with a battery voltage of 1.5 V. In the conditioris mentioned, the capacitance Ce becomes about O#4pF, that is to say, the current ID becomes equal to 0-2y A for a division factor of 8; for example.In the present example, the consumption of the oscillator alone being 0; A, that of the oscillator divider unit is about 1 4~s A.

This low consumption is achieved with an integrated circuit of relative large dimensions, which facilitates its manufacture. It is h6wever, evident that with more advanced miniaturization, the consumption of this divider can become extremely low.

The signal obtained at the points h, hi or m, m', are very well suited to the control of a C-MOS divider. If control is required of a a circuit with relatively high input capacitance, an inverter (not represented) similar to those defined above can also be connected at each of the points a, c, ax and Cx. These additional inverters must then be supplie#d by the phase voltage ~2(t). Thus, when the charge packet is, for example, introduced into the capacitance associated with the point a, then trans- ferred to the capacitance associated with the point b, a signal appears at the inverter output in question, and this signal is similar to those obtained at the points g and gx. Since a single charge packet passes through the shift register during the duration of a period of the divider output signal, a signal shifted in the time in relation to the others is obtained at each output of the four inverters. The signals are, then, very suitable for controlling a decoupling circuit of the type described, for example, in Swiss patent No. 572 666.

Naturally, the circuits which have been de scribed above are capable of many variants which remain within the scope of the invention.

Claims

1. A frequency divider circuit for two periodic signals in phase opposition comprising, integrated in a semi-conductor substrate, a first shift register comprising an assembly of transistors and capacitors which form a plurality of cells connected one after the other, each cell being constituted by two identical stages which are connected in series and are supplied, in use, by the two periodic signals respectively, first detection means for detecting a particular state of the register, and first production means, responsive to the detecting of the said state to produce a first signal with a frequency which is a sub-multiple of that of the said periodic signals, and wherein each stage of the shift register comprises an MOS transistor structure which has two principal electrodes respectively forming the input and output of the stage and two control electrodes, one of which is, in operation, connected to a bias source and the other of which is connected to the output principal electrode, and a capacitor, one plate of which is connected to the said output electrode and the other plate of which receives one of the said periodic signals.

2, A divider circuit according to claim 1, wherein the detection means detect the presence in coincidence of signals of given amplitude at a pre-determined point in each of the celts of the said register.

3. A divider circuit according to claim 2, wherein the detection means comprise a plurality of MOS transistors connected in series, there transistors being equal in number to that of the shift register cells and having their control electrodes respectively connected to the output electrodes of the cells.

4. A divider circuit according to claim 3, wherein the said means for producing a signal with a frequency which is a sub-multiple of that of the said periodic signals comprise a pair of MOS transistors mounted in series with the transistors of the detection means and having their control electrodes respectively connected to receive the said periodic signals, a third MOS transistor whose control electrode is connected to the connection of the transistors of the detection means with the said pair of transistors, a first additional capacitor in series with the third transistor and connected to receive one of the said periodic signals, and a second additional capacitor connected to the connection of the two transistors of the said pair.

5. A divider circuit according to claim 4, wherein the connection of the first additional capacitor with the third transistor is coupled to the first control electrode of the first cell of the shift register.

6. A divider circuit according to claim 1, further comprising a second shift register substantially identical to the said first register, second detection means for detecting a particular stage of the second shift register, second production means, responding to the detecting of the said state, for producing a second signal with a frequency which is a sub-multiple of that of the said periodic signals, and a bistable circuit having a first and second control input and a first and second output, the said first and second control inputs being connected to receive the said first and second signals respectively and the said first and second outputs being connected to supply control signals to the first and second detection means respectively.

7. A divider circuit according to claim 6, wherein the first and second detection means are substantially identical and each comprises a plurality of MOS transistors connected in series, these transistors being equal in number to that of the cells of the corresponding shift register and having their control electrodes respectively connected to the output electrodes of the cells of this register, and an MOS transistor connected in series with the said plurality of transistors and whose control electrode is connected to receive one of the control signals produced by the bistable circuit.

8. A divider circuit according to claim 7, wherein the first and second production means are substantially identical and'each comprises a pair of MOS transistors mounted in series with the transistors of the corresponding detection means and having their control electrodes respectively connected to receive the said periodic signals, a third MOS transitor whose control electrode is connected to the connection of the transistors of the detection means with the said pair of transistors, and a capacitor in series with the said third transistor and connected to receive one of the said periodic signals, the output of the said production means being formed by the connection of this capacitor to the third transistor.

9. A divider circuit according to claim 8, wherein the first production means further comprise an MOS transistor connected between the second output of the bistable circuit and the connection of the two transistors of -the pair of the said first production means; and the second production means further comprise an MOS transistor connected between the first output of the bistable circuit and the connection of the two transistors of the pair of the said second production means.

10. A divider circuit according to claim 8, wherein the output of the first production means is coupled to the first control electrodeof the first cell of the second shift register, and the output of the second production means is coupled to the first control electrode of the first cell of the first shift register.