JPH03228296A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To omit a refresh operation without increasing the scale of a semiconductor integrated circuit IC by providing a switch means provided between an input terminal and an input terminal of a logic gate and a MOS transistor TR where a gate whose source and drain are connected between a power supply and the input terminal of the logic gate is connected to the output terminal of the logic gate. CONSTITUTION:In a master-slave type flip-flop, a switch means using the MOS TR 20 and 21 is cascaded to an information holding circuit consisting of the logic gates 10 and 11. This flip-flop is provided with the MOS TR 30 and 31 having their sources connected to a power potential VDD, gates connected to the outputs of logic gates 10 and 11, and drains connected to the inputs of logic gates 10 and 11 respectively. In such a constitution, it is not required to recharge the electric charge of a stray capacity in each fixed period unlike a dynamic flip-flop nor to use many elements unlike a static flip-flop. Thus no refresh operation is needed without increasing the circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device including a master-slave type flip-flop circuit.

[Conventional technology]

Conventionally, master-slave type flip-flops using this type of MOS transistor can be roughly divided into two circuit systems. One is a dynamic type shown in FIG. 10, and the other is a static type shown in FIG. 11.

As shown in FIG. 10, the dynamic flip-flop is an N-channel MO3 transistor (hereinafter referred to as NMO3).
A circuit that holds H (high level) or L (low level) information using the 201 inverter 10 and stray capacitance C1 such as wiring capacitance and input capacitance is on the master side,
A circuit that holds L or H information using the NMO 321, the inverting amplifier 11, and the stray capacitance C2 is on the slave side. Here, the information H and L are expressed by the level of potential.

φl and φ2 are clock inputs of opposite phases; when φ1 is at a high potential, φ2 is at a low potential, and when φ1 is at a low potential, φ2 is at a high potential.

Next, the operation of the dynamic flip-flop will be explained. Now, node D is at a low potential, D2 is at a high potential, and the input Din
Consider the case where a high potential is applied to First, when φl becomes a high potential, NMO320 becomes conductive and starts charging the stray capacitance C1, which causes Note D.

The potential of goes from ground potential to high potential. Then, by the inverting amplifier 10, the node DM, which has been at a high potential until now, moves to a low potential. In this series of operations, NMO321 is cut off because φ2 is at a low potential, and node D2
There is no impact on

Eventually, almost at the same time as φ1 becomes a low potential, φ2 becomes a high potential, NMO 321 becomes conductive, and the charge stored in stray capacitance C2 is discharged through NMO 321. Then, the output Dout finally becomes a low potential due to the inverting amplifier 11. The same consideration as above can be given when a high potential is applied to the input Din.

What should be noted here is that the dynamic type has stray capacitance C
1 and C2 hold H or L information.

Therefore, φ1. φ
2 is applied every certain period of time to rewrite the data, so-called refresh is required.

Unlike the dynamic type that requires refreshing, the static type shown in Figure 11 adds an NMO 328゜29 and an inverting amplifier 15,16, and also has a feedback loop that retains information by inputting clocks φl and φ2 as shown in the figure. φ1. The feature is that information does not disappear even if φ2 is not applied.

[Problem to be solved by the invention]

The above-mentioned conventional master-slave type flip-flop circuit has the drawback that in the dynamic type, information is retained by the charge stored in the stray capacitance, so the information will be lost if it is not periodically recharged (refreshed). . Further, in the static type, although information does not disappear, it has the disadvantage that the circuit becomes complicated and large in size due to the formation of a feedback loop.

An object of the present invention is to provide a semiconductor integrated circuit device that does not require refreshing without increasing the circuit scale.

[Means to solve the problem]

The semiconductor integrated circuit device of the present invention includes a logic gate, a switch means provided between an input terminal and an input terminal of the logic gate, and a source/drain path connected between a power supply and an input terminal of the logic gate. MOS)-transistor connected to the output terminal of the logic gate.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a logic circuit diagram of a master-slave type flip-flop according to an embodiment of the present invention. 20°21 is NMO3
, 10, 11 are inverting amplifiers, 30.31 is a P-channel MOS transistor whose one end is connected to the power supply potential VDD, C1, C2 are floating capacitances, φ1. φ2 are clock inputs having mutually opposite phases. Figure 2 shows the complementary MO of an inverting amplifier.
This is a concrete circuit using three transistors. 32 is a P-channel type MO3) transistor (hereinafter referred to as PMO3)
, 22 are NMO3, and when one is conducting, the other is cut off, and has been widely used in recent years as a circuit that does not consume DC power. Figure 3 shows Del-John type NMO3
40 and NMO323. This circuit consumes DC power from the power supply to ground when 23 NMO3 is conductive, so it is not often used in places where it is necessary to suppress power consumption.

The operation of this embodiment will be explained with reference to FIG. First, consider the case where the input Din goes from a low potential to a high potential. After the input Din becomes a high potential, the clock φ2 first becomes a low potential and the NMO 321 is cut off. This means separation of the master side and slave side. After that, when the clock φ1 becomes high potential, the input Din is connected to the NMOS
20, the stray capacitance C1 is charged. Then, when the node D1 exceeds the inversion potential of the inverting amplifier 10, the potential of the node DM decreases, and eventually P
MOS30 becomes conductive. Next, when the potential of the clock φl decreases and the potential of φ2 increases, the charges stored in the floating capacitance C2 are discharged through the NMO 321, and when the potential of the node D2 eventually reaches the inverted potential of the inverting amplifier 11, as shown in FIG. As shown in (■) in the middle, the potential of the output Dout rises and at the same time the PMO 331 is cut off.

When the input Din is at a low potential, when the clock φ1 becomes a high potential, the node DM rises as shown by ■ in the figure, and the PMO
330 is cut off. When the clock φ1 decreases and φ2 increases, the output Dout decreases, as shown by ■ in the figure.
PMO 531 becomes conductive. Here, PMOS30.31 is cut off by the switch NMO320 or 21,
And when the stray capacitance is charged and has a high potential, the power supply V
There is no natural discharge of charges connected to the DD, and there is no need for refreshing as in the case of the conventional dynamic flip-flop 71. FIG. 4 shows that in the conventional example, when the clock cycle Tcyc is relatively large, it is several tens of m5ec~
The broken line shows how the potential fluctuates due to spontaneous discharge over several hundred m5ec.

FIG. 5 is a logic circuit diagram for explaining a second embodiment of the present invention. The difference between this embodiment and the first embodiment is that complementary type MOS transistors are used as the switch MOS transistors. 33.34, PMO3, 12, 13 are clock φ1. This is an inverting amplifier for creating the opposite phase of φ2.

In this embodiment, since complementary MOS transistors are used for the switches, when NMO3 is selected, the potentials of nodes Dl and D2 fall below the potential of input Din or node DM by the threshold potential of the MOS transistor ■7, a so-called -step drop. It has the advantage of not occurring. This situation is shown in FIG.

FIG. 7 is a logic circuit diagram for explaining a third embodiment of the present invention. This embodiment has a reset circuit that can set the flip-flop circuit to an initial state. As shown in the figure, 50 is a two-man NAND circuit, 60
14 is a two-man powered NOR circuit, and 14 is an inverting amplifier for inputting the inverted potential of the reset signal R3T to the two-man powered NOR circuit. FIGS. 8 and 9 show specific circuits using complementary MO3 transistors for a two-man powered NAND circuit and a two-man powered NOR circuit, respectively. 35,36°37.38 is PM
O3, 24, 25, 26, 27 are NMO3.

First, consider the case where a low potential is input to the reset signal R3T. The two-man power NAND circuit 50 brings the node DM to a high potential regardless of the potential of the node D1. Similarly, since the opposite potential of the reset signal R3T is input to the two-man power NOR circuit 60, the output D
out becomes a low potential.

As described above, this embodiment has the advantage that the potentials on the master side and the slave side can be forcibly set to the initial state regardless of the input or node potentials.

〔Effect of the invention〕

As explained above, the present invention provides a master-slave type flip-flop in which information holding circuits configured by switches and logic gates using MOS transistors are connected in cascade, and the gate is connected to the source or power supply potential to output the output of the logic gate. MO whose train is connected to the input of the logic gate
By providing an S transistor, there is no need to recharge (refresh) the stray capacitance at regular intervals like in a dynamic flip-flop, and it also does not require as many elements as in a static flip-flop. This has the advantage that large-scale semiconductor integrated circuits using several tens to 10,000 flip-flops can be constructed in an extremely small area.

[Brief explanation of drawings]

Fig. 1 is a logic circuit diagram for explaining the first embodiment of the present invention, Fig. 2 is a circuit diagram in which the inverting amplifier of Fig. 1 is implemented using complementary MOS transistors, and Fig. 3 is a circuit diagram of the inverting amplifier shown in NM
4 is a potential waveform diagram for explaining the operation of FIG. 1, FIG. 5 is a logic circuit diagram showing the second embodiment of the present invention, and FIG. 6 is a circuit diagram realized using O3 only. 7 is a logic circuit diagram showing the third embodiment of the present invention, and FIGS. 8 and 9 are two-manual NA of FIG. 7.
A circuit diagram in which an ND circuit and a two-way NOR circuit are realized using complementary MOAS transistors. Figure 10 is a logic circuit diagram for explaining a conventional example. Figure 11 is a logic circuit diagram of a conventional static master-slave flip-flop. It is. 10.11, 12, 13, 14, 15. 16... Inverting amplifier, 20, 21, 22, 23, 24° 25. 26.
27...N-channel type MOS transistor, 30,3
1, 32, 33, 34, 3536.37.38...P
Channel type MO8 transistor, 40...Depletion type N-channel type MOS transistor, 50...2
Human powered NAND circuit, 60...2 human powered NOR circuit.

Claims (1)

[Claims] 1. A logic gate, a switch means provided between an input terminal and an input terminal of the logic gate, a source/drain path connected between a power supply and an input terminal of the logic gate, and a switch means provided between an input terminal and an input terminal of the logic gate; 1. A semiconductor integrated circuit device comprising: a MOS transistor connected to an output end of a logic gate. 2. The semiconductor integrated circuit device according to claim 1, further comprising means for setting the logic gate to an initial state using a control signal.