GB1602216A - Thyristor having emitter shunts uniformly spaced from edge of the emitter - Google Patents
Thyristor having emitter shunts uniformly spaced from edge of the emitter Download PDFInfo
- Publication number
- GB1602216A GB1602216A GB974778A GB974778A GB1602216A GB 1602216 A GB1602216 A GB 1602216A GB 974778 A GB974778 A GB 974778A GB 974778 A GB974778 A GB 974778A GB 1602216 A GB1602216 A GB 1602216A
- Authority
- GB
- United Kingdom
- Prior art keywords
- region
- emitter
- shunts
- thyristor
- inner edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 2
- 238000007600 charging Methods 0.000 description 7
- 238000009826 distribution Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000009827 uniform distribution Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000009828 non-uniform distribution Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0839—Cathode regions of thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
- Bipolar Transistors (AREA)
Description
(54) THYRISTOR HAVING EMITTER SHUNTS UNIFORMLY
SPACED FROM EDGE OF THE EMITTER
(71) We, WESTINGHOUSE ELECTRIC
CORPORATION of Westinghouse Building,
Gateway Center, Pittsburgh, Pennsylvania,
United States of America, a company organised and existing under the laws of the
Commonwealth of Pennsylvania, United
States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The invention relates to semiconductor devices and more particularly to thyristors.
It is well known in the art that emitter shunts can be used to improve power thyristors dV/dt and emitter turn-on characteristics. In the prior art, the so-called distributed shunts were typically arranged either in square or hexagonal arrays and distributed over the emitter region. The inner edge of prior art emitter regions were usually round. These geometries created a discontinuity in the distribution of the shunts around the perimeter of the gate and the inner edge of the emitter region. The emitter turns on first in the regions where the emitter shunts are closest to the inner edge of the emitter. This is a direct result of the non-uniform shunting resistance between the inner edge of the emitter and the shunts nearest this edge. Additionally, the charging current associated with the rate of use of the anode voltage must flow to the cathode through the emitter shunts. Areas having a low and non-uniform distribution density of emitter shunts, due to the discontinuities discussed above, tend to turnon first due to lower charging currents. The areas of low charging current establish the permissible rate of rise of the anode voltage. The net result of these discontinuities is a non-uniform emitter turn-on characteristic and a lowering of the dV/dt capability of the thyristor.
It is the principal object of the invention to provide uniform emitter turn-on characteristics.
The invention resides broadly in a thyristor having a first emitter region on one surface, the first region having an inner boundary having portions which lie on the perimeter of a regular polygon area, said inner boundary being formed by plurality of lines which are exclusively straight;
a second region comprising a gate disposed adjacent the first region and forming a PN junction with a first region, said second region disposed on said first region opposite said one surface and extending to said one surface within the area defined by the polygon;
emitter shunts disposed in said first region, at least a portion of the emitter shunts being disposed in a first series of emitter shunts which form rows, which rows are exclusively straight, said portion of the exclusively straight rows of said first series of rows of emitter shunts being spaced from and parallel to the exclusively straight lines forming said inner boundary, said first row of emitter shunts being spaced apart and having a spacing from one another;
a second series of emitter shunts being spaced apart from one another, the spacing of the second series, from any one shunt to the other thereof, being greater than the spacing of the first series from any one shunt to the other thereof;
a third region disposed on the side of said second region opposite said first region;
said third region forming a PN junction with said second region; and
a fourth region disposed on the side of said third region opposite said second region;
said fourth region forming a PN junction with said third region.
The preferred embodiment of the thyristor which is the subject of this invention utilizes an emitter region having an inner edge in the form of a polygon. Along the substantially straight edges of the polygon and spaced uniformly from the inner edge of the emitter region is a row of emitter shunts. The remainder of the emitter area also includes emitter shunts distributed in a uniform pattern. This new geometry assures that the distribution of the emitter shunts along the inner edge of the emitter and the outer perimeter of the gate contact is uniform. This assures that the turn-on characteristics of the thyristor are substantially uniform across the entire emitter area and that the charging current, associated with a rise in the anode voltage is uniformly distributed over the emitter region. This substantially improves the turn-on characteristics of the emitter and dV/dt capability of the thyristor.
A preferred embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
Figure 1 is a top view of a typical prior art thyristor;
Fig. 2 is a cross section of a first embodiment of the improved thyristor;
Fig. 3 is a top view of the thyristor illustrating the cross section of Fig. 2;
Fig. 4 is a cross section of a second embodiment of the improved thyristor;
Fig. 5 is a top view of the thyristor illustrating the cross section of Figure 4;
Fig. 6 is a cross section of a third embodiment of the improved thyristor;
Fig. 7 is a top view of the thyristor illustrating the cross section in Fig. 6;
Fig. 8 is a cross section view of a third embodiment of the improved thyristor;
Fig. 9 is a top view of the thyristor illustrated in cross section in Fig. 8;
Fig. 10 is a cross section of a fourth embodiment of the improved thyristor; and
Fig. 11 is a top view of the thyristor illustrated in cross section in Fig. 10.
Figure 1 is a top view of a typical prior art thyristor utilizing emitter shunts. These prior art devices typically utilized a circular gate contact 30. The inner edge 31 of the emitter region was also circular with the emitter shunts arranged in a square pattern and distributed over the entire emitter region. Two typical emitter shunts are identified by reference number 32 in
Fig. 1.
It can be seen from the top view of this prior art thyristor that the emitter shunts closest to the inner edge of the emitter region are not uniformly distributed with respect to the inner edge of the emitter. It is well known that this causes the turn-on characteristics of the emitter region to be non-uniform and lowers the dV/dt capability of the thyristor.
The improved thyristor which is the subject of this application utilizes a circular semiconductor structure. One embodiment of the thyristor is illustrated in cross-section in Fig. 2 and in half top view in Fig. 3.
The thyristor includes an anode region 40. In the preferred embodiment the anode region 40 is a thin layer of P-conductivity type silicon. Electrical contact is made to the anode region 40 through a metallic contact layer 48. Immediately overlying the anode region 40 and forming a PN junction therewith is a N-conductivity type silicon region 41. Overlying the N-conductivity type region 41 and forming a PN junction therewith is a P-conductivity type gate region 42. An N-conductivity type emitter region 43 forms a PN junction with the gate region 42. Portions of the P-conductivity type gate region and the N-conductivity type emitter region extend to the upper surface 51 of the semiconductor structure 50 with the inner edge of the emitter region 43 being in the form of a polygon. The central portion of the P-conductivity type gate region 42 makes electrical contact with the metallic gate terminal 44. Circular shunt regions 46 of P-type material also extend from the upper surface 51 of the semiconductor structure 50 to the gate region 42. These regions make contact with an emitter terminal 45.
A row of emitter shunts is distributed around the inner edge of the emitter region 43 in a pattern such that each of the shunts comprising the row is the same distance from the inner edge of the emitter. Two typical shunts of this row are identified in
Fig. 3 by reference numeral 47. The remainder of the emitter shunts are arranged in a square pattern and uniformly distributed over the remainder of the emitter region 43. This distribution of emitter shunts assures a more uniform turn-on of the emitter region 43 because the uniform pattern of emitter shunts along the inner edge of the emitter region 43 results in a substantially uniform distribution of the gate to emitter current along the inner edge of the emitter region 43. The charging current resulting from a rise in the anode voltage is also more uniformly distributed over the emitter region 43 resulting in an increase in the rate of rise (dV/dt) required to turn-on the thyristor. These improvements in emitter turn-on and dV/dt characteristics are attributable to the more uniform shunting resistance between the inner edge of the emitter region 43 and the shunts nearest this edge of the emitter region 43.
Since the semiconductor structure is symmetrical only one half of the top view is shown in Fig. 3.
Another embodiment of the thyristor which is the subject of this invention is illustrated in cross-section in Fig. 4 and in one half top view in Fig. 5. This embodiment utilizes a circular semiconductor structure 54 including a P-conductivity type anode region 55. Electrical contact to the anode region 55 is provided by a metallic layer 61. Immediately overlying the anode region 55 and forming a PN junction therewith is an N-conductivity type region 56. The Nconductivity type region 56 forms a PN junction with P-conductivity type gate region 57. An N-conductivity type emitter region 58 extends from the gate region 57 to the upper surface 63 of the semiconductor structure 54 and forms a PN junction with the gate region 57. Portions of the gate region also extends to the upper surface 63 of the semiconductor structure 54. Overlying the central portion of the semiconductor structure 54 and making electrical contact with the P-conductivity type gate region 57 is
a metallic gate contact 60. Overlying the Nconductivity type emitter region 58 is an emitter contact 59. The emitter contact 59 makes electrical contact with the P-conductivity type gate region 57 through emitter shunts with two typical shunts illustrated in cross-section at reference numeral 62.
Figure 5 is a top view of one half of the thyristor illustrated in cross-section in
Figure 4. From this view it is clear that the outer perimeter of the gate contact 60 and the inner edge of the emitter region 58 is in the shape of a polygon. Along each of the sides of the polygon there is a row of emitter shunts. Two typical shunts are identified in the top view by reference numeral 64. The emitter shunts comprising each row are distributed such that the distance between each of the shunts and the inner edge of the emitter region is substantially equal. The remainder of the shunts are distributed over the surface of the emitter region 58 in a rectangular pattern. This structure assures that the emitter 58 will turn-on uniformly around its edge and increases the uniformity of the distribution of the charging current thereby improving the turn-on and dV/dt characteristics of the thyristor.
Figure 6 is a cross-section of another embodiment of the thyristor which is the subject of this invention. The circular semiconductor structure 84 includes a P-conductivity type anode region 75. Electrical contact with the anode region 75 is provided by a metallic layer 83. Immediately over
lying the P-conductivity type anode region 75 and forming a PN junction therewith is
an N-conductivity type region 76. A P
conductivity type gate region 77 forms a
PN junction with N-conductivity region 76.
The P-conductivity type gate region 77
forms a PN junction with the N-conduc
tivity type emitter region 78 with portions
of both of these regions extending to the
upper surface 85 of the semiconductor struc
ture 84 forming a flat upper surface 85.
Overlying the central portion of the upper
surface 85 of the semiconductor structure
84 is a metallic gate contact 79. Electrical
contact to the emitter region 78 is through
emitter contact 80. The emitter contact 80
makes contact with the emitter region 78
and to the gate region 77 through emitter shunts illustrated in cross-section at reference numeral 81.
The thyristor illustrating cross-section in
Figure 6 is shown in top view in Figure 7.
From this view it is clear that the inner edge 82 of the emitter region 78 is a polygon. Distributed along the inner edge 82 of the emitter region 78 and spaced substantially uniformly from this edge are emitter shunts 81 with two typical shunts identified in the top view by reference numeral 86.
The remainder of the emitter region 78 is covered by emitter shunts 81 spaced in a hexagonal pattern. Providing shunts along the inner edge oft he emitter 78 such that they are spaced - uniformly from this edge substantially improves the operation of the device as discussed previously.
Another embodiment of the improved thyristor shown in cross-section in Fig. 8 and in half top view in Fig. 9. The thyristor includes an anode region 91. Electrical contact is made to the anode region 91 through a metallic anode contact 92. Overlying the
P-conductivity type anode region 91 and forming a PN junction therewith is an Nconductivity type region 87 which forms a second PN junction with a P-conductivity type gate region 94. Portions of the P-conductivity type gate region 94 and the Nconductivity type emitter region 95 extend to the upper surface 96 of the semiconductor structure 97. Overlying and making contact with the P-conductivity type gate region 94 is a metallic gate contact 88. Overlying the N-conductivity type emitter region 95 and making electrical contact therewith is a metallic emitter contact 93. Smaller regions of P-conductivity type material extend to the upper surface and make contact with the emitter contact 93 to form emitter shunts 99. Typical emitter shunts are illustrated in cross-section at reference numeral 99.
Figure 9 is a top view of the thryristor shown in cross-section in Figure 8. From this view it is clear that the inner edge of the emitter region 95 is in the form of a polygon. Distributed along the inner edge of the emitter region 95 and spaced substantially equidistant therefrom is a row of emitter shunts. Two typical shunts so spaced are identified in top view by reference numeral 88. The remainder
of the emitter shunts are distributed over the emitter 95 in a substantially rectangular pattern. This pattern of shunts leads to a uniform turn-on characteristic around the
entire perimeter of the emitter and assures
a more uniform distribution of the charg
ing current greatly improving the overall
operation of the device.
Another embodiment of the improved
thyristor illustrated in cross-section in Fig.
10 and in half top view in Fig. 11. The
semiconductor structure 106 includes a P conductivity type anode region 100 and an overlying N-conductivity type region
101 forming a PN junction therebetween.
Electrical contact with this anode region
100 is through a metallic layer 107. Ovr- lying the Neonductivity type conductor region 101 is a P-conductivity type gate region 102. Portions of the P-conductivity type gate region 102 and the Nconductivity type emitter region 103 extend to the upper surface 107 of the semiconductor structure 106 forming a substantially flat upper surface 107. Overlying and electrically contacting the emitter region 103 is a metallic emitter contact region 104.
Electrical contact to the gate region 102 is through a metallic gate contact 105.
Positioned around the inner edge of the emitter region 103 is row emitter shunts with two members of this row illustrated in cross-section at reference numeral 108.
The members of this row are positioned such that each of the shunts comprising this row are substantially the same distance from the inner edge of the emitter region
103. Two of these shunts are identified in cross-section by reference numeral 108.
The remainder of the shunts are distributed uniformly in a square grid over the remainder of the emitter region with three typical shunts identified in top view at reference numeral 109.
The various embodiments of the invention described above can be constructed being well known in process techniques.
Doping concentration currently used to form the various PN junctions used in thyristors are suitable for use in forming the junction of the various thyristors disclosed herein.
From the above discussion it can be easily appreciated that by utilizing an emitter region having an inner edge in the shape of a polygon that it is easy to distribute the emitter shunts nearest to the inner edge of the emitter such that they form a plurality of rows parallel to the lines forming the inner edge and some are substantially the same distance from the inner edge. This improves the turn-on and dV/dt characteristic of the thyristor as previously discussed.
WHAT WE CLAIM IS:
1. A thyristor having a first region, comprising an emitter, on one surface, the first region having an inner boundary having portions which lie on the perimeter of a regular polygon area, said inner boundary being formed by plurality of lines which are exclusively straight;
a second region comprising a gate disposed adjacent the first region and forming a PN junction with first region, said second region disposed on said first region opposite said one surface and extending to said one surface within the area defined by the polygon;
emitter shunts disposed in said first region, at least a portion of the emitter shunts being disposed in a first series of emitter shunts which form rows, which rows are exclusively straight, said portion of the exclusively straight rows of said first series of rows of emitter shunts being spaced from and parallel to the exclusively straight lines forming said inner boundary, said first row of emitter shunts being spaced apart and having a spacing from one another;
a second series of emitter shunts being spaced apart from one another, the spacing of the second series, from any one shunt to another thereof, being greater than the spacing of the first series from any one shunt to another thereof;
a third region disposed on the side of said second region opposite said first region;
said third region forming a PN junction with said second region; and
a fourth region disposed on the side of said third region opposite said second region;
said fourth region forming a PN junction with said third region.
2. A thyristor according to Claim 1 wherein said polygon comprises a square.
3. A thyristor according to Claim 1 wherein said polygon comprises a hexagon.
4. A thyristor according to any of the preceding claims wherein additional portions of said first region, other than said portions of said inner boundary which lie on the perimeter of said polygon area, emanate from said polygon area and wherein additional portions of said exclusively straight rows of said first series of emitter shunts are spaced from and parallel to the exclusively straight rows of the additional portions of said inner boundary.
5. A thyristor substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (5)
- **WARNING** start of CLMS field may overlap end of DESC **.conductivity type anode region 100 and an overlying N-conductivity type region101 forming a PN junction therebetween.Electrical contact with this anode region100 is through a metallic layer 107. Ovr- lying the Neonductivity type conductor region 101 is a P-conductivity type gate region 102. Portions of the P-conductivity type gate region 102 and the Nconductivity type emitter region 103 extend to the upper surface 107 of the semiconductor structure 106 forming a substantially flat upper surface 107. Overlying and electrically contacting the emitter region 103 is a metallic emitter contact region 104.Electrical contact to the gate region 102 is through a metallic gate contact 105.Positioned around the inner edge of the emitter region 103 is row emitter shunts with two members of this row illustrated in cross-section at reference numeral 108.The members of this row are positioned such that each of the shunts comprising this row are substantially the same distance from the inner edge of the emitter region 103. Two of these shunts are identified in cross-section by reference numeral 108.The remainder of the shunts are distributed uniformly in a square grid over the remainder of the emitter region with three typical shunts identified in top view at reference numeral 109.The various embodiments of the invention described above can be constructed being well known in process techniques.Doping concentration currently used to form the various PN junctions used in thyristors are suitable for use in forming the junction of the various thyristors disclosed herein.From the above discussion it can be easily appreciated that by utilizing an emitter region having an inner edge in the shape of a polygon that it is easy to distribute the emitter shunts nearest to the inner edge of the emitter such that they form a plurality of rows parallel to the lines forming the inner edge and some are substantially the same distance from the inner edge. This improves the turn-on and dV/dt characteristic of the thyristor as previously discussed.WHAT WE CLAIM IS: 1. A thyristor having a first region, comprising an emitter, on one surface, the first region having an inner boundary having portions which lie on the perimeter of a regular polygon area, said inner boundary being formed by plurality of lines which are exclusively straight; a second region comprising a gate disposed adjacent the first region and forming a PN junction with first region, said second region disposed on said first region opposite said one surface and extending to said one surface within the area defined by the polygon; emitter shunts disposed in said first region, at least a portion of the emitter shunts being disposed in a first series of emitter shunts which form rows, which rows are exclusively straight, said portion of the exclusively straight rows of said first series of rows of emitter shunts being spaced from and parallel to the exclusively straight lines forming said inner boundary, said first row of emitter shunts being spaced apart and having a spacing from one another; a second series of emitter shunts being spaced apart from one another, the spacing of the second series, from any one shunt to another thereof, being greater than the spacing of the first series from any one shunt to another thereof; a third region disposed on the side of said second region opposite said first region; said third region forming a PN junction with said second region; and a fourth region disposed on the side of said third region opposite said second region; said fourth region forming a PN junction with said third region.
- 2. A thyristor according to Claim 1 wherein said polygon comprises a square.
- 3. A thyristor according to Claim 1 wherein said polygon comprises a hexagon.
- 4. A thyristor according to any of the preceding claims wherein additional portions of said first region, other than said portions of said inner boundary which lie on the perimeter of said polygon area, emanate from said polygon area and wherein additional portions of said exclusively straight rows of said first series of emitter shunts are spaced from and parallel to the exclusively straight rows of the additional portions of said inner boundary.
- 5. A thyristor substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US77944777A | 1977-03-21 | 1977-03-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1602216A true GB1602216A (en) | 1981-11-11 |
Family
ID=25116481
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB974778A Expired GB1602216A (en) | 1977-03-21 | 1978-03-13 | Thyristor having emitter shunts uniformly spaced from edge of the emitter |
Country Status (8)
| Country | Link |
|---|---|
| JP (1) | JPS53116082A (en) |
| BE (1) | BE865003A (en) |
| BR (1) | BR7801555A (en) |
| CA (1) | CA1108309A (en) |
| DE (1) | DE2811760A1 (en) |
| FR (1) | FR2385226A1 (en) |
| GB (1) | GB1602216A (en) |
| IN (1) | IN149647B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58222571A (en) * | 1982-06-19 | 1983-12-24 | Mitsubishi Electric Corp | Thyristor |
| JP3225334B2 (en) * | 1995-06-14 | 2001-11-05 | 株式会社新川 | Lead frame detection device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2254880B1 (en) * | 1973-12-12 | 1978-11-10 | Alsthom Cgee | |
| JPS5155677A (en) * | 1974-11-11 | 1976-05-15 | Hitachi Ltd | HANDOTAISEIGYOSEIRYUSOCHI |
| GB1546094A (en) * | 1975-04-11 | 1979-05-16 | Aei Semiconductors Ltd | Thyristors |
| DE2520134C3 (en) * | 1975-05-06 | 1978-10-19 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Thyristor with a rectangular semiconductor element |
-
1978
- 1978-02-07 IN IN139/CAL/78A patent/IN149647B/en unknown
- 1978-02-24 CA CA297,837A patent/CA1108309A/en not_active Expired
- 1978-03-13 GB GB974778A patent/GB1602216A/en not_active Expired
- 1978-03-15 BR BR7801555A patent/BR7801555A/en unknown
- 1978-03-17 BE BE1008771A patent/BE865003A/en not_active IP Right Cessation
- 1978-03-17 DE DE19782811760 patent/DE2811760A1/en not_active Withdrawn
- 1978-03-20 JP JP3118078A patent/JPS53116082A/en active Pending
- 1978-03-20 FR FR7808033A patent/FR2385226A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| IN149647B (en) | 1982-02-27 |
| BE865003A (en) | 1978-09-18 |
| JPS53116082A (en) | 1978-10-11 |
| BR7801555A (en) | 1978-10-31 |
| FR2385226A1 (en) | 1978-10-20 |
| CA1108309A (en) | 1981-09-01 |
| DE2811760A1 (en) | 1978-09-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PCNP | Patent ceased through non-payment of renewal fee |