CA1108309A - Thyristor having emitter shunts uniformly spaced from edge of the emitter - Google Patents
Thyristor having emitter shunts uniformly spaced from edge of the emitterInfo
- Publication number
- CA1108309A CA1108309A CA297,837A CA297837A CA1108309A CA 1108309 A CA1108309 A CA 1108309A CA 297837 A CA297837 A CA 297837A CA 1108309 A CA1108309 A CA 1108309A
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- Prior art keywords
- region
- emitter
- shunts
- thyristor
- polygon
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- 230000002730 additional effect Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 13
- ODPOAESBSUKMHD-UHFFFAOYSA-L 6,7-dihydrodipyrido[1,2-b:1',2'-e]pyrazine-5,8-diium;dibromide Chemical compound [Br-].[Br-].C1=CC=[N+]2CC[N+]3=CC=CC=C3C2=C1 ODPOAESBSUKMHD-UHFFFAOYSA-L 0.000 description 6
- 239000005630 Diquat Substances 0.000 description 6
- 238000009826 distribution Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000002674 ointment Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000009827 uniform distribution Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000009828 non-uniform distribution Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0839—Cathode regions of thyristors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
- Bipolar Transistors (AREA)
Abstract
46,307 THYRISTOR HAVING EMITTER SHUNTS UNIFORMLY
SPACED FROM EDGE OF THE EMITTER
ABSTRACT OF THE DISCLOSURE
A thyristor utilizing emitter shunts uniformly distributed around the inner edge of the emitter is dis-closed. The perimeter of the gate contact and the inner edge of the emitter are in the form of a polygon with a row of shunts positioned at a substantially uniform dis-tance from the perimeter of the gate contact and the inner edge of the emitter. This substantially improves the turn-on and dV/dt characteristics of the thyristor.
SPACED FROM EDGE OF THE EMITTER
ABSTRACT OF THE DISCLOSURE
A thyristor utilizing emitter shunts uniformly distributed around the inner edge of the emitter is dis-closed. The perimeter of the gate contact and the inner edge of the emitter are in the form of a polygon with a row of shunts positioned at a substantially uniform dis-tance from the perimeter of the gate contact and the inner edge of the emitter. This substantially improves the turn-on and dV/dt characteristics of the thyristor.
Description
BACKGROUND OF THE INVENTION
Field o~ the Invention .
The invention relates to semiconductor devices and more particularly to thyristors utilizing an emitter with a substantially straight inner edge and emitter shunts posi~ioned in a row along this edge with the shunts com-prising the row uniformly positioned from the inner edge of the emitter.
Descripkion of the Prior Art It is well known in the art that emitter shunts can be used to improve power thyristor dV/dt and emitter turn-on characteristics. In the prior art, the so-called distributed shunts were typically arranged either in square or hexagonal arrays a~d distributed over the emitter region. The inner edge of prior art emitter regions were usually round. These geometries created a discontinuity in the distributlon of the shunts around the perimeter of the gate and the inner edge of the emitter region. The emitter turns on first in the regions where the emitter ' ' . .` ' : ' ' :, ' ~: ' : :. .
' :~ , ` : : : :
:' '' : ' ,, ' ' :
3~A9 L~ 6,307 shunts are closest to the lnner edge of the emitter. Thisis a direct result of the non-uniform shunting resistance between the inner edge of the emitter and the shunts nea~est this edge. Additionally, the charging current associated with the rate of ~ of the anode voltage must fLow t;o the cathode through the emitter shunts. Areas having a low and non-uniform distribution density of emit~er shunts, due to the discontinuities discussed above, tend to turn-on first due to lower charging currents.
The areas of low charging current establish the permissible rate of rise of the anode voltage. The net result of these discontinuities is a non-~miform emitter turn-on characteristic and a lowering of the d~/dt capability of the thyristor.
SUMMARY OF THE INVENTION ~-- :
The preferred embodiment of the thyristor which :' is the sub~ect of this lnvention utilizes an emitter region having an inner edge in the form of a polygon. Along the substantiaIly straight edges of the polygon and spaced uniformly from the inner edge of the emitter region is a row of emi.tter shunts. The remainder of the emltter area also includes emi.tter shunts distributed in a uniform pattern. This new geometry assures that the distribution of the emitter shunts along the inner edge of the emitter - and the outer perimeter of the gate contact is uniform.
This assures that the turn-on characteristics of the .: ;
thyristor are substantially uniform across the entire - ~ emitter area and that the charging current, assoclated with a rise in the anode voltage is uniformly distributed over the emitter region. This substantially improves the 3~
turn-on characteristics of the emitter and dV/dt capability of the thyristor.
DESCRIPTION OF THE DRAWINGS
Figure 1 is a top view of a typical prior art thyristor;
Fig. 2 is a cross-section of a first embodiment of the improved thyristor;
Fig. 3 is a top view of the thyristor illustrating the cross-section of Fig. 2;
Fig. 4 is a cross-section of a second embodiment of the improved thyristor;
Fig. 5 is a top view o~ the thyristor illustrating the cross-section of Figure 4;
Fig. 6 is a cross-section of a third embodiment of the improved thyristor;
Fig. 7 is a top view of the thyristor lllustratlng the cross-section in Fig. 6;
Fig.;8 is~cross-section view of a third embodiment of the~improved thyristorS
Fig. 9 is a top view of the thyristor illustrated in cross-section in Fig. 8;
Fig. 10 is a cross section of a fourth embodiment of the improved thyristor; and Fig. 11 ls a top view of the thyrlstor illustrated ~ .
in cross-section~in Fig. 10.
DE
- Figure 1 is a top view of a typical prior art - thyristor utilizing emitter shunts. ~These.prior art devices ~ `
typically utllized a circular gate contact 30. The lnner edge 31 of the em~tter region was also circular with the L~6,307 emitter ~hunts arranged in a hexagonal pattern and distributed over the entire emitter region. rrwO typical emitter shunts are identified by reference number 32 in ~ig. 1.
It can be seen from the top view of this prior art thyristor that the emlkter shunts closest to the inner edge o~ the emit~er region are not uniformly distributed with respect to t;he inner edge of the emitter. It ls well known that this causes the turn-on characteristics of the emitter region to be non~uniform and lowers the dV/dt ` capability of the thyristor.
The improved thyristor which is the sub~ect of ;~, this app]ication utilizes a circular semiconductor structure. One embodiment of the thyristor is illustrated in cross-section in Fig. 2 and in half top view in Fig. 3.
The thyristor includes an anode region 40. In the preferred embodiment the anode region 40 is a thin ., .
layer of P-conductivity type silicon. Electrical contact is made to the anode region 40 through a metallic contact ~ ~ ;
layer 48. Immediately overlying the anode region 40 and forming a PN junction therewith is a N-conductivity type ; silicon region 41. Overlying the N-conductivity type region 41 and forming a PN junction therewith is a P-conductivity type gate region 42. An N--conductivity type ; emitter region 43 forms a PN junction with the gate region 42.
Portions of the P-conductivity type gate region and the `~
N-conductivity type emitter region extend to the upper surface 51 of the semiconductor structure 50 with the - inner edge of the emitter region 43 being in the form of a polygon. r~he central portion of the P-conductivity type ~ ' .
:
46,3~7 gate region 42 makes electrical contact with the metallic gate terminal 44. Circular shunt regi.ons 46 of P-type material also extend from the upper surface 51 of the semiconductor structure 50 to the gate region 42. These regions make contact with an emitter terminal L15. A row of emitter shunts is distribu~ed around the lnner edge of the emitter region 43 in a pattern such that each of the shunts comprising the row is khe same distance from the inner edge of the emitter. Two typical shunts of this row are identified in Fig. 3 by reference numeral 47. ~he remainder of the emitte.r shunts are arranged in a square pattern and uniformly distributed over the remainder of the emitter region 43. This distribution of emitter shunts assures a more uniform turn-on of the emitter region 43 because the uniform pattern of emitter shunts along the inner edge of the emitter region 43 results i.n a sub-stantially uniform distribution of the gate to emitter current along the inner edge of the emitter region 43. ~;
The charging current resulting from a rise in the anode voltage is also more uniformly distributed over the emitter region 43 resulting in an increase in the rate of rise (d~/dt) required to turn-on the thyristor. These `
improvements in emitter turn-on and dV/dt characteristics are attributable to the more uniform shunting resistance ;~
between the inner edge of the emitter region 43 and the shunts nearest this edge of the emitter region 43. Since `
the semiconductor structure is symrnetrical only one half of the top view is shown in ~ig. 3.
Another embodi.nent of the thyristor which is the `
subject of this invention is illustrated in cross-section .' ' ~
Ll ~i, 3 () 7 in ~E~lg. 4 and in one half top view in Fig. 5. This embodiment utilizes a circular semiconductor structure 54 including a P~condllct:Lv:l.ty type anode region 55.
Electrlcal contact -to the anode region 55 ls provlded by a metall.ic layer 61. Irnmedlately overlying the anode region 55 and forming a PN Junctlon therewlth is an N-conduG~iv.ity type region 56. The N~conductivity type region 56 ~orms a PN ~unction with P~conductivity type ~ :
gate region 57. An N-conduc-tivity t~pe emltter region 58 .;
extends from the gate region 57 to the upper surface 63 -~
of the semiconductor structure 54 and forms a PN Junction : , with the gate region 57. Portions of the gate region also ~:~
extends to the upper surface 63 of the semiconductor structure 54. Overlying the central portion of the semi~
conductor structure 54 and maklng electrlcal contact wlth the P-conductivity type gate reglon 57 is a metallic gate contact 60. Overlying the N-conductlvity type emitter re~ion 58 is an emittèr contact 59. The emitter contact 59 makes electrical contact with the P-conductivity type gate region 57 through emitter shunts with two typical shunts i.].lustrated in cross-section at reference numeral 62.
Figure 5 is a top view of one half of the thyristor illustrated i.:n cross-section in Figure 4. From thls view it is clear that the outer perimeter of the gate contact 60 and the inner edge of the emitter region 58 is in the shape of a polygon. Along each of the sides of the polygon .. .
there is a row of emitter shunts. Two typical shunts are identified in the top view by reference numeral 64. ~he ~.
emitter shunts comprising each row are distributed such 30 that the distance ~etween each of the shunts and the inner ~.
~ , :~ ' '' ' .
.: .
~6, 3~7 .P~ 3~'~
edge of' the em:Ltter reglorl is substantially equal. The rema-lnder of the shu~ts are distributed over the surface ol' the emltter region 58 ln a rectangular pattern. This structure assures that the emltter 58 w:Lll turn-on un:Lformly around its edge and increases t,he uniformity of the distribu-tion of -the charglng current thereby improvlng the turn-on and d~/dt characterlstics of the thyrlstor.
Figure 6 is a cross-sect,ion of` another embodiment of the thyristor which is the subJect of this inventlon.
The circular semiconduGtor structure 84 includes a P~conductivity type ancde reg~on 75. Electrlcal contact with the anode region 75 is provided by a metallic layer 83.
Immediately overlying the P-conductivity type anode region 75 and f'orming a PN junction therewith is an N-conductivity type region 76. A P-conducti~ity type gate region 77 f`orms a PN ~unction with N-conductivity region 76. The , P-conductivity type gate region 77 f`orms a PN junction with :~ the N-conductivlty type emitter region 78 with portlons of both of these regions extending to the upper surface 85 of ' 20 the semiconductor structure 84 forming a f`lat upper surface 85. Overlylng the central portion of` the upper surf'ace 85 of the semiconductor structure 84 is a metallic gate contact 79. ~lectrical contact to the emitter region 78 is through emitter contact 80. The emltter contact 80 makes contact with the emitter region 78 and to the gate reglon 77 through emitter shunts illustrated in cross-section at reference numeral 81. ,, ; ~he thyristor illustrating cross-section in , Figure 6 is shown ln top view in Flgure 7. From this view it is clear that -the :Lnner edge 82 of the emitter reglon 78 f f 3;~
is a polygon. Distributed along the inner eclge 82 of the emitter region 78 and spaced substantially uniformly from thls edge are emit-ter shunts 81 with two typical shunts identified in the top view by reference numeral 86. The remainder of the emitter region 78 is covered by emitter shunt;s 81 spaced in a hexagonal pattern. Providing shunts along the inner edge of the emltter 78 such that they are spaced uniformly from this edge substantially improves the operation of the device as discussed prevlously.
Another embodiment of the improved thyristor shown in cross-section in Fig. 8 and in half top view in Fig. 9. The thyristor includes an anode region 91.
Electrical contact is made to the anode region 91 through a metallic anode contact 92. Overlying the P-conductivity type anode region 91 and forming a PN ~unction therewith is an N-conductivity type region 87 which forms a second PN junction with a P-conductivity type gate region 94. ~ ~;
Portions of the P-conductivity type gate region 94 and the N-conductivity type emitter region 95 extend to the upper surface 96 of the semiconductor structure 97. Overlying and making contact with the P~conductivity type gate region 94 is a metallic gate contact 88. Overlying the N-conductivity type emitter region 95 and making electrical contact therewith is a metallic emitter contact 93.
Smaller regions of P-conductivity type material extend to the upper surface and make contact with the emitter contact 93 to form emitter shunts 99. Typical emitter shunts are illustrated in cross-section at reference numeral 99.
Figure 9 is a to~ view of the thyristor shown in ''-.
~R3-~9 46, 307 ' :
cross-sect.ion in Figure 8. ~rom this view it is clear ~ -that the inner edge of the emitter region 95 is in the form of a polygon. Distributed along khe inner edge of the emitter reglon 95 and spaced substantially equidistant therefrom is a row of emitter shunts. Two typical shunts so spaced are identified in top view by re~erence numeral The remainder of the emitter shunts are distributed over the emitter 95 in a substantially rectangular pattern.
This pattern of shunts leads to a uniform turn-on characteristic around the entire perimeter o~ the emitter and assures a more uniform distribution of the charging ~ current greatly improving the overall operation of the device.
; Another embodiment of the improved thyristor illustrated in cross-section in Fig. 10 and in half top . . .
view ln Fig. 11. The semiconductor structure 106 includes a P-conductivity type anode region 100 and an overlying N-conductivity type region ~01 forming a PN junction there-~ between. Electrical contact wLth this anode region 100 ls - through a metallic layer lO7.; Overlying the N-conductivity ~ `~
` 20 type conductor reglon 101 ls a P-conductiviky type gate ; ~-- region 102. ~Portions of the P-conductivity type gate reglon 102 and the N-conductivlty type emitter region 103 extend to the upper surface 107 of the semiconductor structure 106 formlng a substantlally flat upper surface 107.
Overlying and electrically contacting the emitter region 103 `~
is a metallic emitter contact region 104. Electrical ~; ~contact to~the gate region 102 is through a metalllc gate contact 105. Positioned around the inner edge of the emitter region 103 is row emitter shunks with two members ~ 30 of this row illustrated in cross-section ak reference " ~ i ~9~ '-, , ~
. :
3~ 6~ 3 7 numeral ~o8. The members of this row are positioned such that each o~ the shunts comprislng thls row are sub-stantially the same distance from the inner edge of the emîtter region 103. Two of these shunts are identified in cross-section by reference numeral 108. The remainder of the shunts are distributed uniformly in a square grid over the remainder of the emitter region with three typlcal shunts identified in top view at reference numeral 109.
The various embodiments of the lnvention described above can be constructed being well known in process techniques. Doping concentration currently used to form the various PN junctions used in thyristors are sultable for use in formlng the junction of the various thyristors disclosed herein.
From tne above discussion it can be easily appreciated that by utilizing,an emitter region having an inner edge in the shape of a polygon that it is easy to distribute the emitter shunts nearest to the inner of the emitter such that they are substantially the same distance from the inner edge. Thls improves the turn-on and dV/dt characteristic of the thyristor as previously discussed.
.
, ' 10~
: ;
:
Field o~ the Invention .
The invention relates to semiconductor devices and more particularly to thyristors utilizing an emitter with a substantially straight inner edge and emitter shunts posi~ioned in a row along this edge with the shunts com-prising the row uniformly positioned from the inner edge of the emitter.
Descripkion of the Prior Art It is well known in the art that emitter shunts can be used to improve power thyristor dV/dt and emitter turn-on characteristics. In the prior art, the so-called distributed shunts were typically arranged either in square or hexagonal arrays a~d distributed over the emitter region. The inner edge of prior art emitter regions were usually round. These geometries created a discontinuity in the distributlon of the shunts around the perimeter of the gate and the inner edge of the emitter region. The emitter turns on first in the regions where the emitter ' ' . .` ' : ' ' :, ' ~: ' : :. .
' :~ , ` : : : :
:' '' : ' ,, ' ' :
3~A9 L~ 6,307 shunts are closest to the lnner edge of the emitter. Thisis a direct result of the non-uniform shunting resistance between the inner edge of the emitter and the shunts nea~est this edge. Additionally, the charging current associated with the rate of ~ of the anode voltage must fLow t;o the cathode through the emitter shunts. Areas having a low and non-uniform distribution density of emit~er shunts, due to the discontinuities discussed above, tend to turn-on first due to lower charging currents.
The areas of low charging current establish the permissible rate of rise of the anode voltage. The net result of these discontinuities is a non-~miform emitter turn-on characteristic and a lowering of the d~/dt capability of the thyristor.
SUMMARY OF THE INVENTION ~-- :
The preferred embodiment of the thyristor which :' is the sub~ect of this lnvention utilizes an emitter region having an inner edge in the form of a polygon. Along the substantiaIly straight edges of the polygon and spaced uniformly from the inner edge of the emitter region is a row of emi.tter shunts. The remainder of the emltter area also includes emi.tter shunts distributed in a uniform pattern. This new geometry assures that the distribution of the emitter shunts along the inner edge of the emitter - and the outer perimeter of the gate contact is uniform.
This assures that the turn-on characteristics of the .: ;
thyristor are substantially uniform across the entire - ~ emitter area and that the charging current, assoclated with a rise in the anode voltage is uniformly distributed over the emitter region. This substantially improves the 3~
turn-on characteristics of the emitter and dV/dt capability of the thyristor.
DESCRIPTION OF THE DRAWINGS
Figure 1 is a top view of a typical prior art thyristor;
Fig. 2 is a cross-section of a first embodiment of the improved thyristor;
Fig. 3 is a top view of the thyristor illustrating the cross-section of Fig. 2;
Fig. 4 is a cross-section of a second embodiment of the improved thyristor;
Fig. 5 is a top view o~ the thyristor illustrating the cross-section of Figure 4;
Fig. 6 is a cross-section of a third embodiment of the improved thyristor;
Fig. 7 is a top view of the thyristor lllustratlng the cross-section in Fig. 6;
Fig.;8 is~cross-section view of a third embodiment of the~improved thyristorS
Fig. 9 is a top view of the thyristor illustrated in cross-section in Fig. 8;
Fig. 10 is a cross section of a fourth embodiment of the improved thyristor; and Fig. 11 ls a top view of the thyrlstor illustrated ~ .
in cross-section~in Fig. 10.
DE
- Figure 1 is a top view of a typical prior art - thyristor utilizing emitter shunts. ~These.prior art devices ~ `
typically utllized a circular gate contact 30. The lnner edge 31 of the em~tter region was also circular with the L~6,307 emitter ~hunts arranged in a hexagonal pattern and distributed over the entire emitter region. rrwO typical emitter shunts are identified by reference number 32 in ~ig. 1.
It can be seen from the top view of this prior art thyristor that the emlkter shunts closest to the inner edge o~ the emit~er region are not uniformly distributed with respect to t;he inner edge of the emitter. It ls well known that this causes the turn-on characteristics of the emitter region to be non~uniform and lowers the dV/dt ` capability of the thyristor.
The improved thyristor which is the sub~ect of ;~, this app]ication utilizes a circular semiconductor structure. One embodiment of the thyristor is illustrated in cross-section in Fig. 2 and in half top view in Fig. 3.
The thyristor includes an anode region 40. In the preferred embodiment the anode region 40 is a thin ., .
layer of P-conductivity type silicon. Electrical contact is made to the anode region 40 through a metallic contact ~ ~ ;
layer 48. Immediately overlying the anode region 40 and forming a PN junction therewith is a N-conductivity type ; silicon region 41. Overlying the N-conductivity type region 41 and forming a PN junction therewith is a P-conductivity type gate region 42. An N--conductivity type ; emitter region 43 forms a PN junction with the gate region 42.
Portions of the P-conductivity type gate region and the `~
N-conductivity type emitter region extend to the upper surface 51 of the semiconductor structure 50 with the - inner edge of the emitter region 43 being in the form of a polygon. r~he central portion of the P-conductivity type ~ ' .
:
46,3~7 gate region 42 makes electrical contact with the metallic gate terminal 44. Circular shunt regi.ons 46 of P-type material also extend from the upper surface 51 of the semiconductor structure 50 to the gate region 42. These regions make contact with an emitter terminal L15. A row of emitter shunts is distribu~ed around the lnner edge of the emitter region 43 in a pattern such that each of the shunts comprising the row is khe same distance from the inner edge of the emitter. Two typical shunts of this row are identified in Fig. 3 by reference numeral 47. ~he remainder of the emitte.r shunts are arranged in a square pattern and uniformly distributed over the remainder of the emitter region 43. This distribution of emitter shunts assures a more uniform turn-on of the emitter region 43 because the uniform pattern of emitter shunts along the inner edge of the emitter region 43 results i.n a sub-stantially uniform distribution of the gate to emitter current along the inner edge of the emitter region 43. ~;
The charging current resulting from a rise in the anode voltage is also more uniformly distributed over the emitter region 43 resulting in an increase in the rate of rise (d~/dt) required to turn-on the thyristor. These `
improvements in emitter turn-on and dV/dt characteristics are attributable to the more uniform shunting resistance ;~
between the inner edge of the emitter region 43 and the shunts nearest this edge of the emitter region 43. Since `
the semiconductor structure is symrnetrical only one half of the top view is shown in ~ig. 3.
Another embodi.nent of the thyristor which is the `
subject of this invention is illustrated in cross-section .' ' ~
Ll ~i, 3 () 7 in ~E~lg. 4 and in one half top view in Fig. 5. This embodiment utilizes a circular semiconductor structure 54 including a P~condllct:Lv:l.ty type anode region 55.
Electrlcal contact -to the anode region 55 ls provlded by a metall.ic layer 61. Irnmedlately overlying the anode region 55 and forming a PN Junctlon therewlth is an N-conduG~iv.ity type region 56. The N~conductivity type region 56 ~orms a PN ~unction with P~conductivity type ~ :
gate region 57. An N-conduc-tivity t~pe emltter region 58 .;
extends from the gate region 57 to the upper surface 63 -~
of the semiconductor structure 54 and forms a PN Junction : , with the gate region 57. Portions of the gate region also ~:~
extends to the upper surface 63 of the semiconductor structure 54. Overlying the central portion of the semi~
conductor structure 54 and maklng electrlcal contact wlth the P-conductivity type gate reglon 57 is a metallic gate contact 60. Overlying the N-conductlvity type emitter re~ion 58 is an emittèr contact 59. The emitter contact 59 makes electrical contact with the P-conductivity type gate region 57 through emitter shunts with two typical shunts i.].lustrated in cross-section at reference numeral 62.
Figure 5 is a top view of one half of the thyristor illustrated i.:n cross-section in Figure 4. From thls view it is clear that the outer perimeter of the gate contact 60 and the inner edge of the emitter region 58 is in the shape of a polygon. Along each of the sides of the polygon .. .
there is a row of emitter shunts. Two typical shunts are identified in the top view by reference numeral 64. ~he ~.
emitter shunts comprising each row are distributed such 30 that the distance ~etween each of the shunts and the inner ~.
~ , :~ ' '' ' .
.: .
~6, 3~7 .P~ 3~'~
edge of' the em:Ltter reglorl is substantially equal. The rema-lnder of the shu~ts are distributed over the surface ol' the emltter region 58 ln a rectangular pattern. This structure assures that the emltter 58 w:Lll turn-on un:Lformly around its edge and increases t,he uniformity of the distribu-tion of -the charglng current thereby improvlng the turn-on and d~/dt characterlstics of the thyrlstor.
Figure 6 is a cross-sect,ion of` another embodiment of the thyristor which is the subJect of this inventlon.
The circular semiconduGtor structure 84 includes a P~conductivity type ancde reg~on 75. Electrlcal contact with the anode region 75 is provided by a metallic layer 83.
Immediately overlying the P-conductivity type anode region 75 and f'orming a PN junction therewith is an N-conductivity type region 76. A P-conducti~ity type gate region 77 f`orms a PN ~unction with N-conductivity region 76. The , P-conductivity type gate region 77 f`orms a PN junction with :~ the N-conductivlty type emitter region 78 with portlons of both of these regions extending to the upper surface 85 of ' 20 the semiconductor structure 84 forming a f`lat upper surface 85. Overlylng the central portion of` the upper surf'ace 85 of the semiconductor structure 84 is a metallic gate contact 79. ~lectrical contact to the emitter region 78 is through emitter contact 80. The emltter contact 80 makes contact with the emitter region 78 and to the gate reglon 77 through emitter shunts illustrated in cross-section at reference numeral 81. ,, ; ~he thyristor illustrating cross-section in , Figure 6 is shown ln top view in Flgure 7. From this view it is clear that -the :Lnner edge 82 of the emitter reglon 78 f f 3;~
is a polygon. Distributed along the inner eclge 82 of the emitter region 78 and spaced substantially uniformly from thls edge are emit-ter shunts 81 with two typical shunts identified in the top view by reference numeral 86. The remainder of the emitter region 78 is covered by emitter shunt;s 81 spaced in a hexagonal pattern. Providing shunts along the inner edge of the emltter 78 such that they are spaced uniformly from this edge substantially improves the operation of the device as discussed prevlously.
Another embodiment of the improved thyristor shown in cross-section in Fig. 8 and in half top view in Fig. 9. The thyristor includes an anode region 91.
Electrical contact is made to the anode region 91 through a metallic anode contact 92. Overlying the P-conductivity type anode region 91 and forming a PN ~unction therewith is an N-conductivity type region 87 which forms a second PN junction with a P-conductivity type gate region 94. ~ ~;
Portions of the P-conductivity type gate region 94 and the N-conductivity type emitter region 95 extend to the upper surface 96 of the semiconductor structure 97. Overlying and making contact with the P~conductivity type gate region 94 is a metallic gate contact 88. Overlying the N-conductivity type emitter region 95 and making electrical contact therewith is a metallic emitter contact 93.
Smaller regions of P-conductivity type material extend to the upper surface and make contact with the emitter contact 93 to form emitter shunts 99. Typical emitter shunts are illustrated in cross-section at reference numeral 99.
Figure 9 is a to~ view of the thyristor shown in ''-.
~R3-~9 46, 307 ' :
cross-sect.ion in Figure 8. ~rom this view it is clear ~ -that the inner edge of the emitter region 95 is in the form of a polygon. Distributed along khe inner edge of the emitter reglon 95 and spaced substantially equidistant therefrom is a row of emitter shunts. Two typical shunts so spaced are identified in top view by re~erence numeral The remainder of the emitter shunts are distributed over the emitter 95 in a substantially rectangular pattern.
This pattern of shunts leads to a uniform turn-on characteristic around the entire perimeter o~ the emitter and assures a more uniform distribution of the charging ~ current greatly improving the overall operation of the device.
; Another embodiment of the improved thyristor illustrated in cross-section in Fig. 10 and in half top . . .
view ln Fig. 11. The semiconductor structure 106 includes a P-conductivity type anode region 100 and an overlying N-conductivity type region ~01 forming a PN junction there-~ between. Electrical contact wLth this anode region 100 ls - through a metallic layer lO7.; Overlying the N-conductivity ~ `~
` 20 type conductor reglon 101 ls a P-conductiviky type gate ; ~-- region 102. ~Portions of the P-conductivity type gate reglon 102 and the N-conductivlty type emitter region 103 extend to the upper surface 107 of the semiconductor structure 106 formlng a substantlally flat upper surface 107.
Overlying and electrically contacting the emitter region 103 `~
is a metallic emitter contact region 104. Electrical ~; ~contact to~the gate region 102 is through a metalllc gate contact 105. Positioned around the inner edge of the emitter region 103 is row emitter shunks with two members ~ 30 of this row illustrated in cross-section ak reference " ~ i ~9~ '-, , ~
. :
3~ 6~ 3 7 numeral ~o8. The members of this row are positioned such that each o~ the shunts comprislng thls row are sub-stantially the same distance from the inner edge of the emîtter region 103. Two of these shunts are identified in cross-section by reference numeral 108. The remainder of the shunts are distributed uniformly in a square grid over the remainder of the emitter region with three typlcal shunts identified in top view at reference numeral 109.
The various embodiments of the lnvention described above can be constructed being well known in process techniques. Doping concentration currently used to form the various PN junctions used in thyristors are sultable for use in formlng the junction of the various thyristors disclosed herein.
From tne above discussion it can be easily appreciated that by utilizing,an emitter region having an inner edge in the shape of a polygon that it is easy to distribute the emitter shunts nearest to the inner of the emitter such that they are substantially the same distance from the inner edge. Thls improves the turn-on and dV/dt characteristic of the thyristor as previously discussed.
.
, ' 10~
: ;
:
Claims (4)
1. A thyristor having a first region, compris-ing an emitter, on one surface, the first region having an inner boundary having portions which lie on the peri-meter of a regular polygon area, said inner boundary be-ing formed by plurality of lines which are exclusively straight;
a second region comprising a gate disposed adjacent the first region and forming a PN Junction with first region, said second region disposed on said first region opposite said one surface and extending to said one surface within the area defined by the polygon;
emitter shunts disposed in said first region, at least a portion of the emitter shunts being disposed in a first series of emitter shunts which form rows, which rows are exclusively straight, said portion of the exclusively straight rows of said first series of rows of emitter shunts being spaced from and parallel to the exclusively straight lines forming said inner boundary, said first row of emitter shunts being spaced and having a spacing from one another;
a second series of emitter shunts being spaced apart from one another, the spacing of the second series, from any one shunt to another thereof, being greater than the spacing of the first series from any one shunt to another thereof;
a third region disposed on the side of said second region opposite said first region;
said third region forming a PN junction with said second region; and 46,307 a fourth region disposed on the side of said third region opposite said second region;
said fourth region forming a PN junction with said third region.
a second region comprising a gate disposed adjacent the first region and forming a PN Junction with first region, said second region disposed on said first region opposite said one surface and extending to said one surface within the area defined by the polygon;
emitter shunts disposed in said first region, at least a portion of the emitter shunts being disposed in a first series of emitter shunts which form rows, which rows are exclusively straight, said portion of the exclusively straight rows of said first series of rows of emitter shunts being spaced from and parallel to the exclusively straight lines forming said inner boundary, said first row of emitter shunts being spaced and having a spacing from one another;
a second series of emitter shunts being spaced apart from one another, the spacing of the second series, from any one shunt to another thereof, being greater than the spacing of the first series from any one shunt to another thereof;
a third region disposed on the side of said second region opposite said first region;
said third region forming a PN junction with said second region; and 46,307 a fourth region disposed on the side of said third region opposite said second region;
said fourth region forming a PN junction with said third region.
2. A thyristor according to claim 1 wherein addi-tional portions of said first region, other than said portions of said inner boundary which lie on the perimeter of said polygon area, emanate from said polygon area and wherein additional portions of said exclusively straight rows of said first series of emitter shunts are spaced from and parallel to the exclusively straight rows of the additional portions of said inner boundary.
3. A thyristor according to claim 1 or 2 wherein said polygon comprises a square.
4. A thyristor according to claim 1 or 2 wherein said polygon comprises a hexagon.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US77944777A | 1977-03-21 | 1977-03-21 | |
| US779,447 | 1977-03-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1108309A true CA1108309A (en) | 1981-09-01 |
Family
ID=25116481
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA297,837A Expired CA1108309A (en) | 1977-03-21 | 1978-02-24 | Thyristor having emitter shunts uniformly spaced from edge of the emitter |
Country Status (8)
| Country | Link |
|---|---|
| JP (1) | JPS53116082A (en) |
| BE (1) | BE865003A (en) |
| BR (1) | BR7801555A (en) |
| CA (1) | CA1108309A (en) |
| DE (1) | DE2811760A1 (en) |
| FR (1) | FR2385226A1 (en) |
| GB (1) | GB1602216A (en) |
| IN (1) | IN149647B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58222571A (en) * | 1982-06-19 | 1983-12-24 | Mitsubishi Electric Corp | Thyristor |
| JP3225334B2 (en) * | 1995-06-14 | 2001-11-05 | 株式会社新川 | Lead frame detection device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2254880B1 (en) * | 1973-12-12 | 1978-11-10 | Alsthom Cgee | |
| JPS5155677A (en) * | 1974-11-11 | 1976-05-15 | Hitachi Ltd | HANDOTAISEIGYOSEIRYUSOCHI |
| GB1546094A (en) * | 1975-04-11 | 1979-05-16 | Aei Semiconductors Ltd | Thyristors |
| DE2520134C3 (en) * | 1975-05-06 | 1978-10-19 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Thyristor with a rectangular semiconductor element |
-
1978
- 1978-02-07 IN IN139/CAL/78A patent/IN149647B/en unknown
- 1978-02-24 CA CA297,837A patent/CA1108309A/en not_active Expired
- 1978-03-13 GB GB974778A patent/GB1602216A/en not_active Expired
- 1978-03-15 BR BR7801555A patent/BR7801555A/en unknown
- 1978-03-17 BE BE1008771A patent/BE865003A/en not_active IP Right Cessation
- 1978-03-17 DE DE19782811760 patent/DE2811760A1/en not_active Withdrawn
- 1978-03-20 JP JP3118078A patent/JPS53116082A/en active Pending
- 1978-03-20 FR FR7808033A patent/FR2385226A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| IN149647B (en) | 1982-02-27 |
| BE865003A (en) | 1978-09-18 |
| JPS53116082A (en) | 1978-10-11 |
| BR7801555A (en) | 1978-10-31 |
| FR2385226A1 (en) | 1978-10-20 |
| GB1602216A (en) | 1981-11-11 |
| DE2811760A1 (en) | 1978-09-28 |
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