GB1599852A - Package for holding a composite semiconductor device - Google Patents
Package for holding a composite semiconductor device Download PDFInfo
- Publication number
- GB1599852A GB1599852A GB587878A GB587878A GB1599852A GB 1599852 A GB1599852 A GB 1599852A GB 587878 A GB587878 A GB 587878A GB 587878 A GB587878 A GB 587878A GB 1599852 A GB1599852 A GB 1599852A
- Authority
- GB
- United Kingdom
- Prior art keywords
- package
- layers
- wafers
- support member
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Wire Bonding (AREA)
- Bipolar Transistors (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Die Bonding (AREA)
Description
(54) PACKAGE FOR HOLDING A COMPOSITE SEMICONDUCTOR DEVICE
(71) We, VARIAN ASSOCIATES,
INC., of 611 Hansen Way, Palo Alto,
California 94303. United States of America, a corporation organized under the laws of the State of Delaware, United States of
America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:
The present invention relates to a package suitable for holding a composite semiconductor device. e.g. a power device for instance an rf power device.
In the past, semiconductor devices have been packaged by placing a transistor chip on a single piece of electrically nonconductive material, such as beryllia ceramic, to isolate electrically the chip from the package base which is typically made of copper. The prior art uses a single ceramic substrate upon which a silicon chip is placed. The thermal path is through the silicon chip. through the ceramic, and into whatever the ceramic is braized to, either a copper stud or a copper flange. The thickness of the ceramic has regard to the expansion rate difference between the ceramic and the copper braized to the ceramic.
These two materials expand at substantially different rates. Therefore, as the package gets hot during the braizing operation, the ceramic tends to crack. It is desirable to keep the braize area small and the ceramic as thick as possible to reduce the danger of cracking. However, it is also desirable to make the ceramic as thin as possible because it is a resistive path to the thermal flow through the semiconductor device. It is desirable to reduce the thickness of the base in order to reduce the thermal resistance, but the base has been made thick for structural rigidity. It will be appreciated that as requirements for higher power outputs increase, the size of the transistor chip is increased. This necessitates a larger braize area, thereby increasing the possibility of cracking. Thus, it will be appreciated that problems have to be overcome if the risk of cracking is to be reduced.
According to the present invention, there is provided a package suitable for holding a composite semiconductor device, said device comprising semiconductor dies, said package comprising: an electrically conductive support member; electrically conductive first layers, these layers being in electrical and thermal contact with said support member: electrically conductive second layers, these layers each having respective first and second sides, said first sides being able to be bonded to respective ones of said dies; and electrically non-conductive wafers, these wafers each having respective first and second sides, said first sides of said wafers being bonded to respective ones of said first layers, said second sides of said wafers being bonded to respective ones of said second layers, wherein said support member has at least one first region of thickness thinner that at least one second region of said support member, the or each said first region corresponding to the location of at least one said wafer. There can be a plurality of said first regions, wherein each of the first regions corresponds to the location of a respective one of said wafers.
Said first region can be adapted to receive at least one said wafer. Said first region can comprise at least one cavity for containing at least one said wafer. There can be a plurality of said cavities, wherein each of said cavities is for containing a respective one of said wafers. Said support member can be metallic, e.g. comprise copper. Said first layers can be metallized layers. Said second layers can be metallized layers. Said wafers can be ceramic e.g. comprise beryllia ceramic.
Said package according to the present invention can comprise means for enabling said dies to be wired to give a single semiconductor device. Said means for enabling said wiring can comprise at least one input pad and at least one output pad.
Said means for enabling said wiring can comprise an electrically non-conductive element for attaching to said support member and constituting wall means for at least partly surrounding said dies when said dies are bonded to said first sides of said second layers. Said element can be ceramic, e.g.
comprise beryllia ceramic.
When said package according to the present invention comprises said semiconductor dies, said device can be a power device, e.g. an rf power device.
The present invention will now be described by way of example with reference to the accompanying drawings, wherein:
Figure 1 is a plan view of a prior art power transistor package.
Figure 2 is a side elevation of Figure 1 taken along the section 2-2.
Figure 3 is a plan view of one preferred embodiment of the present invention.
Figure 4 is a side elevation of Figure 3 taken along the section 4-4.
Figure 5 is a plan view of another preferred embodiment of the present invention.
Figure 6 is a side elevation of Figure 5 taken along the section 6-6.
A prior art power transistor package shown in Figures 1 and 2 has a beryllia ceramic wafer 10 provided with an electrically conductive area 12 metallized on a first surface thereof, and an electrically conductive surface 14 metallized on the opposite surface thereof. The wafer is braized to a copper base 16 which acts as a heat sink. A transistor die 18 is braized to the conductive surface 14. The body of the die 18 is the collector region of the transistor device, and the collector region electrically contacts the conductive surface 14. Bond wires for serving as leads attach the emitter and base of the die 18 to input pads and output pads not shown.
In Figures 3 and 4, one embodiment of the present invention has an electrically conductive support member 20 which may be made of copper. The support member 20 has a plurality of cavities 22,24,26. A plurality of electrically non-conductive waf
ers 28,30,32, which can be of beryllia
ceramic, fit into respective ones of the
cavities 22,24,26. Each wafer has an electrically conductive first layer 34 on one side thereof, and an electrically conductive
second layer 36 on the opposite side thereof.
The layers 34,36 can be metallized layers.
The wafers are placed in the cavities 22,24,26 and fixed to the support member 20 by a braizing operation which braizes the
conductive layer 34 to the support member 20 (the base). Transistor dies 38,40,42 are braized respectively to each of the layers 36, e.g. the layer 36 shown on wafer 28.
Bonding wires (not shown) are attached to input pads and output pads not shown, by methods well known in the art.
In Figures 5 and 6, one embodiment of the present invention has a copper base 50 with cavities 52,54,56 provided therein, e.g.
by cutting. Electrically non-conductive wafers 60,62,64. which can be of beryllia ceramic, fit respectively into corresponding ones of the cavities 52,54,56. These wafers can be cut to suitable sizes for this purpose.
The wafers 60,62,64 correspond to the wafers 28,30,32 and similarly have electrically conductive first and second layers 34,36 as mentioned above. The wafers 60,62,64 are braized to the copper base 50 by utilizing the layers 34. The upper surfaces of the layers 36 are braized to respective ones of transistor dies 70,72,74. An electrically nonconductive wafer 68, which can be of beryllia ceramic, carries individual capacitive elements 76,78,80 which are associated with the dies 70,72,74 respectively. A ceramic "ring" 82, which can be of beryllia ceramic, has its lower surface bonded to the copper base 50. The ring 82 provides wall means for surrounding the dies 70,72,74 as shown.
These dies are located within an opening 84 provided in the ring 82. Bond wires for serving as leads can be used to interconnect the various elements, by methods used in the prior art. Base and collector pads 86,88 are bonded to the upper surface of the ring 82. These pads are shown as one piece each to which an input terminal and an output terminal would be suitably attached. It should be uilderstood that separate individual circuits can be packaged utilizing this technique by separately plating three pads ( as shown by the dotted lines in Figure 5) instead of the single pads 86,88. The three pads would provide for three separate circuits corresponding to three wafers and three capacitors.
The transistor package shown in Figures 5 and 6 is especially suitable for packaging devices such as those shown in copending
British patent application 458/78, (Serial No 1598841) which describes a semiconductor package for containing two individual transistors such that they can be externally connected in a push-pull relationship. The two transistors each have an input pad and an output pad and are formed on the same electrically non-conductive wafer. The transistors share a common ground plane and are wired either in a grounded emitter or grounded base configuration. The whole contents of British patent application 458/78 (Serial No 1598841) are hereby imported into the present application. A said package according to the present invention is easily adapted to package the circuit described in application 458/78 (Serial No 1598841).
Thus, output pad 86 would be metallized in two separate parts. The bonding wires would be bonded in a manner similar to that shown in application 458/78 (Serial No 1598841). For example, for a grounded base configuration, bonding wires 90 ( see Figure 5 of the present application) would be bonded from input pad 88 to one plate of capacitor 80 and then to the emitter of transistor 74. The base of transistor 74 would be connected via wire 94 to the other plate of capacitor 80 and also to a suitable ground plane, e.g. the copper support 50.
All of the connections have not been shown in Figure 5 of the present application, i.e.
Figure 5 is a simplified drawing. There are many different types of circuit wiring configurations that can be utilized by those having ordinary skill in the art, and the present invention is not limited to any one particular circuit.
In preferred embodiments according to
Figures 3,4 and 5,6 of the present application, copper support member 20,50 have been provided with cavities cut therein to hold wafers. The cavities enable the support members 20,25 to be made thick enough for structural strength, together with ensuring that the material in the cavities under each wafer is thin to lower thermal resistivity. In the embodiment of Figures 5,6, the copper base 50 can be relatively thin, because the ceramic ring 80 will provide sufficient structural rigidity for the copper base 50 to which it is bonded.
WHAT WE CLAIM IS:
1. A package suitable for holding a composite semiconductor device, said device comprising semiconductor dies, said package comprising:
an electrically conductive support member: electrically conductive first layers these layers being in electrical and thermal contact with said support member; electrically conductive second layers, these layers each having respective first and second sides, said first sides being able to be bonded to respective ones of said dies; and electrically non-conductive wafers, these wafers each having respective first and second sides, said first sides of said wafers being bonded to respective ones of said first layers, said second sides of said wafers being bonded to respective ones of said second layers wherein said support member has at least one first region of thickness thinner than at least one second region of said support member, the or each of said first region corresponding to the location of at least one said wafer.
2. A pakage as claimed in claim 1, wherein there is a plurality of said first regions, and each of which corresponds to the location of a respective one of said wafers.
3. A package as claimed in claim 1 or 2, wherein said first region is adapted to receive at least one said wafer.
4. A package as claimed in claim 3, wherein said first region comprises at least one cavity for containing at least one said wafer.
5. A package as claimed in claim 4, wherein there is a plurality of said cavities, and each of which is for containing a respective one of said wafers.
6. A package as claimed in any one of claims 1 to 5 wherein said support member is metallic.
7. A package as claimed in claim 6, wherein said support member comprises copper.
8. A package as claimed in any one of claims 1 to 7, wherein said first layers are metallized layers.
9. A package as claimed in any one of claims 1 to 8, wherein said second layers are metallized layers.
10. A package as claimed in any one of claims 1 to 9, wherein said wafers are ceramic.
11. A package as claimed in claim 10, wherein said wafers comprise beryllia ceramic.
12. A package as claimed in claim 11, when according to claim 7.
13. A package as claimed in any one of claims 1 to 12 comprising means for enabling said dies to be wired to give a single semiconductor device.
14. A package as claimed in claim 13, wherein said means for enabling said wiring comprises at least one input pad and at least one output pad.
15. A package as claimed in claim 13 or 14, wherein said means for enabling said wiring comprises an electrically nonconductive element for attaching to said support member. and constituting wall means for at least partly surrounding said dies when said dies are bonded to said first sides of said second layers.
16. A package as claimed in claim 15, wherein said element is ceramic.
17. A package as claimed in claim 16, wherein said element comprises beryllia ceramic.
18. A package as claimed in claim 1, substantially as hereinbefore described with reference to and as shown in Figures 3,4 of the accompanying drawings.
19. A package as claimed in claim 1, substantially as hereinbefore described with reference to and as shown in Figures 5,6 of the accompanying drawings.
20. A package as claimed in any one of claims 1 to 19, comprising said semiconductor dies.
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (24)
1. A package suitable for holding a composite semiconductor device, said device comprising semiconductor dies, said package comprising:
an electrically conductive support member: electrically conductive first layers these layers being in electrical and thermal contact with said support member; electrically conductive second layers, these layers each having respective first and second sides, said first sides being able to be bonded to respective ones of said dies; and electrically non-conductive wafers, these wafers each having respective first and second sides, said first sides of said wafers being bonded to respective ones of said first layers, said second sides of said wafers being bonded to respective ones of said second layers wherein said support member has at least one first region of thickness thinner than at least one second region of said support member, the or each of said first region corresponding to the location of at least one said wafer.
2. A pakage as claimed in claim 1, wherein there is a plurality of said first regions, and each of which corresponds to the location of a respective one of said wafers.
3. A package as claimed in claim 1 or 2, wherein said first region is adapted to receive at least one said wafer.
4. A package as claimed in claim 3, wherein said first region comprises at least one cavity for containing at least one said wafer.
5. A package as claimed in claim 4, wherein there is a plurality of said cavities, and each of which is for containing a respective one of said wafers.
6. A package as claimed in any one of claims 1 to 5 wherein said support member is metallic.
7. A package as claimed in claim 6, wherein said support member comprises copper.
8. A package as claimed in any one of claims 1 to 7, wherein said first layers are metallized layers.
9. A package as claimed in any one of claims 1 to 8, wherein said second layers are metallized layers.
10. A package as claimed in any one of claims 1 to 9, wherein said wafers are ceramic.
11. A package as claimed in claim 10, wherein said wafers comprise beryllia ceramic.
12. A package as claimed in claim 11, when according to claim 7.
13. A package as claimed in any one of claims 1 to 12 comprising means for enabling said dies to be wired to give a single semiconductor device.
14. A package as claimed in claim 13, wherein said means for enabling said wiring comprises at least one input pad and at least one output pad.
15. A package as claimed in claim 13 or 14, wherein said means for enabling said wiring comprises an electrically nonconductive element for attaching to said support member. and constituting wall means for at least partly surrounding said dies when said dies are bonded to said first sides of said second layers.
16. A package as claimed in claim 15, wherein said element is ceramic.
17. A package as claimed in claim 16, wherein said element comprises beryllia ceramic.
18. A package as claimed in claim 1, substantially as hereinbefore described with reference to and as shown in Figures 3,4 of the accompanying drawings.
19. A package as claimed in claim 1, substantially as hereinbefore described with reference to and as shown in Figures 5,6 of the accompanying drawings.
20. A package as claimed in any one of claims 1 to 19, comprising said semiconductor dies.
21. A package as claimed in claim 20,
wherein said device is a power device.
22. A package as claimed in claim 21, wherein said device is an rf power device.
23. A package as claimed in claim 20, substantially as hereinbefore described with reference to and as shown in Figures 3,4 of the accompanying drawings.
24. A package as claimed in claim 20, substantially as hereinbefore described with reference to and as shown in Figures 5,6 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US76963777A | 1977-02-17 | 1977-02-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1599852A true GB1599852A (en) | 1981-10-07 |
Family
ID=25086071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB587878A Expired GB1599852A (en) | 1977-02-17 | 1978-02-14 | Package for holding a composite semiconductor device |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS53102674A (en) |
| DE (1) | DE2806099A1 (en) |
| FR (1) | FR2381388A1 (en) |
| GB (1) | GB1599852A (en) |
| NL (1) | NL7801658A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2308008A (en) * | 1995-12-08 | 1997-06-11 | Hewlett Packard Co | Packaging system for semiconductor components |
| US8237260B2 (en) | 2008-11-26 | 2012-08-07 | Infineon Technologies Ag | Power semiconductor module with segmented base plate |
| US9960127B2 (en) | 2016-05-18 | 2018-05-01 | Macom Technology Solutions Holdings, Inc. | High-power amplifier package |
| US10134658B2 (en) | 2016-08-10 | 2018-11-20 | Macom Technology Solutions Holdings, Inc. | High power transistors |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2511193A1 (en) * | 1981-08-07 | 1983-02-11 | Thomson Csf | Laminated support for cooling semiconductor - has three metal layers including one rigid layer to avoid bi-metallic bending with changing temp. |
| JPS5899838U (en) * | 1981-12-28 | 1983-07-07 | 富士通株式会社 | semiconductor equipment |
| US4570337A (en) * | 1982-04-19 | 1986-02-18 | Olin Corporation | Method of assembling a chip carrier |
| US4866571A (en) * | 1982-06-21 | 1989-09-12 | Olin Corporation | Semiconductor package |
| US5014159A (en) * | 1982-04-19 | 1991-05-07 | Olin Corporation | Semiconductor package |
| EP0139029A1 (en) * | 1983-10-19 | 1985-05-02 | Olin Corporation | Improved semiconductor package |
| JPS60113931A (en) * | 1983-11-25 | 1985-06-20 | Toshiba Corp | Semiconductor device |
| US4862323A (en) * | 1984-04-12 | 1989-08-29 | Olin Corporation | Chip carrier |
| FR2563379A1 (en) * | 1984-04-20 | 1985-10-25 | Artus | Assembly of semiconductor electronic devices mounted on a dissipator |
| US4853491A (en) * | 1984-10-03 | 1989-08-01 | Olin Corporation | Chip carrier |
| US4639760A (en) * | 1986-01-21 | 1987-01-27 | Motorola, Inc. | High power RF transistor assembly |
| DE3837617A1 (en) * | 1988-11-05 | 1990-05-10 | Semikron Elektronik Gmbh | SUPPORT BODY FOR THE ELECTRICALLY INSULATED ARRANGEMENT OF COMPONENTS |
| DE3837920A1 (en) * | 1988-11-09 | 1990-05-10 | Semikron Elektronik Gmbh | SEMICONDUCTOR ELEMENT |
| US5317194A (en) * | 1989-10-17 | 1994-05-31 | Kabushiki Kaisha Toshiba | Resin-sealed semiconductor device having intermediate silicon thermal dissipation means and embedded heat sink |
| DE102006011995B3 (en) * | 2006-03-16 | 2007-11-08 | Semikron Elektronik Gmbh & Co. Kg | Power semiconductor module, has base plate connected with substrate in material-coherent manner, and contact layer of substrate divided into segments for providing material-coherent connection with base plate |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3728589A (en) * | 1971-04-16 | 1973-04-17 | Rca Corp | Semiconductor assembly |
| JPS49131863U (en) * | 1973-03-10 | 1974-11-13 |
-
1978
- 1978-02-14 DE DE19782806099 patent/DE2806099A1/en not_active Withdrawn
- 1978-02-14 NL NL7801658A patent/NL7801658A/en not_active Application Discontinuation
- 1978-02-14 GB GB587878A patent/GB1599852A/en not_active Expired
- 1978-02-16 JP JP1597678A patent/JPS53102674A/en active Granted
- 1978-02-16 FR FR7804380A patent/FR2381388A1/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2308008A (en) * | 1995-12-08 | 1997-06-11 | Hewlett Packard Co | Packaging system for semiconductor components |
| GB2308008B (en) * | 1995-12-08 | 2000-11-22 | Hewlett Packard Co | Packaging system for semiconductor components |
| US8237260B2 (en) | 2008-11-26 | 2012-08-07 | Infineon Technologies Ag | Power semiconductor module with segmented base plate |
| US9960127B2 (en) | 2016-05-18 | 2018-05-01 | Macom Technology Solutions Holdings, Inc. | High-power amplifier package |
| US10700023B2 (en) | 2016-05-18 | 2020-06-30 | Macom Technology Solutions Holdings, Inc. | High-power amplifier package |
| US10134658B2 (en) | 2016-08-10 | 2018-11-20 | Macom Technology Solutions Holdings, Inc. | High power transistors |
| US11367674B2 (en) | 2016-08-10 | 2022-06-21 | Macom Technology Solutions Holdings, Inc. | High power transistors |
| US11862536B2 (en) | 2016-08-10 | 2024-01-02 | Macom Technology Solutions Holdings, Inc. | High power transistors |
Also Published As
| Publication number | Publication date |
|---|---|
| NL7801658A (en) | 1978-08-21 |
| DE2806099A1 (en) | 1978-08-24 |
| JPS53102674A (en) | 1978-09-07 |
| JPS6128219B2 (en) | 1986-06-28 |
| FR2381388A1 (en) | 1978-09-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PCNP | Patent ceased through non-payment of renewal fee |