GB1599432A - Programmable control - Google Patents

Abstract

The programmable controller contains an oscillator (1), a step counter (2), a command memory (3), a computer (9) and peripheral devices (5, 6, 7) for outputs and timers. The oscillator (1) activates the step counter (2) with n outputs, corresponding to 2<n> steps. The step counter then serially controls the command memory (3) with n inputs which comprises 2<n> words. The data memory (8), timer, counter, REGISTER (6) and inputs (5) are connected on their output sides to the DATA-IN line of the computer (9), the data memory (8), outputs, timer, counter and register being connected on their input sides to the DATA-OUT line of the computer. The controller intended for controlling industrial processes operates quickly, is inexpensive and requires few memory spaces. <IMAGE>

Description

(54) PROGRAMMABLE CONTROL (71) We, WALTER KLASCHKA GMBH & Co., a Kommanditgesellschaft, of 1 Steineggerstrasse, Tiefenbronn - Lehningen, Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The invention concerns a programmable control (PC) with an oscillator, with a step counter, with an instruction memory. and with a logic unit in addition to inputs, outputs, and optionally a timing pulse generator, counter, register or data store.

An excellent description of the latest state of the art is given in VDI Report 263 "Pro- grammable Controls (PC)", Association of German Engineers.

Known programmable controls work slowly, need many storage positions, can work through logic linkages only slowly and are costly. They are liable to faults and are difficult to extend.

The present invention provides a programmable control which seeks to avoid all of these disadvantages.

According to the present invention there is provided a programmable control including an oscillator for triggering a step counter to provide an output therefrom corresponding to 2n steps, where n is an integer, to trigger an instruction memory having n addressing inputs, which memory contains 2n words each of a predetermined word length for selection in dependence on the step counter output, each selected word including an instruction for a logic unit, and address information; said logic unit having a single bit data input, a single bit data output and an instruction input fc providing one of a plurality of logic operations on data received thereby in dependence on the instruction received from said memory; and a plurality of inputs and outputs selectable in dependence on the address information from said memory for connection to the data input and data output respectively of said logic unit.

While the value of n may be any integer, the invention is of particular advantage when n is not lower than 7, preferably 12 or 16.

If the processor part, consisting of a control unit and a logic unit in a programmable control of this sort, is compared with a present-day commercially available microprocessor, with which the majority of programmable control devices (PC) are constructed at the present time, the following differences become apparent: There are microprocessors with 4bit, 8-bit or 16-bit handling (processing). The control according to the invention, however, only needs a 1-bit handling. Compared with this l-bit a microprocessor operates very wastefully.

The second difference lies in the logic unit. The logic unit of a microprocessor is constructed as an ALU (arithmetic and logic unit). The logic unit of the invention according to British Patent No. 1,549,155 is, however, only an LU (logic unit), i.e. that invention uses no kind of arithmetic. A disadvantage in the arithmetic unit of a microprocessor is that it has a high intelligence in arithmetic and a very low intelligence in logic. In such an arithmetic unit it has only the possibilities of working in the alternatives AND, OR or EXCLUSIVE OR. In no way, however, can the other circuit possibilities be worked through directly serially, as can be done with that invention. In that invention on the other hand a very high degree of intelligence has been realized in the logic, i.e. in the logic linkages. Any desired depth or width of linkage can be worked through with only 9 instructions.

Thirdly in the case of microprocessors linkages can be worked through only with several commands, besides which each command consists of several cycles. On the first command the microprocessor usually extracts the information from the periphery (fetch command) and deposits the information, e.g. in the internal accumulator.

With a second command the actual calculation process takes place in the logic unit after which the storage, e.g. in a further register, is effected. Since in addition for each command several cycles are necessary, the microprocessor becomes slow for linkages, i.e. it needs several commands times several cycles for one linkage.

The control according to the invention however effects processing of a linkage with only one command in only one cycle.

Thus the control according to the invention is very rapid. If the invention is put together in such a way that it is exactly equal in speed to the known processqrs, then the control becomes cheap, since in this case no costly driver stages are needed such as before and after the control store, before and after the inputs and outputs, and before and after the data store, in order to make the control fast, which is necessary in the case of the usual type of microprocessor. Since there is now time for working through the linkages, there is in addition no need for jump instructions in order to shorten the work-through time, as is usual with microprocessors. In this way further registers in the processor are dispensed with.

A fourth difference consists in the fact that a microprocessor needs a complicated machine language with more than ten instructions. This leads in the first place to an 8-bit wide command field for the instructions and secondly to a compiler or assembler for the translation of the application - oriented "linkage language" into the machine language of the microprocessor.

In the invention this is not necessary.

There is only a simple machine language with only nine instructions and therefore a 4-bit wide instruction field is sufficient.

Apart from this the invention can work with an application-oriented linkage language, which is the same as the machine language, and in which the hexadecimal counting system is used, which is favourable for the 4-bit subdivision. Assembler or compiler are not necessary.

A fifth difference between a microprocessor and the invention lies in the store position requirement. As stated above, more than one machine command is necessary for a linkage, hence also more than one instruction memory position, while the invention needs only one instruction memory position for each linkage. In addition, on account of the lack of commands for logic linkages (only AND, OR, EXCLUSIVE OR) a PC with a microprocessor usually needs supplementary interim store positions in the instruction memory and in the data stode, in order to be able to work through the circuit plans. This results in many more store positions. In the programmable control according to the invention only the smallest possible number of store positions is required, i.e. only one instruction memory position per linkage. In this way the construction of the instruction memory and also of the data store is especially economical. The invention can dispense with complicated manoeuvres such as for example to execute jump commands. The invention dispenses with such commands and therefore has an easily understandable cheap arrangement of the control unit.

The invention will now be described with the aid of a constructional example. A 250kHz oscillator is provided as in FIGURE 1, which triggers a step-counter with 12 outputs. 212 yields 4096 steps. A step counter with twelve outputs is chosen if 4096 ("4k") steps are sufficient. It is made greater or smaller if more or fewer steps are needed. For example a step counter with 16 outputs yields 216=65,536 ("65k") steps, which is far more than sufficient for the most sophisticated control system.

To each step is allotted an instruction memory position with a 16-bit word length.

Since the commercially available instruction memories already have decoders built in, it is sufficient to connect the outputs of the step counter with the inputs of the instruction memory. The size of the step counter and the size of the instruction memory are adjusted to suit the control problem as the case demands. For small control equipments only a few hundred steps will be required, for larger ones on the other hand, a few thousand.

In the type of construction with a step counter with 12 outputs an instruction memory with 4 k bytes is used and each byte consists of a word of length 16 bits.

In the centre of Figure 1 is stated how these words are organized: the first 4 bits serve as an instruction for the logic unit.

The next 4 bits give the address destination.

the next 4 bits give the address column.

and the last 4 bits give the address line, the inputs and outputs, for example, being arranged in a number of columns and lines.

Where the inputs and outputs are arranged only in columns, then a word length of only 12 bits is required.

If a step counter with 16 outputs is used the instruction memory is then organized in such a way that it has 65 k bytes and each byte consists again of a word of 16 bits. The step counter has then 16 outputs, which yields cos,536 steps. This corresponds roughly to 65 k.

The invention operates preferably in the region where n is greater than 12.

The connection of the control unit with the peripheral components (inputs,-timing pulse generators, counters, registers, outputs) is clearly shown in Figure 1 and need not be described.

The logic unit is constructed as shown in British Patent No. 1,549,155.

Figure 2 shows the cyclic working out of the commands of the programmable control according to the invention. In this case the number of steps is from 000 to FFF which is equivalent to 0 to 4095.

The invention makes use of the hexadecimal notation. By this means the construction and the understanding of the control are considerably simplified.

FIGURE 3 shows the relationship between binary, decimal and hexadecimal numbers. The hexadecimal notation uses in place of the numbers 0 to 9 of the decimal system the numbers 0 to 15. In place of the two-digit numbers 10 to 15, however, the letters A to F of the alphabet are used. By this artificial device only one digit need be used in the hexadecimal system. In this way the representation of numbers is considerably simplified. For example 15=F, 255=FF, 4095=FFF, etc.

Not only the steps, however, but also every command is inserted hexadecimally.

As was explained at the outset, each command has a word length of 16 bits=4x4 bits=4 digits in hexadecimal notation.

FIGURE 4 shows the three digits of the steps, built up hexadecimally, as well as the hexadecimal build-up of the commands, organized according to an instruction for the logic unit and an address, where the address in turn splits up into destination, column and line.

Inspection of FIGURES 2 and 4 shows the fundamental make-up of the programming language with the aid of a command.

On the left the 3-digit steps can be recognized, and on the right the 4-digit commands.

As already stated in the introduction and also described in British Patent 1,549,155, 9 instructions are suffcient. FIGURE 5 shows the relationship between instructions (first command digit) and hexadecimal numbers. By allotting the letter "A" to the instruction "and invert", a direct relationship is obtained through the letters "a" and "A", and by allotting the letter "C" to the instruction "connect invert", a relationship is likewise obtained through the letters "c" and "C ". This can be carried still further if the letter "B " is allotted to the instruction "begin invert".

The working of the control will now be explained further by means of an example: a command is first invoked and this command gives a calculation instruction which can be one of nine possible instructions. At the same time the address of an allotted input or output link is invoked.

The link invoked gives its data information through the DATA-IN line to the logic unit or takes data information from the logic unit through the DATA-OUT line to one of the outputs. The outputs can be not only the outputs shown in FIGURE 1 but also the timing pulse generator, counter and register as well as the data store also shown there. This l-bit information is processed in the logic unit, and in a single cycle. The control group of FIGURE 6 is now to be worked through. The start is at step 000 with the command 1 B 00, where "1 "=" start". We proceed then through step 001 according to the specification from left to right and from top to bottom. The command 4B16 is received, in which the digit "4" stands for connect, so that direct connection is made for B16. The next step is 002 in which the command BD02 is received so that "return invert" is operated on D02. Thereafter in step 003 (command CB7A) "connect invert" is operated on B7A and finally the command sentence is completed in step 004 with the instruction " out " for D 02, i.e. the command 5 D02.

As can be seen the application-oriented linkage language is identical with the machine language.

Fundamentally the letter B is used for input destinations and the letter D for output destinations, which is a continuation of the designation system in force hitherto, in which B also was used for positioning elements and for input switching elements and D for internal contractors. This is readily made possible by the hexadecimal notation.

FIGURE 7 shows the allotment of the destinations to the individual units such as the input and output units in FIGURE 1.

A unit has 128 inputs or outputs arranged in 16 columns of 8 lines. The top two units are necessary if 256 inputs!outputs are required. With the six additional units a maximum total of 1024 inputs 1 outputs is obtained. On the right-hand side of FIGURE 7 the destinations allotted according to the case, B, D; A, C; 1, 4; 2, 5, are given.

WHAT WE CLAIM IS: 1. A programmable control including an oscillator for triggering a step counter to provide an output therefrom corresponding to 2n steps, where n is an integer, to trigger an instruction memory having n addressing inputs, which memory contains 2n words each of a predetermined word length for selection in dependence on the step counter output, each selected word including an instruction for a logic unit, and address information; said logic unit having a single bit data input, a single bit data output and an instruction input for providing one of a plurality of logic operations on data received thereby in dependence on the instruction received from said memory; and a plurality of inputs and outputs selectable in dependence on the address information

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (9)

**WARNING** start of CLMS field may overlap end of DESC **. in British Patent No. 1,549,155. Figure 2 shows the cyclic working out of the commands of the programmable control according to the invention. In this case the number of steps is from 000 to FFF which is equivalent to 0 to 4095. The invention makes use of the hexadecimal notation. By this means the construction and the understanding of the control are considerably simplified. FIGURE 3 shows the relationship between binary, decimal and hexadecimal numbers. The hexadecimal notation uses in place of the numbers 0 to 9 of the decimal system the numbers 0 to 15. In place of the two-digit numbers 10 to 15, however, the letters A to F of the alphabet are used. By this artificial device only one digit need be used in the hexadecimal system. In this way the representation of numbers is considerably simplified. For example 15=F, 255=FF, 4095=FFF, etc. Not only the steps, however, but also every command is inserted hexadecimally. As was explained at the outset, each command has a word length of 16 bits=4x4 bits=4 digits in hexadecimal notation. FIGURE 4 shows the three digits of the steps, built up hexadecimally, as well as the hexadecimal build-up of the commands, organized according to an instruction for the logic unit and an address, where the address in turn splits up into destination, column and line. Inspection of FIGURES 2 and 4 shows the fundamental make-up of the programming language with the aid of a command. On the left the 3-digit steps can be recognized, and on the right the 4-digit commands. As already stated in the introduction and also described in British Patent 1,549,155, 9 instructions are suffcient. FIGURE 5 shows the relationship between instructions (first command digit) and hexadecimal numbers. By allotting the letter "A" to the instruction "and invert", a direct relationship is obtained through the letters "a" and "A", and by allotting the letter "C" to the instruction "connect invert", a relationship is likewise obtained through the letters "c" and "C ". This can be carried still further if the letter "B " is allotted to the instruction "begin invert". The working of the control will now be explained further by means of an example: a command is first invoked and this command gives a calculation instruction which can be one of nine possible instructions. At the same time the address of an allotted input or output link is invoked. The link invoked gives its data information through the DATA-IN line to the logic unit or takes data information from the logic unit through the DATA-OUT line to one of the outputs. The outputs can be not only the outputs shown in FIGURE 1 but also the timing pulse generator, counter and register as well as the data store also shown there. This l-bit information is processed in the logic unit, and in a single cycle. The control group of FIGURE 6 is now to be worked through. The start is at step 000 with the command 1 B 00, where "1 "=" start". We proceed then through step 001 according to the specification from left to right and from top to bottom. The command 4B16 is received, in which the digit "4" stands for connect, so that direct connection is made for B16. The next step is 002 in which the command BD02 is received so that "return invert" is operated on D02. Thereafter in step 003 (command CB7A) "connect invert" is operated on B7A and finally the command sentence is completed in step 004 with the instruction " out " for D 02, i.e. the command 5 D02. As can be seen the application-oriented linkage language is identical with the machine language. Fundamentally the letter B is used for input destinations and the letter D for output destinations, which is a continuation of the designation system in force hitherto, in which B also was used for positioning elements and for input switching elements and D for internal contractors. This is readily made possible by the hexadecimal notation. FIGURE 7 shows the allotment of the destinations to the individual units such as the input and output units in FIGURE 1. A unit has 128 inputs or outputs arranged in 16 columns of 8 lines. The top two units are necessary if 256 inputs!outputs are required. With the six additional units a maximum total of 1024 inputs 1 outputs is obtained. On the right-hand side of FIGURE 7 the destinations allotted according to the case, B, D; A, C; 1, 4; 2, 5, are given. WHAT WE CLAIM IS:

1. A programmable control including an oscillator for triggering a step counter to provide an output therefrom corresponding to 2n steps, where n is an integer, to trigger an instruction memory having n addressing inputs, which memory contains 2n words each of a predetermined word length for selection in dependence on the step counter output, each selected word including an instruction for a logic unit, and address information; said logic unit having a single bit data input, a single bit data output and an instruction input for providing one of a plurality of logic operations on data received thereby in dependence on the instruction received from said memory; and a plurality of inputs and outputs selectable in dependence on the address information

from said memory for connection to the data input and data output respectively of said logic unit.

2. A control as claimed in claim 1, wherein a pulse generator, counter, register or data store is provided for connection to the data input and output of said logic unit in dependence on addressing information made available from said memory.

3. A control as claimed in claim 1 or 2, wherein the instruction memory has a word length of 12 bits comprising four bits for the logic unit instruction, four bits for the address destination and four bits for the address column.

4. control as claimed in claim 1 or 2, wherein the instruction memory has a word length of 16 bits, comprising four bits for the logic unit instruction, four bits for the address destination, four bits for the address column and four bits for the address line.

5. A control as claimed in any one of claims 1 to 4, wherein the step counter is adapted to provide an output capability of n being equal to 12 or 16.

6. A control as claimed in any one of claims 1 to 5, wherein the machine language is at the same time the programming language.

7. A control as claimed in any one of claims 1 to 6, wherein a linkage is worked through in only one command step and in only one cycle of the sep counter.

8. A programmable control as claimed in claim 1, substantially as hereinbefore described.

9. A programmable control substantially as described herein with reference to the accompanying drawings.