DD232622A3 - CIRCUIT ARRANGEMENT FOR A MEMORY PROGRAMMABLE PROCESS CONTROL - Google Patents

Abstract

Circuit arrangement for a programmable logic controller, in particular for use in computer-controlled machining processes for the treatment of input and output information. By the invention, the processing speed should be increased in such controls. For this purpose, a circuit arrangement for programmable controllers is to be created by the basic structure is changed so that simple and quickly provided information to be processed in a shorter cycle time. To solve this problem, a second linkage controller and a switchover device are added to the input and output buffer memory, link controller, memory and sequencer assembly. The second linkage controller is connected to the inputs provided for processing simple and fast information and is called via masking ports by the first linkage controller. The switching means alternately switches the outputs of the first and second linkage controllers to the output buffer memory. The second join controller is activated by a clock center in shorter clock cycles than the first join controller from the scheduler. figure

Description

Ludwig Bachmann Dipl.-Ph.

Albrecht Donner Dipl.-Ing.

Rüdiger Haufert Dipl.-Ing.

Wolfgang Hoffmann Dipl.-Ing.

Bernd Hunger i Dipl.-Ing.

Harald Kessler Dr.-Ing.

Title of the invention

Circuit arrangement for a storable programmable process control

Field of application of the invention

The invention relates to the field of electronic programmable logic controllers, in particular to the application in computer-controlled Bearbeitungsaprozesaen for handling the input and output data.

Characteristic of the known technical solutions

It is known to use programmable logic controllers for processing and processing. In DE-OS 27 43 176 a connection programmable controller with logical Punktionabauateinen is described which has a matrix-like arrangement of the logic function blocks and a programmable by decision tables three-dimensional connection matrix.

In DE-OS 27 18 122 a programmable controller with an oacillator, a pedometer, an instruction booker, an arithmetic unit and input and Auagaberegiatern is considered. The calculator used in this process is characterized by its simplicity.

However, these controls are based on the fact that all information is treated and processed in the same way, so that the same time is required for each cycle. The duration of the processing azykluaaea is therefore always the same regardless of the information content.

Object of the invention

The invention aich daa goal to increase the processing speed in programmable controllers and thus to expand their application options.

Weaen the invention

The invention has for its object to provide a circuit arrangement for programmable controllers, which improves the basic structure aua input and Ausgabepufferapeicher, linking hardware, Arbeitaapeieher and sequencer so that simple and fast to be netted information to be processed in a shorter cycle time.

According to the invention, this object is achieved by connecting a second linkage to daa linkage via masking adapters on which input buffers are connected, and the outputs of the second linkage are connected via a switching device whose second inputs are connected to the equivalent outputs of the first linkage , on the output

Bufferapeicher led aind _r and that one, compared to the expiration work higher-frequency, clock center for calling with the second logic operation and the switching device connected and for interruption with the expiration works iat ·

Between the clock cycles provided by the expiration counterclockwork, an interruption signal is sent to the expiry station by the central station. Thus, the daa erate link ad network is disabled. Daa second linkage adopters the incoming input information, processes the same when called by daa corresponding Maakierungaaignal by simple logical operations and provides the appropriate Auagangssignale ready. If input signal changes after activation by the expiration mechanism are recognized by the first linkage converter, their processing is done by them themselves, without the use of the second linkage mechanism. The Auagangaaignale reach over the Umachalteinrichtung on the Auagabepufferspeicher.

Auaführungabeispiel

The invention should be explained in more detail by way of example with reference to an exemplary embodiment. In the accompanying drawing iat daa Blockachaltbild shown.

A expiration mechanism AS is connected to an input buffer EP, an aggregate buffer AP, and a first link converter SE 1 to which a processor AA Z angachloaaen iat is connected. Daa Ablaufateuerwerk AS in addition to these Auagangsanachlüaaen still an interrupt input via the ea connected to a Taktateuerwerk T iat. The clock controller T iat for activation with a second logic operation SE 2, a switching

device S and the output buffer AP connected. Certain inputs E0 to EK of the input buffer memory EP, which are provided for simple operations and fast switching operations, are connected to the second logic controller SE 2. The remaining inputs EK + 1 to EL are routed via the input buffer memory EP only to the first linkage rate SE 1. The outputs AO to AK of the second logic controller SE 2 are routed via the switching device S to the output buffer memory AP. The first link converter SE 1 is connected to the second logic controller SE 2 via the main logic controller MO to MK. The first logic controller SE 1 has the outputs AO "to AK", dea second logic controller SE 2, equivalent outputs AO 'to AK ¹ , which are connected to the mating contacts of the switching device S. For the punctures to be processed only by the first logic operation SE 1, the outputs AK + 1 'to Aiii ^{1 are} provided which are routed via the output buffer memory AP to the outputs AK + 1 to AM.

The sequence control AS activates sequentially the input buffer EP, the logic controller SE 1 and the Auagabebufferspeicher AP in a cyclic sequence. As a result, the signals present at the inputs E0 to EL are taken over into the input buffer memory EP, then processed by the linking network SE 1 in conjunction with the main memory ZP and output to the output buffer memory AP and the masking signals MO to MK to the second logic controller SE 2.

The clock center T gives at its outputs signals with much shorter cycle time for inactivation of the flow control unit AS and for continuous activation of the

222 11

second linkage processing unit SS 2, the Umacbalteinrichtung S and the Auagabebufferapeichera AP. The Maakierungasignale MO bia MK call depending on the Eingangaaignalen at the inputs EK + 1 bia EL simple logiache shortcuts in the second link control SE 2. If a signal is present at one of the inputs EO bia EK, then the logic operation called by the masking signal MO bia MK is filtered through in the same clock cycle and an Auaganga signal is viewed at its output AO "bia AK". The switching device S is geachaltet on the Auagänge of the second linkage SE 2 and daa Auagangaaignal is taken over by a signal from the clock center T in the Auagabebufferapeicher AP. At the corresponding output AO bia AK dea Auagabepufferapeichera AP is then daa signal to Daa causes a switching action in the process to be controlled. During the expiration of the clock cycles, the clock center T and the expiration controller AS are locked against each other. If a Taktateuerzyklua the sequencer AS and ea signals are at the inputs EO to EK, ao they are taken into the input buffer Eiche EP, processed by the eraten link 33tewerk SE 1 as well as at the inputs EK + 1 to E 2 pending signals and to issued to the auctions AO ¹ bia AK '. During this process, the switching device S is switched so that the outputs AO * to AK ^{f are} connected to the Auagabebufferapeicher AP and the outputs AO "to AK" of the second logic control circuit SE 2 are turned off. The signals output at the openings AO ¹ to AK ¹ are then transferred to the Auagabepufferspeicher AP and the corresponding switching operations are triggered. Thereafter, clock cycles of the clock center T, in which simple and quickly required information is processed and provided by the second logic controller SE 2, and clock cycles of the sequential control system AS again alternate.

Claims (1)

222 sl Erfindungaanapruch Scbaltungaanordnung for a Programmable Programmable Prozeßateuerung with an input and an Auagabebufferapeicher, a linkage seed, a Arbeitaapeicher and expiration with a clock center, characterized in that daa link ungaateuerwerk (SE 1) Maakierungaanachlüaae (MO bia MK) a Zweitea linkaateuerwerk (SE 2 ), on which there are tuned inputs of the input bufferape (EP), and that the outputs (AO "Ma AK") of the second linkage (SE 2) are connected via a switching device (S) whose second inputs are connected to the equivalent paths (AO 'bia AK ¹ ) dea the first Linkaateuerwerkea (SE 1) aind connected to the Auagabebufferapeicher (AP) aind, and that compared to the Ablaufateuerwerk (AS) hochfrequentere, clock center (T) for calling with the second linkaa (SE 2) and the switching device (S) and the interruption with the expiration mechanism (AS) connected iat. - For this a sheet drawing -