GB1599294A

GB1599294A - Analogue-to-digital converters

Info

Publication number: GB1599294A
Application number: GB25744/77A
Authority: GB
Original assignee: Solartron Electronic Group Ltd
Current assignee: Gemalto Terminals Ltd
Priority date: 1977-06-20
Filing date: 1977-06-20
Publication date: 1981-09-30

Description

(54) ANALOGUE-TO DIGITAL CONVERTERS (71) We, THE SOLARTRON ELECTRONIC GROUP LIMITED, a British Company of Victoria Road, Farnborough, Hampshire GU14 7PW. do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to analogue-to-digital converters and particularly to mark-space analogue-to-digital converters.

One of the types of analogue-to-digital converter which can be used in digital voltmeters is the bipolar mark-space analogue-to-digital converter, two forms of which are described in our UK Patent Specification No. 1 434 414 and in our copending patent application No.

25745/77, Serial No. 1599295 and in which the analogue input signal to be converted is continuously applied to an integrator, whose output is applied to one input of each of the two two-input level detectors. Each level detector compares the output of the integrator with a respective detector level applied to its other input and a periodic signal is superimposed on the output of the integrator. The detector levels are equal in magnitude but opposite in sense to one another, and whenever the signal at one input of either level detector has the same sense as and greater absolute magnitude than the detector level at the other input, the output of that level detector changes from a first state to a second state.

The outputs of the level detectors, when in their second states, cause the application of respective reference signals, equal in magnitude but opposite in sense, to the input of the integrator, the reference signal applied by each level detector having the same polarity as the detector level applied to that level detector, and therefore opposite polarity to any integrator input signal which causes a change in state of the output of the level detector.

Equilibrium is reached when the mean input to the integrator, due to the analogue signal and the two reference signals, is zero. In the converter of specification No. 1 434 414 one reference signal is effectively applied, whereas in that of application no. 25745/77 Serial No.

1599295, both reference signals have to be applied. In either case, the period for which one or other is applied, or the difference in the periods for which both are applied, is dependent upon the analogue input signal magnitude, and can be measured digitally to provide a digital representation of that magnitude.

According to one aspect of this invention a mark-space analogue-to-digital converter comprises: generating means for receiving an analogue input signal to be converted to generate a mark-space signal having a mark-space ratio dependent upon the magnitude of the input signal; means for defining a conversion interval containing a plurality of cycles of said mark-space signal; a source of clock pulses; counter means responsive to said mark-space signal to count the clock pulses under the control of each cycle of the mark-space signal to derive a net count dependent upon the mark-space ratio in that cycle; and a microprocessor arranged to receive the net count of clock pulses counted during each said cycle and to aggregate said counts over the conversion interval, whereby the aggregate count produced by the microprocessor at the end of the conversion interval is a digital representation of the magnitude of the integral of the analogue input signal over the conversion interval.

Microprocessors are known devices, the nature of which will be discussed in more detail hereinafter, but the term 'microprocessor' is intended to describe the combination of a microprocessor unit (operating registers, arithmetic and logic unit and instruction decoder), memory circuitry (read-only memory and random-access memory) and interface circuits for connecting the microprocessor to a system to operate therewith.

According to another aspect of this invention there is provided a mark-space analogue-to-digital converter comprising: generating means for receiving an analogue input signal to be converted to generate at least one of first and second periodic control signals having a period dependent upon the magnitude and sense of the analogue input signal; means for defining a conversion interval containing a plurality of said control signals; a source of clock pulses; counter means responsive to said control signals to count the clock pulses in a first direction during any said first control signal and in a second direction during any said second control signal, thereby producing a net count; and a microprocessor arranged to receive the net counts of clock pulses and to aggregate said counts over the conversion interval, whereby the aggregate count produced by the microprocessor at the end of the conversion interval is a digital representation of the magnitude of the integral of the analogue input signal over the conversion interval.

The microprocessor may be arranged to control switch means for applying said analogue input signal to the generating means for the duration of one conversion interval and for applying zero input signal to the generating means for the duration of another conversion interval, and to subtract algebraically the counts received in said other conversion interval from those received in said one conversion interval, whereby to correct said digital representation for zero drift. It may be arranged to subtract the counts as aforesaid as each count is received. The said other conversion interval may occur after said one conversion interval.

In the circumstances in which a converter according to this invention is incorporated in a digital voltmeter, the microprocessor may be arranged to perform at least one of the following operations in relation to the voltmeter measurements: (a) calculation of the ratio of a measurement and a reference magnitude; (b) calculation of the logarithm of the ratio of a measurement and a reference magnitude; (c) calculation of the power dissipated by a measured voltage applied across a specified resistance; (d) comparison of a measurement with two threshold values; (e) calculation of the average of a number of measurements; calculation of the time integral of a number of measurements; (g) calculation of the variance of a number of measurements; calculation of the standard deviation of a number of measurements;; (i) calculation of the root-mean-square value of a number of measurements; (j) counting the number of measurements made from a specified time; (k) tracking time elapsed since the start of a series of measurements; (1) calculation of average of a number of measurements having values between two threshold values; (m) calculation of the time integral of a number of measurements having values between two threshold values; (n) conversion of a measurement according to a predetermined function.

A mark-space analogue-to-digital converter in accordance with this invention and of the bipolar kind, and a digital voltmeter incorporating the converter, will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block schematic circuit diagram of a typical microprocessor; Figure 2 is a simplified block schematic circuit diagram of the voltmeter, showing in particular, the microprocessor and the converter; and Figures 3 and 4 show waveforms occurring at various points in the circuit of Figure 2.

For convenience, the construction and operation of a typical microprocessor will be discussed first. Microprocessors are well known, and therefore only a brief outline need be given here.

Referring to Figure 1, a microprocessor typically has four main parts:- a microprocessor unit (MPU) 100, a read-only memory (ROM) 110, a random-access memory (RAM) 120 and an input-output unit 130. The microprocessor unit 100 itself includes a series of operations registers PC, SP, IX; two accumulators ACC A and ACC B; an arithmetic and logic unit ALU and associated condition code register CCR; an instruction register IR and instruction decoder ID; and address output buffer circuits ABC and data buffer circuits DBC. The four parts 100, 110, 120 and 130 are interconnected by three groups of conductors: a 16-line address bus 140, an 8-line data bus 150 and a control line 160.

Part of the design and assembly of the microprocessor involves writing, and storing in the ROM 110, a sequence or program of coded instructions which govern the operation of the microprocessor. These coded instructions (such as 'load a number into an accumulator', 'add', 'shift one place left' and 'complement all binary digits in a number') are stored in individual numbered locations in the ROM 110. When the number (comprising 16 binary digits) of one of these locations is presented by the MPU 100 on the address bus 140, the instruction (comprising 8 binary digits) stored in that location is provided by the ROM 110 on the data bus 150. The instruction thus extracted is effectively copied, and remains unchanged in the ROM 110 - the name 'read-only memory' indicates that its contents can only be read out, and cannot be altered by the MPU 100, for example by writing in new information.

In operation, the number of a location (for example, 1005) in the ROM 110 is held in the register PC and applied to the address bus 140, with the result that the instruction in that location 1005 is supplied via the data bus 150 to the instruction register IR. At the same time, the register PC is automatically incremented by one to 1006. The instruction decoder ID decodes the instruction, and causes the accumulators ACC A and ACC B and the arithmetic and logic unit ALU, for example, to carry out the instruction. This may involve mathematical manipulation of data, this data being stored in the RAM 120. The RAM 120 differs from the ROM 110 only in that information can be both read out of it and written into it, this latter process involving the obliteration of any data already in a numbered location into which new data is written.

If, for example, the instruction in the instruction register IR were 'add the data in RAM location x to the contents of accumulator ACC A', the instruction decoder ID would, in general terms: cause the contents of the register PC (1006) to be applied to the address bus 140, to extract the first half of the address x previously stored at location 1006 in the ROM 110 when the program was loaded into it; repeat the operation with the incremented contents of the register PC (1007) to extract the second half of the address x; apply the address thus built up in the circuits ABC to the address bus 140; send a trigger (read) signal on the control line 160 to the RAM 120 so it responds by supplying the data in location x to the data bus 150; and trigger the arithmetic and logic unit ALU to perform an additional operation between the data on the data bus 150 and data previously loaded into the accumulator ACC A. The condition code register CCR co-operates with the unit ALU in this, and the registers SP, IX are involved in other methods of storing information in and extracting information from the memories 110 and 120. These techniques are well known in the art.

The data in the location x in the RAM 120 may be the result of a previous operation of the MPU 100. Alternatively, it may have been supplied to the RAM 120 via the input-output circuit 130, from apparatus which the microprocessor is controlling, or, particularly. from a keyboard 170 by means of which data and instructions can be entered into the microprocessor manually. Again, the techniques for achieving this are well known and need not be discussed here.

The sequential operation of the various parts of the microprocessor as described above is triggered in conventional manner by timing pulses supplied by a clock 101 to the MPU 100.

Referring now to Figure 2, there is shown a digital voltmeter including an analogue-todigital converter, and the microprocessor of Figure 1 arranged to supervise logic functions in the converter and the voltmeter as a whole.

The converter is indicated generally at 1, and comprises a pair of input terminals 10, 11 to which an analogue-input signal to be converted is applied. The input terminal 10 constitutes the input of an integrating amplifier 14, which comprises a high gain differential amplifier 16 having inverting and non-inverting inputs 18, 20 respectively. An FET switch 12 and an input resistor R1 are connected in series between the input terminal 10 and the inverting input 18, and an integrating capacitor C1 is feedback-connected from the output of the amplifier 16 to the inverting input 18. The input terminal 11 and the non-inverting input 20 of the amplifier 16 are both grounded, and another FET switch 13 is connected between the junction of the switch 12 and the resistor R1, and ground.

The inverting input 18 of the amplifier 16 constitutes a summing junction, and the output of a square wave generator 22 is A.C. coupled thereto via the series combination of a capacitor C2 and a resistor R2. The square wave generator produces a square wave output at a typical frequency of 10kHz, and is connected to be driven via a divide-by-1000 frequency divider 24 by a clock pulse generator 26 having a typical operating frequency of 10MHz.

Also connected to the inverting input 18 of the amplifier 16 is one end of a resistor R3, whose other end is selectively connectable, via three transistor switches FET1, FET2 and FET3 in parallel, to a positive reference voltage source 28, ground, and a negative reference voltage source 30 respectively. Although the sources 28, 30 are opposite in polarity, their respective magnitudes + VREF, are substantially equal: typically they may be +7 volts and -7 volts respectively. Normally, one of the sources 28, 30 comprises a highly stable temperature-controlled zener diode (not shown), and the other is derived therefrom by inversion.

The output of the amplifier 16, which also constitutes the output of the integrating amplifier 14, is connected via respective resistors 32 and 34 to the base electrodes of respective NPN transistors 36 and 38. The emitter electrodes of the transistors 36 and 38 are grounded, and the base electrode of the transistor 36 is coupled to a negative voltage supply (which may conveniently be the source 30) via a resistor 40. The transistors 36 and 38 operate as level detectors, the detector level V1 for the transistor 38 being determined primarily by its base-emitter voltage for conduction, and the detector level V2 for the transistor 36 being rendered slightly higher (by about 200 millivolts) by the resistor 40.

The collector electrodes of the transistors 36 and 38 constitute the outputs of the level detectors and are respectively connected to the respective D inputs of two D-type bistable circuits 48, 50, whose respective clock inputs are both connected to the output of the clock pulse generator 26. The Q output of the bistable circuit 48 is connected to the control input (gate electrode) of the switch FET1, and the 0~output of the bistable circuit 50 is connected to the control input of the switch FET3. The Q outputs of both bistable circuits 48, 50 are connected to respective inputs of a two-input AND gate 51, whose output is connected to the control input of the switch FET2. Additionally, the Q output of the bistable circuit 48 is connected to one input 52 of a two-input AND gate 54, while the Q output of the bistable circuit 50 is connected to one input 56 of a two-input AND gate 58.The other input 60 of each of the AND gates 54, 58 is connected to the output of the clock pulse generator 26, while the outputs of the AND gates 54, 58 are respectively connected to the forward and reverse count inputs 62, 64 respectively of a reversible multi-decade BCD counter 66.

The counter 66 has a count output 68 which constitutes one input of the input-output circuit 130 of the microprocessor. One output 85 of the circuit 130 is connected to a display unit 74, which may be of the known seven-segment light-emitting diode or liquid crystal type.

The circuit 130 has three other control inputs 78-80 respectively connected to receive control input signals from the clock pulse generator 26 (which may be combined with the clock 101 in the microprocessor) the square wave generator 22, and a detect zero output of the counter 66. In addition, the circuit 130 has three other control outputs 83, 86 and 87, at which it produces respective control signals under the control of the MPU 100, as will hereinafter be described, for application to a reset input of the counter 66 and the control inputs (gate electrodes) of the FET switches 12 and 13, respectively.

In operation, and assuming the Q outputs of the bistable circuits 48, 50 are initially in their logic 0 states, the switches FET1 and FET3 are open (non-conducting) and the switch FET2 is held closed (conducting) via the AND gate 51. The square wave produced by the square wave generator 26 is integrated by the integrating amplifier 14. Since the square wave is A.C. coupled to the integrating amplifier 14 via the capacitor C2, its mean D.C.

level at the input of the resistor R2 should be zero, and its waveform is as shown in Figure 3(a). In the absence of an analogue input signal at the input terminals 10, 11, and ignoring the effects of any drift at the input of the amplifier 16, the integrating amplifier 14 therefore produces an output signal of disorted triangular waveform, symmetrically disposed about the voltages V1 and V2, as shown in Figure 3(b). The separation of the voltages V1 and V2 is relatively small compared to the amplitude of this triangular waveform, so that most of the positive half-cycle of this waveform exceeds the level V2 and most of the negative half-cycle falls below the level V1.Each time the voltage V2 is exceeded, the transistor level detector 36 produces a logic 1 output signal, which is applied to the D input of the bistable circuit 48, so that the first clock pulse to occur after the voltage V2 is crossed in the positive direction sets the Q state output of this bistable circuit to its logic 1 state. Similarly, when the output voltage produced by the integrating amplifier 14 falls below the voltage V2 (i.e.

during each negative-going flank of the triangular waveform), the output signal produced by the transistor 36 and applied to the D input of the bistable circuit 48 reverts to its logic 0 state, so that the first clock pulse to occur thereafter sets the Q output of the bistable circuit back to its logic 0 state.

The logic 1 state at the Q output of the bistable circuit 48 is effective to close the switch FET1, thus applying the positive reference voltage source 28 to the integrating amplifier 14 in opposition to the input voltage at the terminals 10 and 11. At the same time, the logic 1 state at the Q output of the bistable circuit 48 is also effective to enable the AND gate 54, thereby permitting clock pulses to be applied to, and counted in, the counter 66 throughout the duration of the application of the voltage source 28 to the integrating amplifier 14.

The transistor level detector 38 and the bistable circuit 50 operate in a similar manner to close the switch FET3 and apply the negative reference voltage source 30 to the integrating amplifier 14, whenever the output voltage of the amplifier 14 is below the voltage V1. At the same time, clock pulses are applied via the AND-gate 58 to the counter 66.

Equilibrium is reached, typically after a few cycles of the square wave from the square wave generator 26, when the mean input current (that is, net charge supplied) to the integrating amplifier 14 is zero. Each cycle of the output signal from the integrating amplifier 14 can be divided into six successive periods, indicated by Roman numerals I to VI in Figure 3(b), during which the charge supplied to the integrating amplifier 14 is as follows:: QI = (- VIN - VS - VREF) ti R1 R2 R3 Qil = ( VIN - Vs) til R1 R2 Quill = (- VIN - VS + VREF) till R1 R2 R3 QIv = (- VIN + VS + VREF) tiv R1 R2 R3 Qv = ( VIN + VS) tv R1 R2 QVI = (- VIN + Vs - VREF) tVI R1 R2 R3 where 2Vs is the peak-to-peak amplitude of the square wave from the square wave generator 26, VIN is a voltage (at present zero) to be applied to the terminals 10 and 11, and tI to tvi are the durations of the periods I to VI respectively. It can be assumed that the mean value of the charge components due to the square wave is zero, since, nominally, ti + tii + till = tlv + tv + tvi If this assumption is incorrect (for example, because the square wave does not have an exact 1:1 mark-space ratio), the effect is a zero error which is automatically compensated by the converter as will be explained hereinafter. The components due to any voltage VIN will be present for the whole period T, where T is the period of the square wave (and equal to the sum of tI to tvI). Thus, at equilibrium and assuming VIN is zero, 0 = R1 .VREF. (t+ - t~) = constant x (t+ R3 T where t+ = till + tiv and t = tI + tvI, see figure 3(b), and are the durations of the applications of the sources 28 and 30 respectively to the integrating amplifier 14.

It will be noted from figure 3(b) that the sources 28 and 30 are each applied for substantially all of a half-cycle of the square wave when there is zero input at the terminals 10 and 11. Also, during the periods I and IV, the sources 28 and 30 augment the square wave, while during the periods III and VI, they oppose it, thus varying the slope of the triangular waveform and distorting it as shown.

When an analogue input signal in the form of a negative input voltage - VIN is applied to the input terminals 10 and 11, the FET switch 12 being closed by the circuit 130, the integrating amplifier 14 integrates it to produce a positive component in the triangular waveform output signal produced thereby. This positive component increases the slope of the positive-going flanks of the triangular waveform, and decreases the slope of the negative-going flanks, thus causing the positive peaks to increase in magnitude and duration at the expense of the negative peaks, as shown in figure 3(c).

Consequently, the positive reference voltage source 28 is applied for a relatively longer time (t+ increases) and the negative reference voltage source for a relatively shorter time (t~ decreases), in proportion to the magnitude of the input voltage - VIN. At equilibrium, VIN = constant x (t+ - t~).

Thus, in order to measure the magnitude of the input voltage - VIN, the MPU 100, under the control of the program of instructions previously stored in the ROM 110, produces a start signal at the output 83 of the circuit 130, which start signal coincides with a predetermined point in a cycle of the square wave from the generator 26. In the embodiment shown in Figure 2, this predetermined point is the beginning of a cycle; however, this is not essential. This start signal resets the count in the counter 66 to zero, and the counter 66 then counts clock pulses from the AND gate 54 in a forward direction throughout the duration of each application of the source 28, and clock pulses from the AND gate 58 in a reverse direction throughout the duration of each application of the source 30.The program controlling the microprocessor is arranged so that, at the end of each pulse of the square wave from the generator 26, the microprocessor extracts the net count from the counter 66 on the count output 68 and maintains an aggregate of these counts. After each such extraction the counter 66 is reset to zero again, via the control output 83, ready to count the clock pulses driving the next application of each of the sources 28 and 30. Thus the full-house count of the counter 66 need only be large enough to accommodate the number of the clock pulses which can occur during the longest possible single application of either of the sources 28 and 30.

Under the control of its program, the microprocessor continues aggregating the counts from the counter 66 for a total of ten cycles from the square wave generator 26, this period defining a first conversion interval (see Figure 4(a)). At the end of the first conversion interval (that is, when the microprocessor has counted ten cycles of the square wave) the microprocessor opens the FET switch 12, disconnecting the input voltage VIN, and closes the FET switch 13, grounding the input of the integrating amplifier 14. The microprocessor also resets the counter 66 after one square wave cycle, to allow switching transients to settle, and then resumes aggregation of counts from the counter 66 for a second conversion interval of ten square wave cycles (see Figure 4(a)).These counts are produced in dependence upon the application of the sources 28 and 30, these sources being in turn applied in accordance with the zero input voltage to the integrating amplifier 14 resulting from the grounding of the input via the FET switch 13. Accordingly, the microprocessor program causes these counts to be subtractively aggregated with the total count carried forward from the first conversion interval. Thus, if there is any zero drift in the converter, owing to, for example, amplifier drift or departures from 1:1 in the mark-space ratio of the square wave, the corresponding small net count in the second conversion interval will be algebraically subtracted from the net count for the first conversion interval.At the end of the second conversion interval therefore, the microprocessor will have stored in the RAM 120 a number representative of the magnitude of the magnitude of the input signal VIN, but corrected for any zero drift that exists.

For a negative input signal VIN, for example, the net count at the end of the first conversion interval will be positive, since the source 28 will have been applied for a longer aggregate time than the source 30 (see Figures 3(c) and 4). If there is a small negative zero drift, for example, the source 28 will again be applied for longer than the source 30, resulting in another net surplus of clock pulses from the AND-gate 54. However, these pulses are aggregated subtractively by the microprocessor, thereby reducing the net count and compensating for the aggregation of the negative input signal with the negative zero drift which occurs during the first conversion interval.

After the second conversion interval, that is, when the microprocessor has again counted ten square-wave cycles, the final net count stored in the RAM 120 is compared, digit by digit, with a look-up table in the ROM 110 which contains all the possible digits and the corresponding patterns of energisation required for a seven-segment display to define those digits. The patterns required for each digit in the final count are temporarily stored, and then supplied by one in a multiplex mode of operation to the display unit 74 along the output 85. Thus, the circuit 130 periodically 'interrupts' the MPU 100 and requests the appropriate pattern for one digit position of the display. This pattern is supplied by the RAM 120 to the circuit 130, which energises the anodes (bars) of all the digit positions in the display in accordance with the pattern, and also energises the common, cathode electrode of only that digit position which is required to display the digit defined by that pattern. Subsequently, the process is repeated for each digit position in turn, at a rate fast enough to avoid flickering of the image presented by the display.

At the same time, the microprocessor opens the FET switch 13 and closes the FET switch 12, and resets the counter 66 again, in preparation for another conversion interval for measuring the input voltage VIN.

During the operations described above, the microprocessor receives no signal from the detect zero output of the counter 66, since this output is adapted to produce an output signal when the count in the counter 66 either goes from all zeroes to all nines in the reverse count direction or from all nines to all zeroes in the forward count direction, and this does not occur with a negative input signal VIN. Thus the final net count will be in ordinary BCD form, and is decoded directly via the look-up table in the ROM 110 to provide a display of the required zero-drift-corrected measurement. The control output 85 is then also caused by the microprocessor to supply a signal to the display unit 74 effecting the display of a negative polarity indication.While the measurement cycle described above, comprising two conversion intervals, is being repeated, the microprocessor continues to supply the display unit 74 with the digit patterns necessary for the decoded count to be displayed, until a new final count is aggregated in the microprocessor.

When an analogue input signal in the form of a positive input voltage +VIN is applied to the input terminal 10, a negative component is introduced into the triangular waveform output signal produced by the integrating amplifier 14. This negative component increases the slope of the negative-going flanks of the triangular waveform output signal, and decreases the slope of the positive-going flanks, thus causing the negative peaks of the triangular waveform signal to increase in magnitude and duration at the expense of the positive peaks, as shown in Figure 3(d). In a manner complementary to that already described with reference to negative analogue input voltages, the negative reference voltage source 30 is applied to the integrating amplifier 14 more often than is the positive source 28, in opposition to the positive input voltage at the terminals 10 and 11.

Consequently, more clock pulses are supplied via the AND gate 58 to the reverse input 64 of the counter 66 than are supplied via the AND gate 54 to the forward input 62, and there is a net negative count.

Equilibrium is reached, as already described, when the mean input current to the integrating amplifier 14 is zero, and the measurement and the zero-drift correction are performed during two successive conversion intervals, also as already described. However, this time the final count aggregated by the microprocessor is in nines complement form - the detect zero output of the counter 66, generated when the count in the counter 66 goes from all zeroes to all nines, informs the microprocessor that the count is negative. Accordingly, the microprocessor is arranged to complement the nines-complement BCD count before comparison with the look-up table in the ROM 110, and supply a signal on the output 85 to cause a positive polarity indication to be provided by the display unit 74 alongside the correctly-decoded final count.

It can be shown that, in general, the duration of the period (t+ - t~) is proportional to the integral of the input voltage VIN over any integral number of periods T of the square wave.

It will be appreciated that the magnitude of the input current to the integrating amplifier 14 due to Vs should be larger than twice that of the respective currents due to full scale positive and negative input voltages, since each reference source 28 and 30 is equal in magnitude to the full-scale voltage and may be applied simultaneously.

If desired, the output of the square wave generator 22 can be phase-locked to a line-frequency signal, typically at 50 or 60 Hz. The duration of the conversion interval can then be made very closely equal to the duration of an integral number of cycles e.g. one, of the line-frequency signal, so as to provide excellent rejection of any series mode interference at the line frequency which may be superimposed on the input voltage.

Further details of the advantages conferred by the converter shown in Figure 2, and possible modifications, are discussed in the aforementioned copending patent application.

It will be understood that the program of instructions for the microprocessor, stored in the ROM 110, provides for the various sequences of logical steps in the MPU 100 which are necessary to effect the various operations of the microprocessor described above. These logical steps would include, for example, repeatedly adding to and storing the accumulating count of clock pulses, comparing the number of square wave cycles counted with, for example, ten to determine the end of a conversion interval, comparing each digit of the final count with the look-up table in the ROM 110, supplying control signals to the input-output circuit 130 to control the FET switches 12 and 13 and the display unit 74, and adjusting the period of the conversion interval to vary the range of the measurements in accordance with manual commands entered via the keyboard 170.

In addition, the ROM 110 contains a number of routines which may be called into operation manually by commands entered via the keyboard 170. These routines cause the microprocessor to undertake calculations upon the measurements produced by the converter 1, in order to derive the values of various functions involving those measurements. The routines comprise sequences of instructions corresponding to formulae and equations defining the functions required. Thus, for example, an averaging routine would keep a running total of a series of measurements, and also count the number of measurements in the series, and then divide the total by that number to provide the desired average.This routine would in turn involve instructions for repeated extraction and incrementing of the total and the number stored in the RAM 120 as each new measurement is performed, and a division operation whenever an average is required.

Routines which can be provided are as follows: (a) calculation of the ratio Vir of a measurement V and a reference value r (which could be another measurement); (b) calculation of the logarithm of the ratio 20 (lOgloVlr) (in decibels); (c) calculation of the power V2/R dissipated by a measured voltage V applied across a specified resistance R; (d) comparison of a measurement V with two threshold values T1 and T2 - counts number of measurements V respectively above, between and below T1 and T2; (e) calculation of the average Vl + V2 +,..

n of a number n of measurements V; (f) calculation of the area (time integral) V1.otl + V2ot2 + V36g3 + . . . .Vn.5tn of a number n of measurements V; (g) calculation of the variance = = (V1 - m)2 + (V2 - m)2 + .... (Vn - m)2 n of a number n of measurements V having a mean value m; (h) calculation of the standard deviation o (see g) of a number n of measurements V having a mean value m; (i) calculation of the root-mean-square value (V12 + V22 + ... Vn2)1/21n of a number n of measurements V; (j) counting the number n of measurements made from a specified time; (k) tracking time t elapsed since the start of a series of measurements;; (l) calculation of the average (see e) of a number n of measurements V having values between two threshold values T1 and T2 (see d); (m) calculation of the area (time integral - see f) of a number n of measurements V having values between two threshold values T1 and T2 (see d); and (n) conversion of a measurement V according to a specified function, e.g. a polynomial T = aV3 + bV2 + cV + d for example for linearisation of a thermocouple output signal.

These functions are conveniently accorded a respective code number, so that each may be called into operation by pressing a first key on the keyboard 170 for programmed functions, and then the appropriate key carrying the code number of the desired function.

The program of instructions in the ROM 110 is then inspected by the microprocessor for the segment of instructions relating to that function, and the segment implemented by the microprocessor: the microprocessor continues to implement the instructions for control of the a-d conversion process, the display of results, etc., on a time-sharing basis with this segment of instructions. The segment will cause the display to request any preliminary information required, such as the limits T1 and T2 in (d), and then proceed to control the calculation and display of the value of the desired function.

The invention has been described with first (measurement) and second (zero-drift correction) conversion intervals occurring in that order, since this arrangement permits a measurement to be started accurately at any desired instant. However, the order of these conversion intervals may be reversed, if desired. Furthermore the first and second conversion intervals need not alternate; a conversion interval conversion interval for zero-drift correction could take place at regular intervals, for example every ten seconds, with the result being stored for correction of all the measurements which are made until another check of zero-drift takes place.

In the embodiment shown in Figure 2, the counter 66 may be a binary counter instead of a BCD counter, the aggregation of counts by the microprocessor then being carried out in pure binary arithmetic. In this case, the microprocessor would be programmed to convert the final count from binary to decimal for operation of the display 74.

The invention is not restricted to use in the type of mark-space converter shown in Figure 2, but is also applicable to the converter of Specification No. 1 434 414, for example.

WHAT WE CLAIM IS: 1. A mark-space analogue-to-digital converter comprising: generating means for receiving an analogue input signal to be converted to generate a mark-space signal having a mark-space ratio dependent upon the magnitude of the input signal; means for defining a conversion interval containing a plurality of cycles of said mark-space signal; a source of clock pulses; counter means responsive to said mark-space signal to count the clock pulses under the control of each cycle of the mark-space signal to derive a net count dependent upon the mark-space ratio in that cycle; and a microprocessor arranged to receive the net count of clock pulses counted during each said cycle and to aggregate said counts over the conversion interval, whereby the aggregate count produced by the microprocessor at the end of the conversion interval is a digital representation of the magnitude of the integral of the analogue input signal over the conversion interval.

2. A mark-space analogue-to-digital converter comprising: generating means for receiving an analogue input signal to be converted to generate at least one of first and second periodic control signals having a period dependent upon the magnitude and sense of the analogue input signal; means for defining a conversion interval containing a plurality of said control signals; a source of clock pulses; counter means responsive to said control signals to count the clock pulses in a first direction during any said first control signal and in a second direction during any said second control signal, thereby producing a net count; and a microprocessor arranged to receive the net counts of clock pulses and to aggregate said counts over the conversion interval, whereby the aggregate count produced by the microprocessor at the end of the conversion interval is a digital representation of the magnitude of the integral of the analogue input signal over the conversion interval.

3. A converter according to Claim 1 or Claim 2, wherein the microprocessor is arranged to control switch means for applying said analogue input signal to the generating means for the duration of one conversion interval and for applying zero input signal to the generating means for the duration of another conversion interval, and to subtract algebraically the counts received in said other conversion interval from those received in said one conversion interval, whereby to correct said digital representation for zero drift.

4. A converter according to Claim 3, wherein the microprocessor is arranged to subtract the counts as aforesaid as each count is received.

5. A converter according to any one of the preceding claims, wherein said other conversion interval occurs after said one conversion interval.

6. A digital voltmeter including a converter according to any one of the preceding claims, wherein the microprocessor is arranged to perform at least one of the following operations in relation to the voltmeter measurements: (a) calculation of the ratio of a measurement and a reference magnitude; (b) calculation of the logarithm of the ratio of a measurement and a reference magnitude; (c) calculation of the power dissipated by a measured voltage applied across a specified resistance; (d) comparison of a measurement with two threshold values; (e) calculation of the average of a number of measurements; (f) calculation of the time integral of a number of measurements; (g) calculation of the variance of a number of measurements; (h) calculation of the standard deviation of a number of measurements; ; (i) calculation of the root-mean-square value of a number of measurements;

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. measurement to be started accurately at any desired instant. However, the order of these conversion intervals may be reversed, if desired. Furthermore the first and second conversion intervals need not alternate; a conversion interval conversion interval for zero-drift correction could take place at regular intervals, for example every ten seconds, with the result being stored for correction of all the measurements which are made until another check of zero-drift takes place. In the embodiment shown in Figure 2, the counter 66 may be a binary counter instead of a BCD counter, the aggregation of counts by the microprocessor then being carried out in pure binary arithmetic. In this case, the microprocessor would be programmed to convert the final count from binary to decimal for operation of the display 74. The invention is not restricted to use in the type of mark-space converter shown in Figure 2, but is also applicable to the converter of Specification No. 1 434 414, for example. WHAT WE CLAIM IS:

1. A mark-space analogue-to-digital converter comprising: generating means for receiving an analogue input signal to be converted to generate a mark-space signal having a mark-space ratio dependent upon the magnitude of the input signal; means for defining a conversion interval containing a plurality of cycles of said mark-space signal; a source of clock pulses; counter means responsive to said mark-space signal to count the clock pulses under the control of each cycle of the mark-space signal to derive a net count dependent upon the mark-space ratio in that cycle; and a microprocessor arranged to receive the net count of clock pulses counted during each said cycle and to aggregate said counts over the conversion interval, whereby the aggregate count produced by the microprocessor at the end of the conversion interval is a digital representation of the magnitude of the integral of the analogue input signal over the conversion interval.

(j) counting the number of measurements made from a specified time; (k) tracking time elapsed since the start of a series of measurements; (l) calculation of average of a number of measurements having values between two threshold values; (m) calculation of the time integral of a number of measurements having values between two threshold values; (n) conversion of a measurement according to a predetermined function.

7. A mark-space analogue-to-digital converter substantially as hereinbefore described with reference to the accompanying drawings.