GB2219659A

GB2219659A - Loadcells

Info

Publication number: GB2219659A
Application number: GB8813621A
Authority: GB
Inventors: Andrew Merrick
Original assignee: CHRONOS RICHARDSON Ltd
Current assignee: CHRONOS RICHARDSON Ltd
Priority date: 1988-06-09
Filing date: 1988-06-09
Publication date: 1989-12-13
Also published as: GB8813621D0

Abstract

An AC exciter 16, 18, 20 for a loadcell 22 is constructed to provide an excitation waveform which pauses at a substantially zero value for a period of time sufficient for rectifier means 28 in the loadcell signal path to operate, such that small phase shifts have no effect upon the rectified loadcell signal, which therefore has negligible drift due to the electronic circuitry. The loadcell signal is supplied to an integrating A/D converter 42, 44, 46, 48 in which a reference signal is pulse-width modulated at 44 to equalise and balance the weight signal, both supplied to integrator 42. The cycle time of the pulse width modulation is synchronised with the loadcell excitation supply and the time ratio is measured by counting clock pulses until balance is achieved. The pulse width modulation is maintained after equalisation until the next clock pulse has been counted, thereby to accumulate an imbalance in the integrator 42 until equalisation occurs one clock pulse early. The over and under value counts are stored and averaged to provide a measuring resolution of less than one clock pulse per excitation cycle. <IMAGE>

Description

LOADCELLS This invention relates to excitation of loadcells and analogue-to-digital conversion in the processing of loadcell signals, such as may, for example, be used in weighing and bagging apparatus.

It is known to excite a loadcell with an AC signal, as opposed to a conventional DC signal, using a sine wave at a non-resonant frequency for the loadcell.

It is one object of the present invention to provide a novel manner of AC loadcell excitation which bvercomes disadvantages of the known techniques.

Accordingly, one aspect of the present invention is a method of AC loadcell excitation wherein each alternation of the loadcell excitation supply is arranged to pause at a substantially zero value for a period of time sufficient for rectifier means in the loadcell signal path to operate. By this means, small changes in phase shift have no effect on the value of the rectified loadcell signal and this, in turn, provides a loadcell signal which has negligible drift due to the electronic circuitry.

Also, according to said one aspect of the present invention, an AC exciter for a loadcell includes an alternating waveform generator constructed so that each alternation of the loadcell excitation supply pauses at a substantially zero value for a period of time sufficient for rectifier means in the loadcell signal path to operate.

In a preferred embodiment, loadcell excitation and signal bRr - cing apparatus included..

a clock; a digital waveform generator programmed with a waveform having a dead time as it crosses zero and operatively connected to be controlled by said clock; a digital-to-analogue converter connected to the output of the waveform generator, to provide an AC excitation supply for a loadcell; and rectifying switches in the signal path of the loadcell, the switches being operatively connected to be controlled by said clock.

In a known type of integrating A/D converter, a reference signal proportional to the loadcell excitation supply is pulse width modulated to equalise and balance an integrated weight signal, the time ratio of the pulse width modulation being an indication of the ratio between the weight signal and the reference signal and thus a measure of the applied load on the loadcell. The cycle time of the pulse width modulation is synchronized with the loadcell excitation supply and the time ratio is measured by counting clock pulses until balance is achieved. The resolution of such integrating AD converters is limited by the number of clock pulses in the pulse width modulation cycle time.

It is an object of another aspect of the present invention to improve the resolution of integrating AD converters.

According to said another aspect of the present invention, in an integrating A/D converter, means are provided to maintain the pulse width modulation after equalisation, until the next clock pulse has been counted, thereby to accumulate inbalance in the integrator until eq-âlisation occurs one clock pulse early, and further means are provided to receive and store sequential over value and under value counts and produce an average thereof. By this means, a resolution of less than one clock pulse can be obtained.

The above and other features of the present invention are illustrated, by way of example, in the drawings wherein: - Fig. 1 is a schematic block diagram of loadcell excitation and signal processing apparatus in accordance with the present invention; Figs. 2a and 2b are a circuit diagram of the apparatus of Fig. 1; and Figs. 3 and 4 are graphs of waveforms produced by various parts of the apparatus of Figs. 1 and 2.

The frequency of the AC excitation is derived from a 57.42kHz signal from a control computer, which signal is obtained by dividing a crystal-controlled microprocessor clock 10 signal (6.144MHz) by 107 in a divider 12. This signal is normally high dropping low for every 163nS every 17.4uS. This signal shown in Fig. 3a is applied to an eight stage binary counter 14. Not only does this counter divide the 57.42kHz signal by 256 to give the desired 225Hz excitation frequency, but as outputs from all the counter stages are available, it gives an ascending count from 0 to 255 every 4.44mS. This ascending count is applied to the address inputs of a bipolar PROM 16, which is programmed with the desired excitation waveform.

The output of the bipolar PROM is a digital representation of the desired excitation waveform, and is shown in Fig. 3b, where 0 is the maximum negative value, 255 is the maximum positive value, and 127/128 are close to zero output. This is converted to an analogue value by a D to A converter 18, which produces a current output proportional to the digital value applied. The current is applied to a power op-amp 20 which is capable of supplying the excitation current required by loadcell 22.

The waveform chosen for the loadcell excitation is shown in Fig. 3b to have "dead time" where it crosses zero (which is when the rectifiers in the signal amplifier path are switching) so that small changes in phase shift will have no effect on the rectified value.

The loadcell's output returns via a filter 24, which effectively removes radio frequency energy which may provide troublesome and feeds to an instrumentation amplifier 26, responsible for handling the very small signals from the loadcell.

Rectifying switches 28, controlled by the 225Hz clock from counter 14 have the effect of selecting the positive parts of the waveforms presented to them. The DC level of the signal at the rectifier output now represents the weight but has an AC component that is removed by a low-pass filter 30. The weight signal W is present at the output of filter 30.

The excitation supply is not very stable but this does not matter as A/D converter 18 operates on a ratiometric basis, so long as the value of the excitation supply is measured and applied to the A/D converter as a reference signal, precision will be maintained.

The excitation signal returns from the loadcell 22 via filter 32, to remove radio frequency energy, and thence to a buffer amplifier 34 at the input of a differential amplifier 36 from whence the upward signal is rectified by switches 38 and filtered by low pass filters 40 in the same way as previously described for the weight signal, to give a voltage reference signal V at the output of filter 40.

As the reference signal voltage is proportional to the loadcell excitation supply, the weight signal W represents the applied load as a proportion of the reference signal V.

Analogue to digital conversion of the weight signal W is obtained by pulse width modulation of the reference signal V. The time ratio of the pulse width modulation will thus indicate the ratio between the weight signal W and reference signal V and thus indicate applied load on the loadcell.

The weight signal W is applied to one input of an integrator 42. Switches 44 modulate the reference signal V from low pass filter 40 to provide a mean level equal to the weight signal W. This is applied to the other input of integrator 42; if the output of integrator 42 is to be prevented from going into saturation, the mean input levels have to be equal. The reference signal V from low pass filter 40 is also applied to a triangle wave generator 46, synchronised by the signal from binary counter 14 and the signals from the integrator 42 and triangle waveform generator 46 are fed to a comparator 48 which monitors the triangular waveform from generator 46 together with the output from inttegrator 42. When the voltage at the output integrator 42 rises above the value of the triangle waveform, then the output of the comparator 48 rises.A control computer 50 is connected to receive the output of comparator 48 and master clock pulses 10 and is programmed so that, on the next rising edge of the master clock a "ramp down" signal is generated and passed to modulating switches 44 to reverse the direction of the ramp at the output of the integrator 42. Likewise, when the output of the integrator 42 falls below the value of the triangle wave, then the output of the comparator 48 will fall and a "ramp up" signal will be generated by computer 50 and passed to modulator switches 44 to cause the integrator ramp to change direction once more. Figure 4 shows at A the pulses from counter 14, at C, the output of triangle generator 46, and Figures 4D to 41 show balance outputs from integrator 42 and comparator 48 for various weight signals W.

Control computer 50 is also programmed to count pulses of clock 10 during the "on" periods of the pulse width modulation. On each falling edge of the binary counter 14 output the count is interrupted and the count value is read.

As the cycle time of the pulse width modulation is synchronised to counter 14, which is itself is obtained by dividing master clock 10 by a given ratio, then the advance of the counter ratio since the last counter cycle interrupt represents the load on the loadcell to a resolution of binary counter pulses in master clock pulses. For example, as master clock runs at 6.144MHz and binary counter 14 runs at 225Hz, a resolution of one part in 27392 of the rated capacity of the loadcell is obtained; in practice this is a little less as a smaller overrange is allowed by using a maximum weight signal of 8 to 9 volts rather than 10 volts.

Resolution of one part in 27392 is not sufficient, especially when one considers that this relates to the whole loadcell range and the active load may account for only a quarter of the range.

Part of the function of the control computer 50 is to synchronise the changeover of the pulse width modulation to the next rising edge of the master clock 10, following changeover in the output of the comparator 48, the modulating switches being controlled by a clocked latch 52.

Thus pulse width modulation occurs in time periods which are exact multiples of the master clock period 10. As the value of this pulse width modulated signal has to balance an analogue input signal W, whose value is obviously not going to be exactly on one of the steps obtained from the pulse width modulating signal, there is always going to be some imbalance which will be accumulated in integrator 42 so that it can be corrected for by subsequent cycles.

An example helps to illustrate this effect. Assuming there is a steady input voltage weight signal to integrator 42 and that this input voltage results in an input "count", the "on" period of the pulse width modulation signal to switches 44, of 1000.75. However, the pulse width modulation signal is synchronised to counter 14 so fractions of a count won't occur. The action of the clocked latch 52 is to hold the pulse width modulation signal on until the next count i.e. until 1001. This will result in a small imbalance in the int?egrator, but the next period will probably be 1001 as well, increasing the imbalance at the integrator. Eventually the accumulating error in the integrator will cause the comparator 48 to trip "one pulse early", i.e. a count of 1000 will be recorded.For the example given, there will be a lower conversion every fourth cycle, so a sequence of conversions would typically be 1001, 1001, 1000, 1001, 1001, 1001, 1000, 1001, 1001, 1001, 1000 and so on. This is of course an ideal example. Noise on the input signal will always cause a "jitter" in conversions anyway, but clock latching action is guaranteed and, owing to the action of integrator 42 at the heart of the AD converter, this averages out to the true value. The averaging out is per:iormed by a digital filter in control computer 50. Thus a weight signal is obtained the resolution of which is not limited by the action of the AD converter but only by the accuracy of the means to average the weight counts.

Figure 2 is a circuit diagram corresponding to the schematic of Fig. 1 and wherein IC17 is a stage binary counter 14. Not only does the IC divide the 57.42kHz signal by 256 to give the desired 225Hz excitation frequency, but as outputs of all the counter stages are available, it gives an ascending count from 0 to 255 every 4.44mS. This ascending count is applied to the address inputs of a bipolar PROM IC16, which is programmed with the desired waveform.

The output of the bipolar PROM is converted to an analogue value by the D to A converter IC15 which produces at pin 4 a current output proportional to the digital value applied. This current output has a maximum value defined by the reference current applied at pin 14 and its direction is into IC15, so that the output will be bipolar, half of the reference current is subtracted via R70 and R71. Amplifier IC20 not only converts the current waveform into a voltage the amplitude which is determined by R73, but is also a power op-amp, capable of supplying the current required by the loadcell. Amplifier IC14 is another power op-amp, configured simply to give a gain of -1 and hence generate the signal for the other excitation terminal of the loadcell.By driving the loadcell excitation in "push-pull" there is very little common-mode component appearing a~ loadcell's bridge output. The excitation supply leaves the circuit via ports 23 and 11.

The load cell's output returns to the circuit via ports 24 and 12. The connector is a filter connector, which removes radio frequency energy which may prove troubles^r.

Filters formed by R46/C21 and R49/C20 (R46 and R49 being inductors), are also provided to remove RF-energy.

IC6 output pins 6 and 13 and IC5 output pin 8 are connected as a conventional triple op-amp instrumentation amplifier. IC2 output pin 7 is a unity gain inverter and two antiphase signals are applied to switches in IC7. These two switches are controlled by the 225Hz clock from IC17 so they have the effect of selecting the positive parts of the waveforms presented to them i.e. the signal is rectified.

The DC level of the signal at pins 2 and 7 of IC9 now represents the weight but has an AC component at 450Hz which is removed by two stages of low-pass filtering IC1 output pins 1 and 14. These filter stages also amplify the signal so that the signal level at IC pin 14 is 0 to 8-9 volts, representing the full range of the loadcell.

The excitation signal returns to the circuit in the loadcell via ports 25 and 13. Filtering to remove radio frequency energy is accomplished by filters in the connector and filters formed by R45/C10 and R48/C9 (again R45 and48 inductors), in an identical manner to the loadcell signal.

Amplifiers IC51 and IC57 simply act as unity gain buffers for the input of the differential amp = ~- IC5/14, the gain of which is chosen so that the mean level of the rectified output will be about 2.5V. This 2.5V signal is rectified and filtered in the same way as previously described for the weight signal, to give a 10V reference signal at the junction of R10 and Rll.

The weight signal is applied to IC3 pin 10 (switches between pins 6 and 7 of IC8 being normally closed).

Switches in IC9 (pins 3 to 2 and 14 to 15) modulate the 10V reference signal to provide a mean level equal to the weight signal, IC4 output pin 1 buffers the pulse width modulated signal to eliminate the effects of the small "on" resistance of the switches. Amplifier IC3 output pin 8 is connected as an integrator.

IC3 output pin 1 is a unity-gain inverter which derives approximately -10V from the 10V reference. These +10V and 10V signals are passed to switches IC8 pins 3 to 2 and 14 to 15, which are directly controlled by the 225Hz clock. Thus a 225Hz squarewave signal is produced at the switch output, as shown in Fig. 4B. IC3 output pint 14 is an integrator which converts this squarewave into a triangle waveform, as shown in Fig. 4C and shown dotted in Figs. 4D, 4F and 4H.

IC10 forms comparator 48.

Claims

1. A method of AC loadcell excitation wherein each alternation of the loadcell excitation supply is arranged to pause at a substantially zero value r~ o period of time sufficient for rectifier means in the lc6ce11 signal path to operate.

2. An AC exciter for a loadcell including an alternating waveform generator constructed so that each alternation of the loadcell excitation supply pauses at a substantially zero value for a period of time sufficient for rectifier means in the loadcell signal path to operate.

3. A loadcell exciter as claimed in claim 2 together with signal processing apparatus including :a clock; a digital waveform generator programmed with a waveform having a dead time as it crosses zero and operatively connected to be controlled by said clock; a digital-to-analogue converter connected to the output of the waveform generator, to provide an AC excitation supply for a loadcell; and rectifying switches in the signal path of the-loadcell, the switches being operatively connected to be controlled by said clock.

4. A loadcell exciter and sinai processing apparatus as claimed in claim 3 wherein a binary counter is connected to receive pulses from said clock and to control a programmable read only memory forming said digital waveform generator.

5. An integrating A/D converter having means to maintain the pulse width modulation after equalisation until the next clock pulse has been counted, thereby to accumulate inbalance in the integrator until equalisation occurs one clock pulse early, and further means are provided to receive and store sequential over value and under value counts and produce an average thereof.

6. A loadcell exciter and signal processing apparatus as claimed in Claim 3 or Claim 4 and having an A/D converter as claimed in Claim 5 and including:an AC weight signal rectifier:an AC loadcell excitation signal rectifier; a pulse width modulator connected to the loadcell excitation signal rectifier; an integrator connected to the weight signal rectifier and to the excitation signal rectifier; a triangle wave generator connected to the excitation signal rectifier and to be controlled by the clock; a comparator connected to the integrator and to the triangle wave generator; control means connected to the comparator and to the clock and arranged to output a control signal for the ro-lator that is synchronised with the clock and which reverses the direction of the ramp signal from the integrator in response to a signal from the comparator that the integrator ramp signal has risen above or r ' 'n below the trianale waveform generator signal and to count clock pulses during on periods of the pulse width modulation control signal; and, a latch connected between the control means and the modulator and to be controlled by the clock to delay pulse width modulation control signals until the next clock pulse.

7. A method of AC loadcell excitation substantially as described with reference to Fig. 3 of the drawings.

8. An AC loadcell exciter substantially as described with reference to or as shown by the drawings.

9. An AC converter substantially as described with reference to or as shown by the drawings.