GB1599295A - Analogue-to-digital converters - Google Patents

Description

(54) ANALOGUE-TO-DIGITAL CONVERTERS (71) We, THE SOLARTRON ELECTRONIC GROUP LIMITED, a British Company of Victoria Road, Farnborough, Hampshire GU14 7PW, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly- described in and by the following statement: This invention relates to analogue-to digital converters, and particularly to bipolar analogue-to-digital converters adapted to operate on the mark-space conversion principle.

In the form of bipolar mark-space analogue-to-digital converter described in our British Patent Specification No. 1 434 414. the analogue input signal to be converted is continuously applied to an integrator. whose output is applied to one input of each of two two-input level detectors. Each level detector compares the output of the integrator with a respective detector level applied to its other input and a periodic signal is superimposed on the output of the integrator. The detector levels are equal in magnitude but opposite in sense to one another. and whenever the signal at one input of either level detector has the same sense as and greater absolute magnitude than the detector level at the other input, the output of that level detector changes from a first state to a second state.The outputs of the level detectors when in their second states, cause the application of respective reference signals, equal in magnitude but opposite in sense, to the input of the integrator, the reference signal applied by each level detector having the same polarity as the detector level applied to that level detector, and therefore opposite polarity to any integrator input signal which causes a change in state of the output of that level detector. Equilibrium is reached when the mean input to the integrator, due to the analogue signal and the two reference signals, is zero. The period for which one or other of the reference signals has to be applied to achieve this equilibrium is dependent upon the analogue input signal magnitude, and it is possible to measure digitally the duration of this period to provide a digital representation of the magnitude of the signal.

In the converter described in Specification No. 1 434 414, the detector levels are spread apart such that, for zero analogue input signal. the periodic signal (a triangular waveform) superimposed on the integrator outpt lies wholly or substantially wholly between the levels.

Consequently, only one or other of the reference signals is applied to the integrator input for any significant period of time during each cycle of the periodic signal. Although this avoids zero offset problems. it also leads to the disadvantage that any difference in the magnitudes of the reference signals causes a difference in scale factor between measurements of positive and negative input voltages; that is, voltages of equal magnitude and opposite polarity would give measurements having different magnitudes as well as opposite signs. This leads to uncertainty in the use of the measurements, since there is no way of ascertaining which of the two different measurements is in error, so a percentage uncertainty must be assigned to both, even though one may in fact be accurate.

According to this invention there is provided a bipolar mark-space analogue-to-digital converter comprising: integrating means for receiving an analogue input signal to be converted; means for superimposing a periodic signal on the output signal produced by the integrating means: first and second level detectors connected to compare the output signal from the integrating means with first and second detector levels respectively. whereby for zero input signal the periodic signal causes the magnitude of the output signal from the integrating means to exceed the first level by crossing it in a direction away from the second level for at least a substantial fraction of one half of each cycle of the periodic signal, and to fall below the second level by crossing it in a direction away from the first level for at least a substantial fraction of the other half of each cycle of the periodic signal, and whereby analogue input signals of one polarity cause the magnitude of the output signal to exceed the first level for more than said fraction of said one half of each cycle, while analogue input signals of the other polarity cause the magnitude of the output signal to fall below the second level for more than said fraction of said other half of each cycle. the first and second level detectors being arranged to produce first and second control signals respectively when the magnitude of the output signal from the integrating means exceeds the first level and falls below the second level respectively: first and second reference signal sources of opposite polarity:: switch means responsive to the first control signal to apply one of said reference signal sources, opposite in polarity to said one polarity of the analogue input signal to the integrating means, said switch means being also responsive to the second control signal to apply the other of said reference signal sources to the integrating means; means for defining a conversion interval equal in duration to the duration of an integral number of cycles of said periodic signal; further switch means for applying said analogue input signal to the integrating means for the duration of one conversion interval and for applying zero input signal to the integrating means for the duration of another conversion interval; a source of clock pulses; and counter means for counting the clock pulses during the application of either of the reference signal sources to the integrating means, whereby the count in the counter means at the end of the one conversion interval, combined with the count at the end of the other conversion interval, is a digital representation of the magnitude of the integral of the analogue input signal over the one conversion interval. corrected for zero drift.

With this arrangement, zero stability is preserved, but the scale factors for positive and negative input signals remain equal even if one of the reference signal sources changes in magnitude. In addition, the measurement error resulting from such a change is only half that which would occur in similar circumstances with the converter described in the aforementioned British Patent Specification.

The level detectors may comprise respective transistors, in which circumstances at least one of the detector levels may be defined by the threshold voltage required to initiate conduction through the transistors.

The counter means may comprise a reversible counter, and means for causing the counter initially to count in one direction during the application of the first reference signal source and in the other direction during the application of the second reference signal source.

A bipolar mark-space analogue-to-digital converter in accordance with this invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a simplified block schematic circuit diagram of the converter; Figures 2 and 3 show waveforms occurring at various points in the circuit of Figure 1; and Figure 4 is a scale factor graph illustrating operation of the converter.

The converter shown in Figure 1 is indicated generally at 1, and comprises a pair of input terminals 10, 11 to which an analogue-input signal to be converted is applied. The input terminal 10 constitutes the input of an integrating amplifier 14, which comprises a high gain differential amplifier 16 having inverting and non-inverting inputs 18, 20 respectively. An FET switch 12 and an input resistor R1 are connected in series between the input terminal 10 and the inverting input 18, and an integrating capacitor C1 is feedback-connected from the output of the amplifier 16 to the inverting input 18. The input terminal 11 and the non-inverting input 20 of the amplifier 16 are both grounded, and another FET switch 13 is connected between the junction of the switch 12 and the resistor R1. and ground.

The inverting input 18 of the amplifier 16 constitutes a summing junction. and the output of a square wave generator 22 is A.C. coupled thereto via the series combination of a capacitor C2 and a resistor R2. The square wave generator produces a square wave output at a typical frequency of 10kHz, and is connected to be driven via a divide-by-1000 frequency divider 24 by a clock pulse generator 26 having a typical operating frequency of 10MHz.

Also connected to the inverting input 18 of the amplifier 16 is one end of a resistor R3 whose other end is selectively connectable, via three transistor switches FET1. FET2 and FET3 in parallel, to a positive reference voltage source 28. ground. and a negative reference voltage source 30 respectively. Although the sources 28. 30 are opposite in polarity. their respective magnitudes, + VREF, are substantially equal : typically they may be + 7 volts and - 7 volts respectively. Normally. one of the sources 28. 30 comprises a highly stable temperature-controlled zener diode (not shown), and the other is derived therefrom by inversion.

The output of the amplifier 16, which also constitutes the output of the integrating amplifier 14, is connected via respective resistors 32 and 34 to the base electrodes of respective NPN transistors 36 and 38. The emitter electrodes of the transistors 36 and 38 are grounded, and the base electrode of the transistor 36 is coupled to a negative voltage supply (which may conveniently be the source 30) via a resistor 40. The transistors 36 and 38 operate as level detectors, the detector level V1 for the transistor 38 being determined primarily by its base-emitter voltage for conduction, and the detector level V2 for the transistor 36 being rendered slightly higher (by about 200 millivolts) by the resistor 40.

The collector electrodes of the transistors 36 and 38 constitute the outputs of the level detectors and are respectively connected to the respective D inputs of two D-type bistable circuits 48, 50. whose respective clock inputs are both connected to the output of the clock pulse generator 26. The Q output of the bistable circuit 48 is connected to the control input (gate electrode) of the switch FET1 and the Q output of the bistable circuit 50 is connected to the control input of the switch FET3. The Q outputs of both bistable circuits 48, 50 are connected to respective inputs of a two-input AND gate 51, whose output is connected to the control input of the switch FET2.Additionally, the Q output of the bistable circuit 48 is connected to one input 52 of a two-input AND gate 54 while the Q output of the bistable circuit 50 is connected to one input 56 of a two-input AND gate 58. The other input 60 of each of the AND gates 54, 58 is connected to the output of the clock pulse generator 26, while the outputs of the AND gates 54, 58 are connected to the forward and reverse count inputs 62, 64 of a reversible multi-decade BCD counter 66, via two respective changeover switches 63 and 65. These switches 63 and 65 (which are shown as mechanical switches for convenience but may be solid-state switches) are arranged such that in a first state the outputs of the AND gates 54 and 58 drive the forward input 62 and the reverse input 64 respectively, as shown, and in the second state these connections are interchanged.

The counter 66 has a count output 68 connected via a set of transfer gates 69 to a staticiser 70. The staticiser 70 in turn is connected via a decoder 72 to a display unit 74, which may be of the known seven-segment light-emitting diode or liquid crystal type.

A sequence controller 76 has three control inputs 78-80 respectively connected to receive control input signals from the clock pulse generator 26, the square wave generator 22, and a detect zero output of the counter 66. The sequence controller 76 comprises a counter 75, which has a typical full house count of twenty-two and which is connected to be driven by the square wave applied to the control input 79 of the sequence controller 76, a first bistable circuit 77 connected to be alternately set and reset by the signal applied to the control input 80 of the sequence controller 76, a second bistable circuit 81 connected to be alternately reset and set by the count eleven and count twenty-two outputs respectively of the counter 75, and further logic circuitry (not shown) such as gates and bistable circuits arranged in a conventional manner.Additionally, the sequence controller 76 has six control outputs 82 to 87, respectively constituted by the count eleven, count one and count twenty-two outputs of the counter 75. the set output of the bistable circuit 77, and the set and reset outputs of the bistable circuit 81, at which control outputs it produces respective control signals, as will hereinafter be described, for application to hold and reset inputs of the counter 66, the transfer gates 69, the decoder 72, and the control inputs (gate electrodes) of the FET switches 12 and 13. respectively. The control output 85 of the sequence controller 76 is also connected to a polarity display input of the display unit 74, while the control output 83 is internally connected to reset the bistable circuit 77.The control outputs 86 and 87 also control the changeover switches 63 and 65, respectively causing them to adopt their first and second states.

In operation. and assuming the Q outputs of the bistable circuits 48, 50 are initially in their logic 0 states, the switches FET1 and FET3 are open (non-conducting) and the switch FET2 is held closed (conducting) via the AND gate 51. The square wave produced by the square wave generator 26 is integrated by the integrating amplifier 14, Since the square wave is A.C. coupled to the integrating amplifier 14 via the capacitor C2. its mean D.C.

level at the input of the resistor R2 should be zero, and its waveform is as shown in Figure 2(a). In the absence of an analogue input signal at the input terminals 10, 11 and ignoring the effects of any drift at the input of the amplifier 16, the integrating amplifier 14 therefore produces an output signal of distorted triangular waveform, symmetrically disposed about the voltages V1 and V2, as shown in Figure 2(b). The separation of the voltages V1 and V2 is relatively small compared to the amplitude of this triangular waveform, so that most of the positive half-cycle of this waveform exceeds the level V2 and most of the negative half-cycle falls below the level V1.Each time the voltage V2 is exceeded, the transistor level detector 36 produces a logic 1 output signal, which is applied to the D input of the bistable circuit 48, so that the first clock pulse to occur after the voltage V2 is crossed in the positive direction sets the Q output of this bistable circuit to its logic 1 state. Similarly, when the output voltage produced by the integrating amplifier 14 falls below the voltage V2 (i.e.

during each negative-going flank of the triangular waveform), the output signal produced by the transistor 36 and applied to the D input of the bistable circuit 48 reverts to its logic 0 state, so that the first clock pulse to occur thereafter sets the Q output of the bistable circuit back to its logic 0 state.

The logic 1 state at the Q output of the bistable circuit 48 is effective to close the switch FET1, thus applying the positive reference voltage source 28 to the integrating amplifier 14 in opposition to the input voltage at the terminals 10 and 11. At the same time, the logic 1 state at the Q output of the bistable circuit 48 is also effective to enable the AND gate 54, thereby permitting clock pulses to be applied to, and counted in. the counter 66 throughout the duration of the application of the voltage source 28 to the integrating amplifier 14.

The transistor level detector 38 and the bistable circuit 50 operate in a similar manner to close the switch FET3 and apply the negative reference voltage source 30 to the integrating amplifier 14, whenever the output voltage of the amplifier 14 is below the voltage V1. At the same time, clock pulses are applied via the AND-gate 58 to the counter 66.

Equilibrium is reached, typically after a few cycles of the square wave from the square wave generator 26, when the mean input current (that is, net charge supplied) to the integrating amplifier 14 is zero. Each cycle of the output signal from the integrating amplifier 14 can be divided into six successive periods, indicated by Roman numerals I to VI in Figure 2(b), during which the charge supplied to the integrating amplifier 14 is as follows:

where 2Vs is the peak-to-peak amplitude of the square wave from the square wave generator 26, VIN is a voltage (at present zero) to be applied to the terminals 10 and 11, and t1 to t"l are the durations of the periods I to VI respectively.It can be assumed that the mean value of the charge components due to the square wave is zero, since, nominally, ti + tii + tnr = tiv + tv + tvi If this assumption is incorrect (for example, because the square wave does not have an exact 1:1 mark-space ratio), the effect is a zero error which is automatically compensated by the converter as will be explained hereinafter.The components due to any voltage VIN will be present for the whole period T, where T is the period of the square wave (and equal to the sum of tI to tv). Thus, at equilibrium and assuming VIN is zero,

where te = till + tiv and t = ti + tvr, see Figure 2(b), and are the durations of the applications of the sources 28 and 30 respectively to the integrating amplifier 14.

It will be noted from Figure 2(b) that the sources 28 and 30 are each applied for substantially all of a half-cycle of the square wave when there is zero input at the terminals 10 and 11. Also, during the periods I and IV, the sources 28 and 30 augment the square wave, while during the periods III and VI. they oppose it, thus varying the slope of the triangular waveform and distorting it as shown.

When an analogue input signal in the form of a negative input voltage - VIN is applied to the input terminals 10 and 11, and the bistable circuit 81 is set, thereby closing the FET switch 12, the integrating amplifier 14 integrates it to produce a positive component in the triangular waveform output signal produced thereby. This positive component increases the slope of the positive-going flanks of the triangular waveform, and decreases the slope of the negative-going flanks, thus causing the positive peaks to increase in magnitude and duration at the expense of the negative peaks, as shown in Figure 2(c).

Consequently, the positive reference voltage source 28 is applied for a relatively longer time (t+ increases) and the negative reference voltage source for a relatively shorter time (t decreases), in proportion to the magnitude of the input voltage - VIN. At equilibrium, ViN = constant x (t+ - t~).

Thus in order to measure the magnitude of the input voltage - VIN, the sequence controller 76 produces a start signal at its output 83, which start signal is constituted by a count one output signal from the counter 75 and is therefore co-incident with a predetermined point in a cycle of the square wave from the square wave generator 26. In the embodiment of the invention shown in Figure 1, this predetermined point is the beginning of a cycle: however this is not essential. This start signal resets the count in the counter 66 to zero, and resets the bistable circuit 77 if necessary.The counter 66 then counts clock pulses from the AND gate 54 in a forward direction throughout the duration of each application of the source 28, and clock pulses from the AND gate 58 in a reverse direction throughout the duration of each application of the source 30, over a first conversion (or measurement) interval whose duration is determined by the counter 75 in the sequence controller 76. The end of the first conversion interval is indicated when the count eleven output of the counter 75 produces an output signal, which appears at the control output 82 of the sequence controller 76. Since this output signal is also co-incident with said predetermined point in, i.e. the beginning of, a cycle of the square wave, the duration of the first conversion interval is equal to an integral number of cycles, ten in the described embodiment, of the square wave (see Figure 3(a)).This output signal enables the hold input of the counter 66, temporarily preventing it from counting pulses at its inputs 62 and 64, and resets the bistable circuit 81, this circuit 81 having been in its set condituion during the first conversion interval. The resetting of the bistable circuit 81 opens the FET switch 12, disconnecting the input voltage VIN, and closes the FET switch 13, grounding the input of the integrating amplifier 14. In addition, the switches 63 and 65 are operated so that pulses are supplied by the AND gate 54 to the reverse input 64 of the counter 66, and by the AND gate 58 to the forward input 62 - that is, in the opposite sense to that which applied during the first conversion interval.

At the end of the twelfth square-wave pulse, the count eleven output ceases, and the signal on the hold input of the counter 66 disappears. The counter 66 then resumes counting clock pulses for a second conversion interval, until the count twenty-two output is produced by the counter 66, that is, for another ten pulses of the square wave (see Figure 3(a)).

During this second conversion interval, the counter 66 counts clock pulses from the AND gate 58 in the forward direction throughout the duration of each application of the source 30, and clock pulses from the AND gate 54 in the reverse direction throughout the duration of each application of the source 28. these sources being applied in accordance with the zero input voltage to the integrating amplifier 14 resulting from the grounding of the input via the FET switch 13.

Nominally, the sources 28 and 30 should be applied for equal periods during the second conversion interval (see Figures 3(c) and 3(d)), but, in practice, this may not be so, owing to, for example, amplifier drift or departures from 1:1 in the mark-space ratio of the square wave. Accordingly, at the end of the second conversion interval, there may be a small net count of clock pulses representative of the magnitude and sign of any such zero drift.

However, this small net count will have been accumulated in the counter 66 in the reverse sense to the counting which took place during the first conversion interval, by virtue of the changeover of the switches 63 and 65 at the end of the first conversion interval. Thus, at the end of the second conversion interval, the counter 66 contains a number representative of the magnitude of the input signal VIN, but corrected for any zero drift that exists.

For a negative input signal VIN, for example, the net count at the end of the first conversion interval will be positive, since the source 28 will have been applied for a longer aggregate time than the source 30 (see Figures 2(c) and 3). If there is a small negative zero drift, for example. the source 28 will again be applied for longer than the source 30, resulting in another net surplus of clock pulses from the AND-gate 54. However, these pulses are counted by the counter 66 via the switch 65 and the reverse input 64. Thus these pulses are deducted from those accumulated in the counter 66 during the first conversion interval, thereby reducing the net count and compensating for the aggregation of the negative input signal with the negative zero drift which occurs during the first conversion interval.

The count twenty-two signal which defines the end of the second conversion interval enables the transfer gates 69, and is therefore effective to strobe the final count in the counter 66 into the staticiser 70. This signal also sets the bistable circuit 81 again, thereby opening the FET switch 13 and closing the FET switch 12, and setting the switches 63 and 65 back to the positions shown in Figure 1. in preparation for another conversion interval for measuringlthe input voltage VIN.

During the operations described above, the sequence controller 76 receives no signal from the detect zero output of the counter 66, since this detect zero output is adapted to produce an output signal, when the count in the counter 66 either goes from all zeroes to all nines in the reverse count direction or from all nines to all zeroes in the forward count direction, and this does not occur with a negative input signal VIN. The bistable circuit 77 in the sequence controller 76 therefore remains in its reset state, which is arranged to set the decoder 72 to operate as a BCD-to-seven-segment decimal decoder. The decoder 72 thus decodes the count held in the staticiser 70, and the decoded count is displayed by the display unit 74 as the required zero-drift-corrected measurement.The signal at control output 85 of the sequence controller 76 additionally causes the display unit 74 to display a negative polarity indication.

The next count one output signal from the counter 75 in the sequence controller 76 constitutes a further start signal, which causes the whole measurement cycle described above (comprising two conversion intervals) to be repeated. However, the display unit 74 continues to display the decoded value of the count held in the staticiser 70 until the end of the second conversion interval, when the new value of the count in the counter 66 is strobed into the staticiser.

When an analogue input signal in the form of a positive input voltage + VIN is applied to the input terminal 10. a negative component is introduced into the triangular waveform output signal produced by the integrating amplifier 14. This negative component increases the slope of the negative-going flanks of the triangular waveform output signal, and decreases the slope of the positive-going flanks, thus causing the negative peaks of the triangular waveform output signal to increase in magnitude and duration at the expense of the positive peaks, as shown in Figure 2(d).In a manner complementary to that already described with reference to negative analogue input voltages, the negative reference voltage source 30 is applied to the integrating amplifier 14 more often than is the positive source 28, in opposition to the positive input voltage at the terminals 10 and 11.

Consequently, more clock pulses are supplied via the AND gate 58 to the reverse input 64 of the counter 66 than are supplied via the AND gate 54 to the forward input 62. and there is a net negative count.

Equilibrium is reached, as already described, when the mean input current to the integrating amplifier 14 is zero, and the measurement and the zero-drift correction are performed during two successive conversion intervals, also as already described. However, this time the final count in the counter 66 is in nines complement form. But when the count in the counter 66 goes from all zeroes to all nines, the sequence controller 76 receives a signal from the detect zero output of the counter. This signal sets the bistable circuit 77 in the sequence controller 76, which in turn sets the decoder 72 to operate as a nines-complement-BCD to seven-segment decimal decoder.This can be accomplished, for example. merely by complementing the signal at the input of the decoder 72 by means of switching circuitry, before its application to the main decoding circuitry. The correctly decoded output from the decoder is then displayed by the display unit 74, which additionally displays a positive polarity indication in response to the set signal from the bistable circuit 77, which appears at the control output 85 of the sequence controller 76.

Performing the measurement before the zero-drift correction, as described above, permits a measurement to be executed at a precisely defined point in time. Known converters have to test for zero-drift before a measurement is made, thereby introducing uncertainty into the time at which the measurement actually occurs. The converter of this invention can also provide advantages when used in. for example. a data logger for successively sampling and recording the values of a number of parameters represented by respective analogue signals. The logger would include a selector or scanner which selects each analogue signal in turn for application to the converter. After the scanner has switched to a new signal it is necessary to delay the measurement of that signal to allow switching transients to settle. With the converter described above. this switching can take place at the start of the second conversion interval, when the FET switch 12 is open and the zero-drift check is taking place. The second conversion interval thus provides the desired settling time. so that the measurement of the new signal can take place without delay at the start of the following first conversion interval. Furthermore, by only checking zero-drift immediately after each measurement, it is possible to monitor an input signal effectively continuously, without risk of interruption by an independently-triggered regular drift-correct cycle.

The reason for employing a reversible counter as the counter 66 is as follows. Consider the case of a very small input voltage having a noise signal superimposed thereon. This noise signal may cause occasional reversal of the polarity of the input voltage during the conversion interval, so that the triangular waveform output signal produced by the integrating amplifier effectively moves up and down with respect to the voltages V1 and V2 and successively trips the level detector 36 longer than the level detector 38 and vice versa.

Each time the level detector 36 is tripped, the counter 66 counts forwardly, each time the level detector 38 is tripped, the counter 66 counts in reverse, and each time the count in the counter 66 goes from all zeroes to all nines or vice versa, a signal is produced at its detect zero output. The signals at the detect zero output of the counter 66 alternately set and reset the bistable circuit 77 in the sequence controller 76, so the state of the bistable circuit 77 indicates whether the net count in the counter 66 at any instant during the conversion interval is above zero, and therefore representative of an analogue input voltage having a mean negative value up to that instant, or below zero, and therefore representative of an analogue input voltage having a mean positive value up to that instant.It will be appreciated that the state of the bistable circuit 77 at the end of the conversion interval provides the signal at the control output 85 of the sequence controller 76.

It can be shown that, in general, the duration of the period (t+ - t) is proportional to the integral of the input voltage VIN over any integral number of periods T of the square wave. It will be appreciated that the magnitude of the input current to the integrating amplifier 14 due to Vs should be larger than twice that of the respective currents due to full scale positive and negative input voltages, since each reference source 28 and 30 is equal in magnitude to the full-scale voltage and may be applied simultaneously.

If desired, the output of the square wave generator 22 can be phase-locked to a line-frequency signal, typically at 50 or 60 Hz. The duration of the conversion interval can then be made very closely equal to the duration of an integral number of cycles e.g. one, of the line-frequency signal, so as to provide excellent rejection of any series mode interference at the line frequency which may be superimposed on the input voltage.

The operation of the converter to alleviate differences in positive and negative scale factors is illustrated in Figure 4.

Referring to Figure 4, the solid line 101 illustrates the optimum measurement characteristic, with true zero and equal positive and negative scale factors. If, for example, the negative reference voltage source 30 decreases slightly in value, the extreme positive point if the characteristic in the upper right-hand quadrant can be considered as moving to the right, to the position 102, while the extreme negative point in the lower left-hand quadrant remains fixed. With the circuit described in the aforementioned Patent Specification No. 1 434 414, the measurement characteristic would become non-linear, as shown by the long-dash line 103, because of the use of separately-applied reference voltage sources.However. with the converter of Figure 1, the characteristic can 'move sideways' on the graph, to remain a straight line joining the extreme positive and negative points - the short-dash line 104 in Figure 4. The zero-drift correction procedure described earlier then operates to compensate the resulting zero error, effectively shifting the characteristic sideways to the position shown by the chain-line 105. It can be seen from Figure 4 that the resulting positive error el is only half what it would be (e2) if the characteristic 103 were operative. At the same time, an equal error e1 has been added to the negative part of the characteristic. However, with the characteristic 101/103, there is no way of distinguishing from the measurement alone which polarity is in error.Therefore, it would be necessary to treat the characteristic 101/103 as if it had an error of e7 for both polarities. In contrast, with the converter of Figure 1 (characteristic 105). each polarity has an error of only el, half the value of e2. In addition, zero stability is retained, and the converter always has equal positive and negative scale factors.

The need for circuitry described in relation to Figures 4 and 5 of Specification No. 1 434 414, for ensuring that each reference voltage source is applied for a short time in every cycle of the square wave whatever the value of the analogue input signal, is eliminated with the converter of Figure 1, since both sources are applied in every cycle as an inherent part of the operation of the circuit. In addition, the time taken for the switches FET1 and FET3 to switch on and off. as a proportion of the periods for which the sources 28 and 30 are applied, is largest at full scale reading, when one of these periods is at a minimum.Thus any errors attributable to this switching time have their greatest effect at full scale reading, when they are relatively insignificant, whereas with the earlier converter of Specification No. 1 434 414, these errors have their greatest effect at zero scale reading. when they could be much more noticeable.

In addition to eliminating the need for the circuitry described with reference to Figures 4 and 5 of Specification No. 1 434 414, it has been found that the converter of Figure 1 permits a considerable simplification and saving in cost in its associated circuitry when incorporated in, for example, a digital voltmeter. Thus, the input amplifiers and gain selectors of a voltmeter incorporating a converter as shown in Figure 1 can be made with ordinary, general-purpose operational amplifiers and field-effect transistors, instead of special low-drift and low-leakage types.

Many modifications can be made to the described embodiment of the invention. Thus, instead of connecting the square wave generator 22 to the input of the integrating amplifier 14, a summing circuit may be connected to receive the output of the integrating amplifier 14 and arranged to sum this output with a triangular waveform signal from a suitable waveform generator, the output of the summing circuit being applied to the level detectors 36, 38.

Further, the switch FET2 may be omitted if desired, in view of the fact that the input 20 of the amplifier 16 is grounded. It will be understood that the expression "grounded" in this specification merely means connected to a signal low line, or zero volt line, since it is possible for the main circuitry of the converter 1 to by fully floating. Since the conversion interval may be made as long as desired, the counter 66 may be arranged to operate in the floating point mode.

The converter may also be modified as described with reference to Figure 3 of Specification No. 1 434 414, to eliminate the need for a decoder capable of decoding nines-complement BCD to seven-segment format.

Instead of using the counter 66 to aggregate the counts in the first and second conversion intervals, these counts may be extracted and algebraically added elsewhere. For example, in the Applicants' copending patent application number 25744/77 Serial No 1599294 of the same date as the present application, a microprocessor is used to accumulate counts of clock pulses counted by a separate counter during each application of a reference voltage source.

Thus the microprocessor automatically accumulates the counts for the two conversion intervals. Alternatively, the microprocessor could store the accumulated total at the end of the first conversion interval, and then perform an additional routine to add this to the total accumulated for the second conversion interval.

The invention has been described with first (measurement) and second (zero-drift correction) conversion intervals occurring in that order, since this arrangement permits a measurement to be started accuratelv at any desired instant. However, the order of these conversion intervals may be reversed, if desired. Furthermore, the first and second conversion intervals need not alternate; a conversion interval for zero-drift correction could take place at regular intervals, for example every ten seconds, with the result being stored for correction of all the measurements which are made until another check of zero-drift takes place.

WHAT WE CLAIM IS: 1. A bipolar mark-space analogue-to-digital converter comprising: integrating means for receiving an analogue input signal to be converted; means for superimposing a periodic signal on the output signal produced by the integrating means; first and second level dectectors connected to compare the output signal from the integrating means with first and second detector levels respectively. whereby for zero input signal, the periodic signal causes the magnitude of the output signal from the integrating means to exceed the first level by crossing it in a direction away from the second level for at least a substantial fraction of one half of each cycle of the periodic signal, and to fall below the second level by crossing it in a direction away from the first level for at least a substantial fraction of the other half of each cycle of the periodic signal, and whereby analogue input signals of one polarity cause the magnitude of the output signal to exceed the first level for more than said fraction of said one half of each cycle, while analogue input signals of the other polarity cause the magnitude of the output signal to fall below the second level for more than said fraction of said other half of each cycle, the first and second level detectors being arranged to produce first and second control signals respectively when the magnitude of the output signal from the integrating means exceeds the first level and falls below the second level respectively; first and second reference signal sources of opposite polarity; switch means responsive to the first control signal to apply one of said reference signal sources, opposite in polarity to said one polarity of the analogue input signal to the integrating means, said switch means being also responsive to the second control signal to apply the other of said reference signal sources to the integrating means; means for defining a conversion interval equal in duration to the duration of an integral number of cycles of said periodic signal; ; further switch means for applying said analogue input signal to the integrating means for

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (5)

**WARNING** start of CLMS field may overlap end of DESC **. In addition to eliminating the need for the circuitry described with reference to Figures 4 and 5 of Specification No. 1 434 414, it has been found that the converter of Figure 1 permits a considerable simplification and saving in cost in its associated circuitry when incorporated in, for example, a digital voltmeter. Thus, the input amplifiers and gain selectors of a voltmeter incorporating a converter as shown in Figure 1 can be made with ordinary, general-purpose operational amplifiers and field-effect transistors, instead of special low-drift and low-leakage types. Many modifications can be made to the described embodiment of the invention. Thus, instead of connecting the square wave generator 22 to the input of the integrating amplifier 14, a summing circuit may be connected to receive the output of the integrating amplifier 14 and arranged to sum this output with a triangular waveform signal from a suitable waveform generator, the output of the summing circuit being applied to the level detectors 36, 38. Further, the switch FET2 may be omitted if desired, in view of the fact that the input 20 of the amplifier 16 is grounded. It will be understood that the expression "grounded" in this specification merely means connected to a signal low line, or zero volt line, since it is possible for the main circuitry of the converter 1 to by fully floating. Since the conversion interval may be made as long as desired, the counter 66 may be arranged to operate in the floating point mode. The converter may also be modified as described with reference to Figure 3 of Specification No. 1 434 414, to eliminate the need for a decoder capable of decoding nines-complement BCD to seven-segment format. Instead of using the counter 66 to aggregate the counts in the first and second conversion intervals, these counts may be extracted and algebraically added elsewhere. For example, in the Applicants' copending patent application number 25744/77 Serial No 1599294 of the same date as the present application, a microprocessor is used to accumulate counts of clock pulses counted by a separate counter during each application of a reference voltage source. Thus the microprocessor automatically accumulates the counts for the two conversion intervals. Alternatively, the microprocessor could store the accumulated total at the end of the first conversion interval, and then perform an additional routine to add this to the total accumulated for the second conversion interval. The invention has been described with first (measurement) and second (zero-drift correction) conversion intervals occurring in that order, since this arrangement permits a measurement to be started accuratelv at any desired instant. However, the order of these conversion intervals may be reversed, if desired. Furthermore, the first and second conversion intervals need not alternate; a conversion interval for zero-drift correction could take place at regular intervals, for example every ten seconds, with the result being stored for correction of all the measurements which are made until another check of zero-drift takes place. WHAT WE CLAIM IS:

1. A bipolar mark-space analogue-to-digital converter comprising: integrating means for receiving an analogue input signal to be converted; means for superimposing a periodic signal on the output signal produced by the integrating means; first and second level dectectors connected to compare the output signal from the integrating means with first and second detector levels respectively. whereby for zero input signal, the periodic signal causes the magnitude of the output signal from the integrating means to exceed the first level by crossing it in a direction away from the second level for at least a substantial fraction of one half of each cycle of the periodic signal, and to fall below the second level by crossing it in a direction away from the first level for at least a substantial fraction of the other half of each cycle of the periodic signal, and whereby analogue input signals of one polarity cause the magnitude of the output signal to exceed the first level for more than said fraction of said one half of each cycle, while analogue input signals of the other polarity cause the magnitude of the output signal to fall below the second level for more than said fraction of said other half of each cycle, the first and second level detectors being arranged to produce first and second control signals respectively when the magnitude of the output signal from the integrating means exceeds the first level and falls below the second level respectively; first and second reference signal sources of opposite polarity; switch means responsive to the first control signal to apply one of said reference signal sources, opposite in polarity to said one polarity of the analogue input signal to the integrating means, said switch means being also responsive to the second control signal to apply the other of said reference signal sources to the integrating means; means for defining a conversion interval equal in duration to the duration of an integral number of cycles of said periodic signal; further switch means for applying said analogue input signal to the integrating means for

the duration of one conversion interval and for applying zero input signal to the integrating means for the duration of another conversion interval; a source of clock pulses; and counter means for counting the clock pulses during the application of either of the reference signal sources to the integrating means, whereby the count in the counter means at the end of the one conversion interval, combined with the count at the end of the other conversion interval, is a digital representation of the magnitude of the integral of the analogue input signal over the one conversion interval, corrected for zero drift.

2. A converter according to Claim 1, wherein the level detectors comprise respective transistors.

3. A converter according to Claim 2, wherein at least one of the detector levels is defined by the threshold voltage required to initiate conduction through the transistors.

4. A converter according to any one of Claims 1 to 3, wherein the counter means comprises a reversible counter, and means for causing the counter initially to count in one direction during the application of the first reference signal source and in the other direction during the application of the second reference signal source.

5. An analogue-to-digital converter substantially as hereinbefore described with reference to the accompanying drawings.