GB1594239A - Electronic cash register - Google Patents

Description

(54) ELECTRONIC CASH REGISTER (71) We, CASIO COMPUTER COM PANY LIMITED, a Japanese corporation, of 6-1, 2-chome, Nishishinjuku, Shinjukuku, Tokyo, Japan, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following state ment: - The present invention relates to an electronic cash register which includes a time counting function and automatically totalizes data such as the total sales made and the item count and the like within a predetermined time.

Generally, in the electronic cash register, the value of each item sold is inputted by actuation of an entry key and then a department key of the department to which the goods sold belongs is operated. The inputted data is properly processed, assorted and accumulatively stored in memories allotted for totalizations of the sale amount and the item count for each department, the gross sale total for the day's and the sales total for each clerk. At the end of the day work, the cash register is set to a reset mode to successively print out the various data stored in the corresponding memories and then these memories are cleared. These assorted sales data will be used for management purposes. Therefore, it is preferable that the sale data are detailed and correct with brevity while as brief as possible.

Since the conventional cash register is not provided with a clock function, it can totalize only one day's sales so that the data obtained are insufficient for such the purpose. If we knew the sales made during specific time zones of the day, for example, morning, afternoon, and evening, it would be effective and useful for management purposes. Further, if the time counting function is extended to year, month, week and day, an operator can preset the time period for totalization, for example, a week, a month, every two days or the like.

Accordingly, the totalization for a period longer than a day may be automatically made, resulting in a remarkable improvement of the totalization function of the register.

In the conventional register, the operator must key the data such as year, month and day at the beginning of the day's work, for receipts issuing.

Accordingly, an object of the present invention is to provide an electronic cash register which can automatically totalize sales data within a given time zone, with proper time zones preset.

According to the present invention there is provided an electronic cash register comprising a keyboard including data input keys and time zone setting key; a central processing unit coupled to said keyboard; a memory coupled to said central processing unit and having a plurality of memory locations for storing cumulative sales accounts on a time zone basis, a time memory coupled to said central processing unit and arranged to store time zone defining data in response to the operation of the time zone setting key, a timepiece coupled to said time memory to supply current time data, and a comparator coupled to said timepiece and said time memory to compare current time data from said timepiece and time data in said time memory, in which said central processing unit includes means for writing entered data in a memory location of said memory according to the time zone determined by the result of comparison by said comparator when entry of data from said keyboard is completed.

With such a construction, if the time zone for totalization is preset, totalization of sales within the preset time zone may be effected automatically. Therefore, the sales condi tion within desired time zone may be analyzed so that more detailed materials including change of operators, supplement of goods and the like may be recorded which are useful for stock control and other management purposes.

Further, if the time counting function is extended to include the month and day, date printing may be effected when receipts are issued without the need for presetting the date data.

Other features and advantages of the present invention will be apparent from the following description taken in connection with the accompanying drawings, in which: Figure I shows a keyboard of an electronic cash register; Figures 2A and 2B cooperate to form a block diagram of the entire cash register; Figure 3A is a circuit diagram of a central processing unit (CPU) used in the circuit of Figure 2; Figure 3B is a circuit diagram illustrating a memory circuit and a clock circuit used in the arrangement Figure 2; Figure 4 shows a memory map of the memory circuit; Figures 5A and 5B show memory maps of the memory in the clock circuit; Figures 6A and 6B show a flow chart for illustrating the operation of the circuit in time counting; Figure 7 shows data stored in the memory in the clock circuit; Figures 8A to 8C illustrate data stored in the memory and the register during time counting; and Figures 9A and 9B schematically illustrate the operation of printing the serial number and date on a receipt.

Referring now to Figure 1 there is shown an arrangement of a keyboard 10 of an electronic cash register (ECR). In the figurc, reference numeral 11 designates a set of "amount'' keys for entering numeral values such as cost, quantity, and the like of goods, 12 a set of"department"keys for registering goods in groups, 13 a "clear entry" key for erasing numerals inputted by the amount keys 11. A set of function "keys designated by reference numeral 14, is comprised of keys representing non-add (#) for setting up the present time, void (Vo) multiplication (@), percentage (%) and (+) and (-) for indicating increase and decrease of the percentage. Reference numeral 15 designates a set of "clerk" keys for entcring the number of a person responsible for an operation. A set of transaction keys 16 is comprised of keys representing receipt (Rc), paid out (Pd), net total (NT), balance (BL), no sale (NS), credit (Cr), and charges (Ch). Reference numeral 17 designates a subtotal key for obtaining the interim result of a course of calculation. A "cash/amount tendered'key (Ca/AMT) 10 is used for issuing a receipt, for obtainings total or for giving change. A set of "time" keys 19 is used to set up required time zones Key 19a is used for setting up a service time zone.

Key 19b is used to sets up a totalization time zone. Reference 19c designates an alarm key (AL) for setting up an alarm time zone.

The x keys 19a to 19c constitute the time key 19. A control lock 20 allows selection of the modes (OFF), (Pr), (REG), (X) and (Z).

The (OFF) mode is used when the ECR is not to be used; the (Pr) mode for presetting data; the REG mode for normal registering operations; the (X) mode for a reading operation without destroying data stored; (Z) mode for executing a reset operation to clear data after the stored data is read out.

The following explanation relates to the internal construction of an electronic cash register embodying the present invention.

Reference numeral 31 is an I/O (input/ output) controller which controls the keyboard 10 and a printing section 33. The I/O controller 31 applies a sampling signal to the keyboard 10. When a key is actuated on the keyboard 10, a sampling signal is selected in response to the key actuation and is applied as a key input signal to the I/O controller 31. Upon receipt of the key input signal from the keyboard, the I/O controller 31 loads the key input signal into an input buffer register (not shown) and temporarily stores it therein. The I/O controller 31 is coupled with a central processing unit (CPU) 34. When the CPU issues a control signal of an input instruction to the I/O controller 31, the key input signal in the input buffer is read into the CPU 34. When receiving printing data from the CPU 34, the I/O controller 31 loads the printing data into an output buffer (not shown) in which it is temporarily stored therein. The printing section 33 is comprised of a receipt paper printer 36 and a detail paper printer 37. The printers 36 and 37 are provided with printing drums 38 and 39 which are coaxially arranged and have numerical characters on their respective surfaces, respectively. Receipt paper 41 and detail paper 42 are disposed close to the printing drums 38 and 39, respectively. Printing hammers are disposed adjacent the printing drums 38 and 39 with the receipt paper 41 or the detail paper 42 respectively, with ink ribbons (not shown) interposed therebetween, respectively. A printing position detecting device 44 is provided at one of the ends of the printing drum shaft to detects the printing positions of the printing drums 38 and 39 and yields detection signals as the drums turn through specified rotational angles.

The detection signals are applied to the I/O controller 31 through an amplifier 45. When the printing position detection signal and the printing data coincide, the I/O controller 31 supplies a drive signal via a driver 35 to the printing hammer confronting the printing type at the time, thereby actuating the hammer. When the printing drums 38 and 39 have revolved through by one revolution, one line printing operation is complete and the receipt paper 41 and the detail paper 42 are fed by one line. As the printing operation progresses, the receipt paper 41 is guided out of the ECR to permit the printed portion of it to be torn off, after the printing is completed. A legend such as "YOUR RECEIPT THANK YOU", for example, may be printed on the receipt paper 41. For recording the net total the same information as is printed on the receipt paper 41 is also recorded on the detail paper 42, wound on a drum 46.

A memory device 47 and a clock circuit 48 are coupled with the CPU 34. A power source 49 is coupled with both the memory device 47 and clock circuit 48 to make them to always be ready for their operations. The clock circuit 48 also is coupled with a reference frequency oscillator, for example, a crystal oscillator 50. The memory 47 and the clock circuit 48 may each be fabricated as a single chip. The CPU 34 produces a chip enable signal CE1 to specify the memory circuit 47 and another chip enable signal CE2 to specify the clock circuit 48. A read/write signal R/W from the memory 47 specifies a reading or the writing operation for the memory device 47. The clock circuit provides time data and date date which are read out by the CPU 34, if necessary. When a receipt is to be issued, the CPU reads out date information from the clock circuit 48 to cause the printing section to print the date on which the receipt is issued. The time data is used as time marking data when totalizing is to be performed over a given time zone.

The CPU 34 executes a receipt issuing operation in response to the appropriate key input signal from the keyboard. At that time the processing data is transferred as printing data to the I/O controller 31 and to a display section 24 through a display driver 51 where it is visualized made visible.

Figures 3A and 3B cooperate to illustrate the details of the CPU 34, the memory device 47, and the clock circuit 48. The CPU 34 is first described. An address circuit 61 specifies an address of in control section 62.

The control section 62 includes a microprograms to control the operations of the respective circuits, which are stored in a read only memory (ROM). The control section has output lines 63 to 66. The output line 63 provides a code generation instruction; the output line 64 a given timing signal; the output line 65 provides various instructions, for example, a register specifying signal, a transfer instruction and a digit shift instruction; the output line 66 provides signals denoting the next address in sequence in the control section. The code generating instruction from the output line 63 is transferred to a code generating circuit 67.

A timing signal from the output line 64 is transferred to a timing designating circuit 68. The instructions from the output line 65 is transferred to an instruction decoder 69.

The next address outputted to the output line 66 is transferred to the address circuit 61 for specifying the next address. A timing signal from a timing signal generator 80 provided in the CPU 34 is applied to the code generating circuit 67, the timing instruction circuit 68, and the instruction decoder 69. The code generating circuit 67 converts parallel data, consisting of 4 bits for example, provided by the control section 62 at a given time, into a serial code signal.

The output of the code generating circuit 67 is transferred through a gate circuit 70 to an addition/subtraction circuit 71 through a gate circuit 70. The timing designating circuit 68 specifies the timing of operations in the register such as digit specifying of it in accordance with the timing signal fed through the output line 64 from the control section 62. The output signals of circuit 68 are applied as enabling and disabling signals to the respective gate circuits in the CPU 34 such as a gate circuit 70, and AND circuits 72 to 75. The outputs of the AND circuits 72 to 75 are applied through the OR circuit 76 to an input/output register 78a in the register group 77. The instruction decoder 69 decodes the instruction given from the control section 62 to control the operations in the respective portions in the CPU 34, such as designation of a register in the register group 77 and gives a read/write instruction to the memory 47 and the clock circuit 48. The outputs of the timing designating circuit 68 and the instruction decoder 69 are applied as control signals to the display driver 51 and the I/O controller 31.

The register group 77 includes the X register for input/output register 78a, and other registers 78b to 78n denoted as the Y to N registers. The output of the register group 77 is coupled with an add/subtract circuit 71, through the OR gate 70. The output of the X register 78a is also applied to the AND circuit 72, through circuit 79a with one digit memory capacity. The output signal of the add/subtact circuit 71 is applied to the AND circuit 73. The key input signal from the keyboard 10 is applied via the I/O controller 31 to the AND circuit 74. Data decoded from the memory device 47 and the clock circuit 48 is applied to the AND circuit 75.

The output signals of the X to N registers 78b to 78n are applied respectively to gate circuits 81b to 81n, through respective registers 79b to 79n each with one digit memory capacity. The output signal of the add/ subtract circuit 71 is also applied to the gate circuits 81b to 81n. The outputs of the gate circuits 81b to 81n are applied to the X to N registers 78b to 78n, respectively. The output of the X register 78a is applied as display data or printing data to the display driver 51 and the I/O controller 31 and to a chip designating circuit 82. In accordance with an instruction from the control section 62, the chip designating circuit 82 reads out the chip designating data in the X register 78a and produces the chip enable signals CEl and CE2 in accordance with the register contents, thereby to designate the memory 47 or the clock circuit 48. The output of the add/subtract circuit 71 is loaded into an A (address) register 83 for addressing. Data decoded by the A register 83 is inputted to the add/subtract circuit 71 through a gate circuit 70 and is divided into two addresses; a row address RA and a column address CA. These addresses are applied to the memory 47 and the clock circuit 48, respectively. Data and carry signals outputted from the add/subtract circuit 71 are transferred to a decision circuit 84. The decision circuit 84 decides whether the data or the carry from the circuit 71 is or is not present and passes the result of the decision to the address circuit 61. At this time, the succeeding address outputted onto the output line 66 and the detection signal are logically summed so that the next address is changed.

The memory circuit 47 includes a memory unit 91, an address designating circuit 92 into which the read/write (R/W) instruction from the instruction decoder 69, and the row and column addresses from the A register 83 are loaded. The address designating circuit 92 and the gate circuit 93 are enabled by the chip enabling signal CE, given from the chip designating circuit 82.

Data read out from the memory body 91 through the gate circuit 93 is applied to the AND circuit 75 of the CPU 34, as previously stated. The output signal of the X register 78a in the CPU 34 is applied as write data to the memory unit 91, through the gate circuit 93. The memory unit 91 has a capacity of nx8, as shown in Figure 4. The columns B, to Bx are designated by the column address CA and the rows 1 to n are designated by the column address RA. The memory store 91 is divided into three regions; a first region 91A including columns B, to B4, a second region 91B including columns B5 and B,, and a third region 91C including columns B7 to B8. In the first region 91A, the 1st to 16th row addresses store the department total corresponding to the actuated department key 12. The 17th row address stores the sale total between the designated times T, and T2. The 18th row address stores the sale total between the specified times T2 and T.

The 19th row address stores the sale total within the time range between the specified times T2 and T4. The 20th row address stores the receipt total. Such a memory region will be called a time designated sale total memory region. In the second region, the item count is stored in the 1st to 16th row addresses. The item counts within the specified time zones T1 to T2, T2 to T3, and T3 to T4 are stored in the 17th to 19th row addresses, respectively. The receipt count is stored in the 20th row address. Preset unit prices in the respective departments are stored in the 1st to 16th row addresses of the third region 91C.

In Figure 3B, the clock circuit 48 is provided with a memory 100 for storing the date of the day, present time data, preset time data and the like. The memory 100 is specified by the row and column addresses RA and CA set in the address designating circuit 101 through the A register 83 in the CPU 34 and its read and write operations are specified by the R/W instruction fed from the instruction decoder 69. A control section 110 in the clock circuit 48 feeds an address code signal and a R/W instruction to the address designating circuit 101 for addressing the memory 100. The data outputted from the memory 100 is applied to a buffer register 103 via through a gate circuit 102 and also to the gate circuits 104 and 109.

The output of a buffer register 103 and a 1-second clock pulse from a pulse generating circuit 105 are applied to the gate circuit 104. The pulse generating circuit 105 operates in response to a reference signal from a crystal oscillator 50 and, in addition to the 1-second pulse, generates a timing signal defining the timings for the operations in the respective portions of the ECR to be directed to the control section 110. The gate circuit 104 selects an input signal in accordance with a control signal from the clock control section 110 and feeds it to the adder/subtraction circuit 106. The add/subtract circuit 106 executes addition or subtraction in accordance with an instruction from the control section 110, and feeds the result of the calculation as write data to the memory l () 0 through a gate circuit 107. The data and carry resulting from of the calculation result are also applied from the add/ subtract circuit 106 to a decision arranged to decide whether the signals to be introduced into the memory circuit 108 relate to a scale of 60 (seconds, minutes) or to a scale of 24 (hours). The result of the decision made by decision circuit 108 is transferred to the control section 1 10 which in turn produces a control signal for the next processing, on the basis of the decision. The data read out from the memory 100 is applied to the AND circuit 75 in the CPU through gate circuit 109. The gate circuits 107 and 109, and the address designating circuit 101 are enabled by the chip enable signal CE2 from the chip designating circuit 82. The gate circuits 102, 104, 107 and the adder/subtraction circuit 106, and the decision circuit 108 are controlled by a signal from the control section 110.

The gate circuit 107 is controlled by the chip enable signal CE2 and signal from the control section 110. The memory 100 may have a memory capacity of 4 rows x 8 columns as shown in Figure 5A, for example. The respective columns B1 to B8 are specified by the column address CA and the respective rows are specified by the row address RA. The 1st to 3rd rows store time data such as hour and minute in each two columns, i.e. B8-B7, B6-Bs, B4-B3 and B2 Bl. Additionally, time data for the totalization times T(11 to T1)4 are stored in the 1st row; alarm time data ALl to AL4 in the 2nd row; and time data for service times SV, to SV4 in the third row. The time data T1 to T4 define the net total time range; the time ALl to AL4 alarm time; the time data SVl to SV4 service time for discount and the like. In the 4th row, the columns B8 to B7 store Flag 1 and Flag 2 to indicate coincidence between present time and a designated time; the columns B6 to B4 store "year", "month" and "date" of the day; and the columns B3 to B1 the "hour", "minute" and "second" of the present time.

In the memory location at row 4 and column B7 of the memory 100, for storing the Flag 2, a binary "1" is stored in the first bit b1 when the present time is between T1 and in the second binary bit b2 when it is between T2 and TX, and in the third bit b3 when it is between T3 and T4.

In operation, the clock circuit 48 operates in accordance with the reference signal fed from the crystal oscillator 50. The reference signal outputted from the crystal oscillator 50 is applied to the pulse generating circuit 105 which produces a 1-second pulse and various timing pulses. The 1-second pulse produced from the pulse generating circuit 105 is applied to the adder/subtraction circuit 106 through the gate circuit 104. The control section 110 sets the row address RA=4 to specify the 4th row of the memory 100, reads out the contents of this address from the memory 100 through gate circuit 102 and loads it into the buffer register 103.

The gate 104 responds to the output of the buffer register 103 and the 1-second pulse from the pulse generator 105 and applies them to the add/subtract circuit 106 thereby to add the second pulse to the "seconds" data in the B, column. The output signal of the add/subtract 106 is transferred to the memory 100 through the gate circuit 107, and written into the 4th row. In this manner, the contents of the 4th row of the memory 100 is continuously refreshed. The output of the add/subtract circuit 106 is transferred to the decision circuit 108 which decides whether or not the result of the addition has reached a predetermined value and the result of the decision determines the control operation in the control section 110. More specifically, when data representing the counted number of seconds pulses reaches the B1 row of the 4th column, i.e. the seconds data reaches 60 seconds, this condition is determined by the decision circuit 108 and the clock control section 110 adds "1" to the contents ofthe B2 column of the 4th row, i.e. the minutes data, while at the same time the seconds data is cleared. Thereafter, a similar carry control operation will be repeated in the order minute -- hour - month -- year. Clock operations to determined the time and date will thus be executed. At the initiation of the clock circuit 48, the date and time must be correctly set. In the setting operation, the control switch 20 in Figure 1, 20 set to the Pr mode and, under this condition, the amount keys 11 are actuated in the order year month-- day -- hour -- minute -- second. In this case, the non-add key "#" is depressed every time unit data is entered into the ECR. The input data inputted through the respective key operations, i.e. from the keyboard 10, is transferred to the CPU 34 through the I/O controller 31 where it is entered into the X register 78a via the AND circuit 74 and the OR circuit 76 shown in Figure 3. The input data stored in the X register 78a is transferred into the clock circuit 48 where it is loaded into locations at the intersections of the 4th row and B6 to B1 columns through the gate circuit 107. In this manner, the date and time data are loaded into the memory 100 of the clock circuit 48 and, after the second data loading is finally completed, the above-mentioned clock operation will continue.

The time data for totalization time zones, the time data for service time zones, and time data for alarm time zones are written into the memory 100, by using the amount key 11, and the To key 19b, the SV key 19a, or the AL key 19c respectively. For example, after the "hour" time data is inputted by the amount keys 11, the "minute" time data is inputted after actuation of the T (, key 19b. After the operation of the T, key 19b, the time sequence specifying data "1" is inputted by the amount key 11, to specify the intersection of the 1st row and the columns B7 and B8 so that the "hour" and "minute" data of the time data T1 are loaded into these addresses. When an operation similar to that above-mentioned is made by using the SV key 19a instead of the To key 19b, the time data for service time is loaded into the memory 100 at the intersections of the 3rd row and the columns B7 and B8. Use of the AL key 19c writes the time data for alarm into the intersections of the 2nd row and the B7 and B5 columns.

For loading a unit price for a department, the amount key 11 and the department key 12 are depressed with the control switch 20 switched to the Pr position. In this opera tion, the keyed input data is transferred into the memory device 47 by way of the X register 78a. In the memory 47, the input data is written into the Ist to 16th addresses in the 3rd region of the memory unit 91, through the gate circuit 93.

In processing the sales of goods. the control switch 2 () is set to the REG mode and the unit prices of the goods sold are entered by the amount keys 11. Then. one of the department keys 12 is actuated to denote the appropriate department. The dnta is fed to the printing section 33 where it is printed on the receipt paper 41 and the detail paper 42. At the same time, the input data is displayed in the display 24 to which this data is applied by way of the CPU 34 and the display driver 51 and is also stored in the CPU 34. Further, data from the memory circuit 47 corresponding to the address specified by the department key 12 is read out into the CPU 34 where it is added to the data inputted and the result of the addition is written into the specified address of the memory device 47. At this time, the price is added to a predetermined row of the first memory region 91A, and the item count is added to a predetermined row of the second region 91B. In this manner, an operation like that abovementioned will be repeated by operating the amount key 11 and the appropriate department key 12 for each sold. When the prices of all of the goods sold are entered and the departments are specified, the Ca/AMT/TEND key 18 is operated to issue a receipt, with totalization or change. The total amount thus obtained by the CPU 34 is displayed in the display section 24 and applied through the I/O controller 31 to the printing section 33 where it is printed on the detail paper 42 and the receipt paper 41. When it is processed by using the department key preset for each department as mentioned above, and without inputting the prices of goods an operation like the above-mentioned one will be performed with the input data of the preset data of the address corresponding to the actuated department key 12, through a mere operation of the respective department key.

The operation of timed totalization will be described with reference to Figures 1 to 8. When data relating to the goods sold is inputted, the keyed input signal is applied to the CPU 34 through the I/O controller 31 and set in the register 78a. The Ca/ AMT/TEND key 18 is then actuated so that the data in the X register 78a is transferred to the Y register 78b, as sh memory 100 into the output register 78a.

The present time 10:30 lies within the time zone T1 toT2, i.e. 10 : 00 to 12 : 00, binary"1" is set in the first bit b1 of the Flag 2 so that the Flag 2 is "0001". As shown in the step c of Figure 6, the contents "0001" of Flag 2 read out into the register 78a is transferred into the decision circuit 84, through the gate circuit 70 and the adder/subtracter 71. The decision circuit determines whether any one of the bits of the Flag 2 includes "1" or not, as shown in step d. When the result of the decision is NO, i.e. the present time does not belong to a designated time zone, the timed totalization is not performed and the receipt is immediately issued. When the judgement is YES, i.e. the present time belongs to any one of the designated time zones, the operation progresses to the step e in Figure 6. In this step, the control section 62 causes the chip designating circuit 82 to produce the chip enable signal CE1 and addresses the memory device 47 to specify one of the 17th to 19th row addresses in accordance with the contents of Flag 2. In this case, the present time resides in the time zone T1 to T2 so that the 17th row address of the memory device 47 is specified. The operation then progresses to stepf in Figure 6A. In this step, the contents of M(RA, CA), e.g, the article number"20' in the time zone T1 to T2 and the subtotal "Y13,200" in the same zone is read out into the X register 78a. The previous sales contents, e.g. "Y13,200" of the X register 78a and the sales data, e.g. "700", stored in the Y register 78b are transferred through the gate circuit 70 to the add/subtract circuit 71, in which they are added together. The article number "20" stored in the time zone T1 to T2 is also applied to the adder/ subtraction circuit 71 where it is subjected to a "+" operation. Then, the total amount "Y13,900" in the time zone T, to T2 and the article number "21" in the same time zone are loaded into the 17th address of the memory device 47.

The detailed data flow during the step e of Figure 6A is shown in Figure 6B. In a step e1, it is determined whether "1" is set in the first bit b1 or not, i.e. the contents of Flag 2 is 0001 or not. If a "1" is set in the bit b,, step e2 loads the chip enable signal CE1 into the X register 78a and the row address RA=17 and the column address CA=B, are also loaded into the A register 83. When in the step e1, it is found that "1" is not set in bit b1, a step e3 is executed to determine whether binary "1" is set in the second bit b2 or not. If "1" is set in bit b2, a step e4 loads the chip enable signal CEl into the X register 78a and sets the row address RA=17 and the column address CA=B, in the A register 83. If, in step e3 "1" is found not to be stored in bit b2 a further step e5 is executed. This step loads the chip enable signal CE1 into the X register 78a and the row address RA=19 and the column address CA=B1 into the A address register 83.

Figure 8B illustrates the case when the sales processing is made at 11:50.

When the sale being processed is made after 12:00, for example, at 12:01 as shown in Figure 8C, it is totalized and the receipt is issued, the locations of the 18th row and the columns B6 to B1 of the memory 100 are specified since, at this time, the second bit b2 of the Flag 2 is set at "1" and therefore the contents of this flag is "0010". If this sale is the first to be made after 12:00, the contents of the 18th row and the columns B6 to B1 are all "0". Accordingly, the article number "1" is loaded into the memory locations at columns B6 to B1 and the 18th row, for the time zone T2 to T3, together with the total amount in the same time zone, which is the sale amount at this time, for example, "Y450". After this, data totalization will be continued with respect to the memory locations of the 18th row and the columns B5 to B1 of the memory 100 until time T3, i.e. 14:00.

After 14:00, data will be totalized with respect to the memory locations of the 19th row and the columns B6 to B1 until time T4 i.e. 17:00 in this example. In this manner, the amount of money and the number of articles are totalized and then the operation advances to a step g. In this step, this sales data (the above-mentioned total amount) stored in the Y register 78b in the register group 77 is transferred to the X register 78a and then to the I/O controller 31, where it is stored in the output buffer register (not shown). The I/O controller controls the printing section 33 on the basis of the data stored in the output buffer register and prints the data, as shown in step h of Figure 6. In the step h, the printing shown in Figures 9A and 9B is made in addition to the data printing. At the end of data printing, a serial number is printed, as shown in step h, of Figure 9A. At this time, the microprogram read out from the control section 62 sets the chip designating data to specify the memory device 47 in the X register 78a.

Then, the microprogram of the control section 62 transfers an operation instruction to the chip designating circuit 82. Upon receipt of the operation program, the chip designating circuit 82 reads out the chip designating data from the S register 78a to produce the chip enable signal CE1 and to specify the memory device 47. Then, the control section produces an address code to specify the memory locations of the 17th row and the columns B8 and B7 of the memory unit 91. The address code then is converted into a serial code by the code generating circuit 67. The serial code thus converted is then transferred to the add/ subtract circuit 71, through the gate circuit 70. The address data outputted from the add/subtract circuit 71 is loaded into the A register 83 where it is converted into parallel data to be fed to the address designating circuit 92. A read instruction fed from the control section 62 through the instruction decoder 69 is set in the addressing circuit 92.

As a result, the contents of the memory locations of the 17th row and or columns B8 and B7,i.e. the serial number, for example, "3400", is read out from the memory unit 91 and the consecutive number is then applied to the X register 78a through the AND gate 75 and the OR circuit 76. The serial number read out from the X register 78a is transferred to the output buffer register in the I/O controller 31, together with "No" shown in Figure 9A. The data set in the output buffer register controls the operation of the printing section 33, to print the serial number "No3400" on the receipt. The serial number "3400" read out into the X register 78a is applied to the add/subtract circuit 71 where it is subjected to the "+1" operation.

Through this addition, the serial number becomes "3401" which is in turn loaded into the memory locations of the 17th row and the columns B8 and B7 of the memory unit 91.

When the printing of the serial number is completed, the CPU 34 issues a paper feed instruction to the I/O controller 31. As a result, a paper feed appropriate to the N columns of the receipt is executed as shown in a step h2 in Figure 9A.

Then, the CPU 34 transfers a stamp printing instruction to the I/O controller 31 so that "YOUR RECEIPT THANK YOU" is printed, as shown in step h3 in Figure 9A.

When the stamp printing is completed, the operation shifts to the date printing mode so that the CPU 34 issues a chip designation to the clock circuit 48 and the address of the date to the inemory 100. That is, the CPU 34 transfers a code designating the clock circuit chip 48, e.g. "0010" to the X register 78a, and at the same time issues an operation instruction to the chip designating circuit 82, through the control section 62. Upon receipt of the operation instruction, the chip designating circuit 82 reads out the chip designating code '0010" from the X register 78a, and produces the chip enable signal CE2 to designate the the clock circuit chip 48. Then, the control section 62 transfers the address data to the address register 83, through the gate circuit 70 and adder/subtraction circuit 71. The address data specifies the memory locations of 4th row and the columns B6, B5 and B4. The address data is transferred from the address register 83 to the address designating circuit 101 in the clock circuit 48. In the address designating circuit 101, a read instruction is set which is fed from the control section through the instruction decoder 69. As a result, the date data, for example, if it is November 20, 1976, "76 11 20", is read out from the memory locations of 4th row and of columns B6, B5 and B4 of the memory 100 as shown in step h5 of Figure 9B. The date data read out is transferred to the X register 78a, through the gate circuit 109, the AND circuit 75 and the OR circuit 76. The date data read out into the X register 78a is tranferred to the output buffer register in the I/O controller, together with the segment code, as shown in a step h6 of Figure 9B. The I/O controller 31 controls the printing section 33 in accordance with the data stored in the output buffer register to print the date, as shown in a step h7 in Figure 9B. The receipt issuing operation is made in the above-mentioned manner. The stamp printing "YOUR RECEIPT THANK YOU" and the printing of data are made for the succeeding receipt. As shown in Figure 9B, the receipt is torn off between the consecutive number printing with N rows space and the stamp printing. Therefore, the stamp printing and the date printing are positioned at the upper portion of the receipt issued.

In the above-mentioned embodiment, the time and date are set up by setting the control switch 20 to the Pr mode and alternately depressing the appropriate amount keys 11 and the non-add key "#".

However, year, month, day, hour, minute, and second may be consecutively inputted by using the amount key and finally actuating the non-add key "#", for the same pulse. When the totalizing time is set up, hour and minute may be continuously inputted by the amount keys 11 and then operating the totalizing key To 19b, unlike the above-mentioned example. Since the totalizing key T( 19b is separately provided, it may be arranged to be always operable irrespective of the mode set by the control switch 20. If the totalizing key To 19b is desired to be replaced by another key, the ST key 17 or the like may be used under the condition that the control switch 20 is switched to the Pr mode, for example.

In the above-mentioned embodiment the memory unit 91 has a plurality of memory locations for storing a sales item total in connection with a time zone. The memory locations are shown in the sales item total between times T1 and T2, T2 and T3, and T3 and T4. The sales item total is cumulatively stored in one memory location according to the result of comparison by the comparator and according to the flow chart of Figure 6A when an entry is made by the operation of the "cash/amount tendered" key. The memory unit 91 can be so constructed that is has a plurality of memory locations for storing a department sales item total in connection with the time zone. The department sales item total is cumulatively stored in one memory location by the same operation as in the flow chart of Figure 6A.

This is effected according to the result of the comparison made by the comparator, when an entry for a department is effected by the operation of the department key 12.

The memory unit 91 can also be so constructed that it has a plurality of memory places for storing individual transaction amounts in connection with the time zone.

The transaction amount is cumulatively stored in one memory location by the same operation as in a flow of Figure 6A. This storing is done according to the result of the comparison made by the comparator.

The above-mentioned memory unit 91 can also be so constructed that it has a plurality of memory locations, for storing a clerk sales amount in connection with the time zone. The clerk sales amount is stored in one memory location in connection with a clerk designated by a clerk key 15. This storing is done according to the result of the comparison made by the comparator and according to the Figure 6A flow chart each time the sales amount is entered.

The total and count may be totalized not only within time but also within the date. In this case, the memory location for storing the total and count of the preset date is provided and every time the registration is made, the preset date is compared with the date of that registration to accumulately store the total and count in the given memory location.

Reference is directed to our co-pending Application No. 7933756 (Serial No.

1594240) which is divided from the present application.

Claims (12)

WHAT WE CLAIM IS:-

1. An electronic cash register comprising a keyboard including data input keys and time zone setting key; a central processing unit coupled to said keyboard; a memory coupled to said central processing unit and having a plurality of memory locations for storing cumulative sales accounts on a time zone basis, a time memory coupled to said central processing unit and arranged to store time zone defining data in response to the operation of the time zone setting key, a timepiece coupled to said time memory to supply current time data, and a comparator coupled to said timepiece and said time memory to compare current time data from said timepiece and time data in said time memory, in which said central processing unit includes means for writing entered data in a memory location of said memory according to the time zone determined by the result of comparison by said comparator when entry of data from said keyboard is completed.

2. An electronic cash register according to claim 1 in which said keyboard includes a cash amount tendered key for indicating termination of an entry operation, said memory has a plurality of memory locations for storing a sales item total in connection with respective time zones and a sales item total is cumulatively stored in a said memory location according to the result of the comparison by said comarator when an entry is completed by the operation of said cash amount tendered key.

3. An electronic cash register according to claim 1 or claim 2, in which said key board includes a department key, for effecting a department data entry, said memory has a plurality of memory locations for storing department sales item totals in connection with a time zone and a means whereby department sales item total is cumulatively stored in one memory location of said plurality of memory places according to the result of comparison by a comparator, when an entry for a department is effected by the operation of the respective department key.

4. An electronic cash register according to any one of claims 1 to 3 in which said keyboard includes a transaction key for effecting a sales data entry such as a balance, net total, receipt paid, charge etc., said memory has a plurality of memory locations for storing a transaction sales total in connection with the time zone and means are provided whereby a sales amount is cumulatively stored in one memory location of said plurality of memory places according to the result of comparison by a comparator when a sales data entry is effected by the operation of the transaction key.

5. An electronic cash register according to any one of claims 1 to 4 in which said key board includes clerk keys for indicating the clerk who enters a sales amount, said memory has a plurality of memory locations for storing a clerk sales total relating to the time zone and means whereby a sales amount is stored in one of said plurality of memory places with respect to a clerk designated by the clerk key, this storing being effected according to the result of comparison by a comparator each time entry is effected with respect to a sales amount.

6. An electronic cash register according to claim 1 in which said timepiece comprises a pulse producing circuit for frequencydividing a reference signal, a calculation circuit for successively and additively timecounting the pulse signals from said pulse producing circuit and means for supplying current time data from the calculation cir cuit to the time memory.

7. An electronic cash register according to any one of claims 1 to 5 in which said time memory has a memory area for storing current time data.

8. An electronic cash register according to claim 1 or 6 in which said time memory includes a memory region for storing a flag indicative of a result of comparison made by a comparator between said current time data and said time data.

9. An electronic cash register according to claim 1 or 6 in which said time memory means has a memory region for storing an alarm time.

10. An electronic cash register according to claim 9 in which said time memory includes a memory region for storing a flag indicating the result of comparison made by a comparator between said current time and said alarm time.

11. An electronic cash register according to claim 1 in which the time memory, timepiece and comparator are constructed on a single chip.

12. An electronic cash register substantially as herein described with reference to the accompanying drawings.