GB1594240A - Electronic cash register - Google Patents

Description

PATENT SPECIFICATION

( 21) Application No 33756/79 ( 62) Divided Out of No 1594239 ( 22) Filed 28 Dec 1977 ( 31) Convention Application No's 51/156453 ( 32) Filed 27 Dec 1976 in Te ITD\ 51/156454 k 33) Ja 1 pdan Lt Jr) ( 44) Complete Specification Published 30 Jul 1981 ( 51) INT CL 3 G 06 C 27/02 ( 52) Index at Acceptance G 4 T BA ( 54) ELECTRONIC CASH REGISTER ( 71) We, CASIO COMPUTER COMPANY LIMITED, a Japanese corporation, of 6-1, 2-chome, Nishishinjuku, Shinjukuku, Tokyo, Japan, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:The present invention relates to an electronic cash register which includes a time counting circuit and prints the sales data on a receipt according to time data and date data supplied from the time counting circuit.

Generally, in the electronic cash register, the value of each item sold is inputted by actuation of an entry key and then a department key of the department to which the goods sold belongs is operated The inputted data is properly processed, assorted and accumulatively stored in memories allotted for totalizations of the sale amount and the item count for each department, the gross sale total for the day and the sales total for each clerk At the end of the day's work, the cash register is set to a reset mode to successively print out the various data stored in the corresponding memories and then these memories are cleared These assorted sales data will be used for management purposes Therefore, it is preferable that the sales data are detailed and correct while as brief as possible.

Since the conventional cash register is not provided with a clock function, it can totalize only one day's sales so that the data obtained are insufficient for such purpose If we knew the sales made during specific time zones of the day, for example, morning, afternoon and evening, it would be effective and useful for management purposes.

Further, if the time counting function is extended to year, month, week and day, an operator can preset the time period for totalization, for example, a week, a month, every two days or the like Accordingly, the totalization for a period longer than a day may be automatically made, resulting in a remarkable improvement of the totalization function of the register.

Generally an electronic cash register prints the date of sales on a receipt paper In the conventional electronic cash register which is not provided with a time counting circuit, the entry keys are selectively depressed to store the date of sales into a memory When a receipt is to be issued, the data representing the sales date are read out from the memory, and the sales date is printed on the receipt paper The operator must therefore depress the entry keys to enter the date, every morning before he uses the cash register for the first time for the day.

The object of the present invention is to provide an electronic cash register which is provided with a time counting circuit and which can print the date of sales on a receipt paper according to automatically updated year, month and day date supplied from the time counting circuit.

According to the present invention there is provided an electronic cash register comprising a keyboard including data input keys, a central processing unit coupled to said keyboard, a memory device coupled to said central processing unit and having a memory location for storing accumulated sales amounts, a time memory coupled to said central processing unit and having a memory location for storing year, month and day data, a timepiece coupled to said time memory to update the year, month and day data, and printing means coupled to said time memory to print the year, month and day data stored in said time memory.

With such a construction, date printing may be effected when receipts are issued without the need for presetting the date 0 o ( 11) 1 594 240 1 594 240 data.

Other features and advantages of the present invention will be apparent from the following description taken in connection with the accompanying drawings, in which:

Figure 1 shows a keyboard of an electronic cash register; Figures 2 A and 2 B cooperate to form a block diagram of the entire cash register; Figure 3 A is a circuit diagram of a central processing unit (CPU) used in the circuit of Figure 2; Figure 3 B is a circuit diagram illustrating a memory circuit and a clock circuit used in the arrangement of Figure 2; Figure 4 shows a memory map of the memory circuit; Figures 5 A and 5 B show memory maps of the memory in the clock circuit; Figures 6 A and 6 B show a flow chart for illustrating the operation of the circuit in time counting; Figure 7 shows data stored in the memory in the clock circuit; Figures 8 A to 8 C illustrate data stored in the memory and the register during time counting; and Figures 9 A and 9 B schematically illustrate the operation of printing the serial number and date on a receipt.

Referring now to Figure 1, there is shown an arrangement of a keyboard 10 of an electronic cash register (ECR) In the figure, reference numeral 11 designates a set of "amount" keys for entering numeral values such as cost, quantity, and the like of goods, 12 a set of "department" keys for registering goods in groups, 13 a "clear entry" key for erasing numerals inputted by the amount keys 11 A set of "function" keys designated by reference numeral 14, is comprised of keys representing non-add (#) for setting up the present time, void (Vo), multiplication (@), percentage (%) and (+) and (-) for indicating increase and decrease of the percentage Reference numeral 15 designates a set of "clerk" keys for entering the number of a person responsible for an operation A set of transaction keys 16 is comprised of keys representing receipt (Rc), paid out (Pd), net total (NT) balance (BL), no sale (NS) credit (Cr), and charges (Ch) Reference numeral 17 designates a subtotal key for obtaining the interim result of a course of calculation A "cash amount tendered" key (Ca/AMT) 10 is used for issuing a receipt, for obtaining S total or for giving change A set of "time" keys 19 is used to set up required time zones Key 19 a is used for setting up a service time zone.

Key 19 b is used to sets up a totalization time zone Reference 19 c designates an alarm key (AL) for setting up an alarm time zone.

The x keys 19 a to 19 c constitute the time key 19 A control lock 20 allows selection of the modes (OFF), (Pr), (REG), (X) and (Z).

The (OFF) mode is used when the ECR is not to be used; the (Pr) mode for presetting data; the REG mode for normal registering operations; the (X) mode for a reading operation without destroying data stored; (Z) mode for executing a reset operation to clear data after the stored data is read out.

The following explanation relates to the internal construction of an electronic cash register embodying the present invention.

Reference numeral 31 is an I/O (input/ output) controller which controls the keyboard 10 and a printing section 33 The I/O controller 31 applies a sampling signal to the keyboard 10 When a key is actuated on the keyboard 10, a sampling signal is selected in response to the key actuation and is applied as a key input signal to the 1/0 controller 31 Upon receipt of the key input signal from the keyboard, the I/O controller 31 loads the key input signal into an input buffer register (not shown) and temporarily stores it therein The I/O controller 31 is coupled with a central processing unit (CPU) 34 When the CPU issues a control signal of an input instruction to the I/O controller 31, the key input signal in the input buffer is read into the CPU 34 When receiving printing data from the CPU 34, the I/O controller 31 loads the printing data into an output buffer (not shown) in which it is temporarily stored therein The printing section 33 is comprised of a receipt paper printer 36 and a detail paper printer 37 The printers 36 and 37 are provided with printing drums 38 and 39 which are coaxially arranged and have numerical characters on their respective surfaces, respectively Receipt paper 41 and detail paper 42 are disposed close to the printing drums 38 and 39, respectively Printing hammers are disposed adjacent the printing drums 38 and 39 with the receipt paper 41 or the detail paper 42 respectively, with ink ribbons (not shown) interposed therebetween, respectively A printing position detecting device 44 is provided at one of the ends of the printing drum shaft to detects the printing positions of the printing drums 38 and 39 yields detection signals as the drums turn through specified rotational angles The detection signals are applied to the I/O controller 31 through an amplifier 45 When the printing position detection signal and the printing data coincide, the I/O controller 31 supplies a drive signal via a driver 35 to the printing hammer confronting the printing type at that time, thereby actuating the hammer When the printing drums 38 and 39 have revolved through by one revolution, one line printing operation is complete and the receipt paper 41 and the detail paper 42 are fed by one line As the printing operation progresses, the receipt paper 41 is 1 594 240 guided out of the ECR to permit the printed portion of it to be torn off, after the printing is completed A legend such as "YOUR RECEIPT THANK YOU", for example, may be printed on the receipt paper 41 For recording the net total the same information as is printed on the receipt paper 41 is also recorded on the detail paper 42, wound on a drum 46.

A memory device 47 and a clock circuit 48 are coupled with the CPU 34 A power source 49 is coupled with both the memory device 47 and clock circuit 48 to make them to always be ready for their operations The clock circuit 48 also is coupled with a reference frequency oscillator, for example, a crystal oscillator 50 The memory device 47 and the clock circuit 48 may each be fabricated as a single chip The CPU 34 produces a chip enable signal CE 1 to specify the memory circuit 47 and another chip enable signal CE 2 to specify the clock circuit 48 A read/write signal R/W from the memory 47 specifies a reading or the writing operation for the memory device 47 The clock circuit provides time data and date data which are read out by the CPU 34, if necessary When a receipt is to be issued, the CPU reads out date information from the clock circuit 48 to cause the printing section to print the date on which the receipt is issued The time data is used as time marking data when totalizing is to performed over a given time zone The CPU 34 executes a receipt issuing operation in response to the appropriate key input signal from the keyboard At that time the processing data is transferred as printing data to the I/O controller 31 and to a display section 24 through a display driver 51 where it is visualized made visible.

Figures 3 A and 3 B cooperate to illustrate the details of the CPU 34, the memory device 47, and the clock circuit 48 The CPU 34 is first described An address circuit 61 specifies an address of in control section 62.

The control section 62 includes a microprograms to control the operations of the respective circuits, which are stored in a read only memory (ROM) The control section has output lines 63 to 66 The output line 63 provides a code generation instruction; the output line 64 a given timing signal; the output line 65 provides instructions, for example, a register specifying signal, a transfer instruction and a digit shift instruction; the output line 66 provides signals denoting the next address in sequence in the control section The code generating instruction from the output line 63 is transferred to a code generating circuit 67 A timing signal from the output line 64 is transferred to a timing designating circuit 68 The instructions from the output line 65 is transferred to an instruction decoder 69.

The next address outputted to the output line 66 is transferred to the address circuit 61 for specifying the next address A timing signal from a timing signal generator 80 provided in the CPU 34 is applied to the code generating circuit 67, the timing instruction circuit 68, and the instruction decoder 69 The code generating circuit 67 converts parallel data consisting of 4 bits for example, provided by the control section 62 at a given time, into a serial code signal The output of the code generating circuit 67 is transferred through a gate circuit 70 to an addition subtraction circuit 71 through a gate circuit 70 The timing designating circuit 68 specifies the timing of operations in the register such as digit specifying of it in accordance with the timing signal fed through the output line 64 from the control section 62 The output signals of circuit 68 are applied as enabling and disabling signals to the respective gate circuits in the CPU 34 such as a gate circuit 70, and AND circuits 72 to 75 The outputs of the AND circuits 72 to 75 are applied through the OR circuit 76 to an input/output register 78 a in the register group 77 The instruction decoder 69 decodes the instruction given from the control section 62 to control the operations in the respective portions in the CPU 34, such as designation of a register in the register group 77 and gives a read/write instruction to the memory 47 and the clock circuit 48 The outputs of the timing designating circuit 68 and the instruction decoder 69 are applied as control signals to the display driver 51 and the I/O controller 31.

The register group 77 includes the X register for input/output register 78 a, and other registers 78 b to 78 N denoted as the Y to N registers The output of the register group 77 is coupled with an add/subtract circuit 71, through the OR gate 70 The output of the X register 78 a is also applied to the AND circuit 72, through circuit 79 a with -one digit memory capacity The output signal of the add/subtract circuit 71 is applied to the AND circuit 73 The key input signal from the keyboard 10 is applied via the I/O controller 31 to the AND circuit 74 Data decoded from the memory device 47 and the clock circuit 48 is applied to the AND circuit The output signals of the X to N registers 78 b to 78 N are applied respectively to gate circuits 81 b to 81 n, through respective registers 79 b to 79 N each with one digit memory capacity The output signal of the add/subtract circuit 71 is also applied to the gate circuits 81 b to 81 n The outputs of the gate circuits 81 b to 81 N are applied to the X to N registers 78 b to 78 n, respectively The output of the X register 78 a is applied as display data or printing data to the display driver 51 and the I/O controller 31 and to a chip designating circuit 82 In accordance 1 594 240 with an instruction from the control section 62, the chip designating circuit 82 reads out the chip designating data in the X register 78 a and produces the chip enable signals CEI and CE 2 in accordance with the register contents, thereby to designate the memory 47 or the clock circuit 48 The output of the add/subtract circuit 71 is loaded into an A (address) register 83 for addressing Data decoded by the A register 83 is inputted to the add/subtract circuit 71 through a gate circuit 70 and is divided into two addresses; a row address RA and a column address CA These addresses are applied to the memory 47 and the clock circuit 48, respectively Data and carry signals outputted from the add/subtract circuit 71 are transferred to a decision circuit 84 The decision circuit 84 decides whether the data or the carry from the circuit 71 is or is not present and passes the result of the decision to the address circuit 61 At this time, the succeeding address outputted onto the output line 66 and the detection signal are logically summed so that the next address is changed.

The memory circuit 47 includes a memory unit 91, an address designating circuit 92 into which the read/write (R/W) instruction from the instruction decoder 69, and the row and column addresses from the A register 83 are loaded The address designating circuit 92 and the gate circuit 93 are enabled by the chip enabling signal CE 1 given from the chip designating circuit 82.

Data read out from the memory body 91 through the gate circuit 93 is applied to the AND circuit 75 of the CPU 34, as previously stated The output signal of the X register 78 a in the CPU 34 is applied as write data to the memory unit 91, through the gate circuit 93 The memory unit 91 has a capacity of nx 8, as shown in Figure 4 The columns B, to By are designated by the column address CA and the rows 1 to it are designated by the column address RA The memory store 91 is divided into three regions; a first region 91 A including columns B, to B 4, a second region 91 B including columns B 5 and B 6, and a third region 91 C including columns B 7 to B 8 In the first region 91 A, the 1st to 16th row addresses store the department total corresponding to the actuated department key 12 The 17th row address stores the sale total between the designated times T 1 and T 2 The 18th row address stores the sale total between the specified times To and T 3.

The 19th row address stores the sale total within the time range between the specified times T, and T 4 The 20th row address stores the receipt total Such a memory region will be called a time designated sale total memory region In the second region.

the item count is stored in the 1st to 16th row addresses The item counts within the specified times zones T 1 to T 2, T 2 to T 3, and T 3 to T 4 are stored in the 17th to 19th row addresses, respectively The receipt count is stored in the 20th row address Preset unit prices in the respective departments are stored in the 1st to 16th row addresses of the third region 91 C.

In Figure 3 B, the clock circuit 48 is provided with a memory 100 for storing the date of the day, present time data, preset time data and the like The memory 100 is specified by the row and column addresses RA and CA set in the address designating circuit 101 through the A register 83 in the CPU 34 and its read and write operations are specified by the R/W instruction fed from the instruction decoder 69 A control section 110 in the clock circuit 48 feeds an address code signal and a R/W instruction to the address designating circuit 101 for addressing the memory 100 The data outputted from the memory 100 is applied to a buffer register 103 via through a gate circuit 102 and also to the gate circuits 104 and 109.

The output of a buffer register 103 and a 1-second clock pulse from a pulse generating circuit 105 are applied to the gate circuit 104 The pulse generating circuit 105 operates in response to a reference signal from a crystal oscillator 50 and, in addition to the 1-second pulse, generates a timing signal defining the timings for the operations in the respective portions of the ECR to be directed to the control section 110 The gate circuit 104 selects an input signal in accordance with a control signal from the clock control section 110 and feeds it to the adder/subtraction circuit 106 The add/subtract circuit 106 executes addition or subtraction in accordance with an instruction from the control section 110, and feeds the result of the calculation as write data to the memory 100 through a gate circuit 107 The data and carry resulting from of the calculation result are also applied from the add/ subtract circuit 106 to a decision circuit 108 arranged to decide whether the signals to be introduced into the mem relate to a scale of (seconds, minutes) or to a scale of 24 (hour The result of the decision made by decision circuit 108 is transferred to the control section 110 which in turn produces a control signal for the next processing, on the basis of the decision The data read out from the memory 100 is applied to the AND circuit 75 in the CPU through gate circuit 109 The gate circuits 107 and 109, and the address designating circuit 101 are enabled by the chip enable signal CE 2 from the chip designating circuit 82 The gate circuits 102, 104 107 and the adder/subtraction circuit 106, and the decision circuit 108 are controlled by a signal from the control section 110.

The gate circuit 107 is controlled by the chip enable signal CE 2 and signal from the control section 110 The memory 100 may 1 594 240 5 have a memory capacity of 4 rows x 8 columns as shown in Figure 5 A, for example The respective columns B, to B 8 are specified by the column address CA and the S respective rows are specified by the row address RA The 1st to 3rd rows store time data such as hour and minute in each two columns, i e B 8-B 7, B 6-B 5, B 4-B 3 and B 2B, Additionally, time data for the totalization times T 11 to TO 4 are stored in the 1st row; alarm time data AL 1 to AL 4 in the 2nd row; and time data for service times SV, to SV 4 in the third row The time data T 1 to T 4 define the net total time range; the time data AL, to AL 4 alarm time; the time data SV 1 to SV 4 service time for discount and the like In the 4th row, the columns B 8 to B 7 store Flag 1 and Flag 2 to indicate coincidence between present time and a designated time; the columns B 6 to B 4 store "year", "month" and "date" of the day; and the columns B 3 to Bl the "hour", "minute" and "second" of the present time.

In the memory location at row 4 and column B 7 of the memory 100, for storing the Flag 2, a binary " 1 " is stored in the first bit bl when the present time is between T 1 and T 2, in the second binary bit b 2 when it is between T 2 and T 3, and in the third bit b 3 when it is between T 3 and T 4.

In operation, the clock circuit 48 operates in accordance with the reference signal fed from the crystal oscillator 50 The reference signal outputted from the crystal oscillator 50 is applied to the pulse generating circuit which produces a 1-second pulse and various timing pulses The 1-second pulse produced from the pulse generating circuit is applied to the adder/subtraction circuit 106 through the gate circuit 104 The control section 110 sets the row address RA= 4 to specify the 4th row of the memory 100, reads out the contents of this address from the memory 100 through gate circuit 102 and loads it into the buffer register 103.

The gate 104 responds to the output of the buffer register 103 and the 1-second pulse from the pulse generator 105 and applies them to the add/subtract circuit 106 thereby to add the 1-second pulse to the "seconds" data in the B, column The output signal of the add/subtract 106 is transferred to the memory 100 through the gate circuit 107, and written into the 4th row In this manner, the contents of the 4th row of the memory is continuously refreshed The output of the add/subtract circuit 106 is transferred to the decision circuit 108 which decides whether or not the result of the addition has reached a predetermined value and the result of the decision determines the control operation in the control section 110 More specifically, when data representing the counted number seconds pulses reaches the B, row of the 4th column, i e the seconds data reaches 60 seconds, this condition is determined by the decision circuit 108 and the clock control section 100 adds " 1 " to the contents of the B 2 column of the 4th row, i.e the minutes data, while at the same time the seconds data is cleared Thereafter, a similar carry control operation will be repeated in the order minute hour month year Clock operations to determined the time and date will thus be executed At the initiation of the clock circuit 48, date and time must be correctly set In the setting operation, the control switch 20 in Figure 1, set to the Pr mode and, under this condition, the amount keys 11 are actuated in the order year month day hour minute second In this case, the non-add key "#" is depressed every time unit data is entered into the ECR The input data inputted through the respective key operations, i e from the keyboard 10, is transferred to the CPU 34 through the I/O controller 31 where it is entered into the X register 78 a via the AND circuit 74 and the OR circuit 76 shown in Figure 3 The input data stored in the X register 78 a is transferred into the clock circuit 48 where it is loaded into locations at the intersections of the 4th row and B 6 to Bl columns through the gate circuit 107 In this manner, the date and time data are loaded into the memory 100 of the clock circuit 48 and, after the second data loading is finally completed, the abovementioned clock operation will continue.

The time data for totalization time zones, the time data for service time zones, and time data for alarm time zones are written into the memory 100, by using the amount key 11, and the To key 19 b, the SV key 19 a, or the AL key 19 c respectively For example, after the "hour" time data is inputted by the amount keys 11, the "minute" time data is inputted after actuation of the To key 19 b After the operation of the To key 19 b, the time sequence specifying data " 1 " is inputted by the amount key 11, to specify the intersection of the 1st row and the columns B 7 and B 8 so that the "hour" and "minute" data of the time data T 1 are loaded into these addresses When an operation similar to that above-mentioned is made by using the SV key 19 a instead of the To key 19 b, the time data for service time is loaded into the memory 100 at the intersections of the 3rd row and the columns B 7 and B 8 Use of the AL key 19 c writes the time data for alarm into the intersections of the 2nd row and the B 7 and B 8 columns.

For loading a unit price for a department, the amount key 11 and the department key 12 are depressed with the control switch 20 switched to the Pr position In this operation, the keyed input data is transferred into the memory device 47 by way of the X register 78 a In the memory 47, the input 1 594 240 1 594 240 data is written into the 1st to 16th addresses in the 3rd region of the memory unit 91, through the gate circuit 93.

In processing the sales of goods, the control switch 20 is set to the REG mode and the unit prices of the goods sold are entered by the amount keys 11 Then, one of the department keys 12 is actuated to denote the appropriate department The data is fed the printing section 33 where it is printed on the receipt paper 41 and the detail paper 42 At the same time, the input data is displayed in the display 24 to which this data is applied by way of the CPU 34 and the display driver 51 and is also stored in the CPU 34 Further, data from the memory circuit 47 corresponding to the address specified by the department key 12 is read out into the CPU 34 where it is added to the data inputted and the result of the addition is written into the specified address of the memory device 47 At this time, the price is added to a predetermined row of the first memory region 91 A, and the item count is added to a predetermined row of the second region 91 B In this manner, an operation like that above-mentioned will be repeated by operating the amount key 11 and the appropriate department key 12 for each sold When the prices of all of the goods sold are entered and the departments are specified, the Ca/AMTTEND key 18 is operated to issue a receipt, with totalization or change The total amount thus obtained by the CPU 34 is displayed in the display section 24 and applied through the 1/0 controller 31 to the printing section 33 where it is printed on the detail paper 42 and the receipt paper 41 When it is processed by using the department key preset for each department as mentioned above, and without inputting the prices of goods, an operation like the above-mentioned one will be performed with the input data of the preset data of the address corresponding to the actuated department key 12, through a mere operation of the respective department key.

The operation of timed totalization will be described with reference to Figures 1 to 8 When data relating to the goods sold is inputted, the keyed input signal is applied to the CPU 34 through the 1/0 controller 31 and set in the register 78 a The Ca/ AMTTEND key 18 is then actuated so that the data in the X register 78 a is transferred to the Y register 78 b, as shown in a step a in Figure 6 A The data flow at this time is suchthat the data emanating from the X register 78 a flows through the gate circuit 70, the adder/subtraction circuit 71, and the gate circuit 81 b into the Y register 78 b At the next step b, the control section 62 reads out the chip specifying data to specify the memory 100 in the clock circuit 48 and then loads into it the digits stored in the X register 78 a The control section 62 issues an operation instruction to the chip specifying circuit 82 Upon receipt of the operation instruction, the chip designating circuit 82 reads out the chip designating data from a given digit of the X register 78 a and produces the chip enabling signal CE 2 to specify the memory 100 The control section 62 then produces addresses RA= 4 and CA= B 7 to specify the intersection of the 4th row and the column B 7 of the memory 100.

The addresses are converted into serial codes by the code generating circuit 67 and then the converted code is transferred to the adder/subtraction circuit 71 through the gate circuit 70 The addresses RA and CA outputted from the adder/subtractor 71 are inputted to the A register 83 where it is converted into parallel data which in turn transferred to the addressing circuit 101 in the clock circuit 48 A read instruction from the control section 62 is issued through the instruction decoder 69 That is, the chip enabling signal CE 2 specifies the clock circuit 48 and the Flag 2 addresses the memory 100 Through the addressing of the step b, the Flag 2 stored in the location M( 4,B 7) of the 4th row and the B 7 column of the memory 100 is read out and the read-out signal is transferred to the X register 78 a, through the AND gate 75 and the OR circuit 76 When the present time is read out from the memory 100 into the buffer register 103, the clock circuit 78 successively reads out the time data representing the totalization time zone T 1 to T 4 from the memory 100 and applies this data through the gate circuit 104 to the add/ subtract circuit 106 to compare it with the present time stored in the buffer register 103 The result of the comparison is applied to the decision circuit 108 In the decision circuit 108, the time zone, i e T 1 to T 2, T 2 to T 3, or T 3 to T 4, to which the present time belongs is determined and a binary " 1 " is loaded into the corresponding bit of the Flag 2 memory location bl to b 3 of the memory 100.

Assuming now that the time T is preset to be 10:00; T 2 12:00; T 3 14:00; T 4 17:00, and that, under this condition, a printed receipt is issued at 10:30 by depression of the key 18 As described above, memory location M( 4,B 7) of the memory 100 is addressed and the content of the Flag 2 is read out from the memory 100 into the output register 78 a The present time 10:30 lies within the time zone T 1 to T 2 i e 10:00 to 12:00, binary " 1 " is set in the first bit bl of the Flag 2 so that the Flag 2 is 001 " As shown in the step c of Figure 6, the contents " 0001 " of Flag 2 read out into the register 78 a is transferred into the decision circuit 84, through the gate circuit 70 and the adder/subtractor 71 The decision circuit 1 594 240 determines whether any one of the bits of the Flag 2 includes " 1 " or not, as shown in step d When the result of the decision is NO, i e the present time does not belong to a designated time zone, the timed totalization is not performed and the receipt is immediately issued When the judgement is YES, i e the present time belongs to any one of the designated time zones, the operation progresses to the step e in Figure 6 In this step, the control section 62 causes the chip designating circuit 82 to produce the chip enable signal CE 1 and addresses the memory device 47 to specify one of the 17th to 19th row addresses in accordance with the contents of Flag 2 In this case, the present time resides in the time zone T 1 to T 2 so that the 17th row address of the memory device 47 is specified The operation then progresses to step f in Figure 6 A.

In this step, the contents of M(RA, CA), e.g, the article number " 20 " in the time zone T 1 to T 2 and the subtotal "V 13,200 " in the same zone is read out into the X register 78 a The previous sales contents, e g.

"Y 13,200 " of the X register 78 a and the sales data, e g "Y 700 ", stored in the Y register 78 b are transferred through the gate circuit 70 to the add/subtract circuit 71, in which they are added together The article number " 20 " in the time zone T 1 to T 2 is also supplied to the adder/subtraction circuit 71 where it is subjected to a "+ 1 ' operation Then, the total amount "Y 13,900 " in the time zone T 1 to T 2 and the article number " 21 " in the same time zone are loaded into the 17th address of the memory device 47.

The detailed data flow during the step e of Figure 6 A is shown in Figure 6 B In a step el, it is determined whether " 1 " is set in the first bit bl or not, i e the contents of Flag 2 is 0001 or not If a " 1 " is set in the bit bl, step e 2 loads the chip enable signal CE 1 into the X register 78 a and the row address RA= 17 and the column address CA=B 1 are also loaded into the A register 83 When in the step el, it is found that " 1 " is not set in bit bl, a step e 3 is executed to determine whether binary " 1 ' is set in the second bit b 2 or not If " 1 " is set in bit b 2, a step e 4 loads the chip enable signal CE 1 into the X register 78 a and sets the row address RA= 17 and the column address CA=B 1 in the A register 83 If, in step e 3 " 1 " is found not to be stored in bit b 2 a further step e 5 is executed This step loads the chip enable signal CE 1 into the X register 78 a and the row address RA= 19 and the column address CA=B 1 into the A address register 83.

Figure 8 B illustrates the case when the sales processing is made at 11:50.

When the sale being processed is made after 12:00, for example, at 12:01 as shown in Figure 8 C, it is totalized and the receipt is issued, the locations of the 18th row and the columns B 6 to B, of the memory 100 are specified since, at this time, the second bit b 2 of the Flag 2 is set at " 1 " and therefore the contents of this flag is " 0010 " If this sale is the first to be made after 12:00, the contents of the 18th row and the columns B 6 to B, are all " O " Accordingly, the article number " 1,, is loaded into the memory locations at columns B 6 to B, and the 18th row for the time zone T 2 to T 3 together with the total amount in the same time zone, which is the sale amount at this time, for example, "Y 450 " After this, data totalization will be continued with respect to the memory locations of the 18th row and the columns B 5 to B, of the memory 100 until time T 3, i e 14:00.

Aftet 14:00, data will be totalized with respect to the memory locations of the 19th row and the columns B 6 to B, until time T 4, i.e 17:00 in this example In this manner, the amount of money and the numbers of articles are totalized and then the operation advances to a step g In this step, this sales data (the above-mentioned total amount) stored in the Y register 78 b in the register group 77 is transferred to the X register 78 a and then to the I/O controller 31, where it is stored in the output buffer register (not shown) The I/O controller controls the printing section 33 on the basis of the data stored in the output buffer register and prints the data, as shown in step h of Figure 6 In the step h, the printing shown in Figures 9 A and 9 B is made in addition to the data printing At the end of data printing, a serial number is printed, as shown in step h, of Figure 9 A At this time, the microprogram read out from the control section 62 sets the chip designating data to specify the memory device 47 in the X register 78 a.

Then, the microprogram of the control section 62 transfers an operation instruction to the chip designating circuit 82 Upon receipt of the operation program, the chip designating circuit 82 reads out the chip designating data from the S register 78 a to produce the chip enable signal CE 1 and to specify the memory device 47 Then, the control section produces an address code to specify the memory locations of the 17th row and the columns B 8 and B 7 of the memory unit 91 The address code then is converted into a serial code by the code generating circuit 67 The serial code thus converted is then transferred to the add/ subtract circuit 71, through the gate circuit The address data outputted from the add/subtract circuit 71 is loaded into the A register 83 where it is converted into parallel data to be fed to the address designating circuit 92 A read instruction fed from the control section 62 through the instruction 1 594 240 decoder 69 is set in the addressing circuit 92.

As a result, the contents of the memory locations of the 17th row and or columns B 8 and B 7, i e the serial number, for example, " 3400 ", is read out from the memory unit 91 and the consecutive number is then applied to the X register 78 a through the AND gate and the OR circuit 76 The serial number read out from the X register 78 a is transferred to the output buffer register in the I/O controller 31, together with "No" shown in Figure 9 A The data set in the output buffer register controls the operation of the printing section 33, to print the serial number "No 3400 " on the receipt The serial number " 3400 " read out into the X register 78 a is applied to the add/subtract circuit 71 where it is subjected to the "+ 1 " operation.

Through this addition, the serial number becomes " 3401 " which is in turn loaded into the memory locations of the 17th row and the columns B 8 and B 7 of the memory unit 91.

When the printing of the serial number is completed, the CPU 34 issues a paper feed instruction to the I/O controller 31 As a result, a paper feed appropriate to the N columns of the receipt is executed as shown in a step h 2 in Figure 9 A.

Then, the CPU 34 transfers a stamp printing instruction to the I/O controller 31 so that "YOUR RECEIPT THANK YOU" is printed, as shown in step h 3 in Figure 9 A.

When the stamp printing is completed, the operation shifts to the date printing mode so that the CPU 34 issues a chip designation to the clock circuit 48 and the address of the date to the memory 100 That is, the CPU 44 transfers a code designating the clock circuit chip 48, e g " 0010-' to the X register 78 a, and at the same time issues an operation instruction to the chip designating circuit 82, through the control section 62 Upon receipt of the operation instruction, the chip designating circuit 82 reads out the chip designating code " 0010 " from the X register 78 a and produces the chip enable signal CE 2 to designate the the clock circuit chip 48 Then, the control section 62 transfers the address data to the address register 83, through the gate circuit 70 and addcr/subtraction circuit 71 The address data specifies the memory locations of 4th row and the columns B 6, B 5 and B 4 The address data is transferred from the address register 83 to the address designating circuit 101 in the clock circuit 48 In the address designating circuit 101, a read instruction is set which is fed from the control section through the instruction decoder 69 As a result, the date data, for example, if it is November 20, 1976, " 76 11 20 ' is read out from the memory locations of 4th row and of columns B, B 5 and B 4 of the memory 100 as shown in step h 5 of Figure 9 B The date data read out is transferred to the X register 78 a, through the gate circuit 109, the AND circuit 75 and the OR circuit 76 The data read out into the X register 78 a is transferred to the output buffer register in the I/O controller, together with the segment code, as shown in a step h 6 of Figure 9 B The I/O controller 31 controls the printing section 33 in accordance with the data stored in the output buffer register to print the date, as shown in a step h 7 in Figure 9 B The receipt issuing operation is made in the abovementioned manner The stamp printing "YOUR RECEIPT THANK YOU" and the printing of data are made for the succeeding receipt As shown in Figure 9 B, the receipt is torn off between the consecutive number printing with N rows space and the stamp printing Therefore, the stamp printing and the date printing are positioned at the upper portion of the receipt issued.

In the above-mentioned embodiment, the time and date are set up by setting the control switch 20 to the Pr mode and alternatively depressing the appropriate amount keys 11 and the non-add key "#".

However, year, month, day, hour, minute, and second may be consecutively inputted by using the amount key and finally actuating the non-add key "#", for the same pulse When the totalizing time is set up, hour and minute may be continuously inputted by the amount keys 11 and then operating the totalizing key To 19 b, unlike the abovementioned example Since the totalizing key T( 19 b is separately provided, it may be arranged to be always operable irrespective of the mode set by the control switch 20.

If the totalizing key To 19 b is desired to be replaced by another key, the ST key 17 or the like may be used under the condition that the control switch 20 is switched to the Pr mode, for example.

In the above-mentioned embodiment the memory unit 91 has a plurality of memory locations for storing a sales item total in connection with a time zone The memory locations are shown in the sales item total between times T 1 and T 2, T 2 and T 3, and T 3 and T 4 The sales item total is cumulatively stored in one memory location according to the result of comparison by the comparator and according to the flow chart of Figure 6 A when an entry is made by the operation of the "cash/amount tendered" key The memory unit 91 can be so constructed that it has a plurality of memory locations for storing a department sales item total in connection with the time zone The department sales item total is cumulatively stored in one memory location by the same operation as in the flow chart of Figure 6 A.

This is effected according to the result of the comparison made by the comparator, when an entry for a department is effected by the 1 594 240 operation of the department key 12.

The memory unit 91 can also be so constructed that it has a plurality of memory places for storing individual transaction amounts in connection with the time zone.

The transaction amount is cumulatively stored in one memory location by the same operation as in a flow of Figure 6 A This storing is done according to the result of the comparison made by the comparator.

The above-mentioned memory unit 91 can also be so constructed that it has a plurality of memory locations, for storing a clerk sales amount in connection with the time zone The clerk sales amount is stored in one memory location in connection with a clerk designated by a clerk key 15 This storing is done according to the result of the comparison made by the comparator and according to the Figure 6 A flow chart each time the sales amount is entered.

The total and count may be totalized not only within time but also within the date In this case, the memory location for storing the total and count of the preset date is provided and every time the registration is made, the preset date is compared with the date of that registration to accumulately store the total and count in the given memory location.

Reference is directed to our co-pending Application No 54035/77 (Serial No.

1594239) from which the present application is divided.

Claims (2)

WHAT WE CLAIM IS:-

1 An electronic cash register comprising a keyboard including data input keys, a central processing unit coupled to said keyboard, a memory device coupled to said central processing unit and having a memory location for storing accumulated sales amounts, a time memory coupled to said central processing unit and having a memory location for storing year, month and day data, a timepiece coupled to said time memory to update the year, month and day data, and printing means coupled to said time memory to print the year, month and day data stored in said time memory.

2 An electronic cash register according to claim 1 wherein the timepiece comprises a reference oscillator and means responsive thereto for updating the time memory, and wherein the time memory and means for updating the time memory are constructed on a single chip.

A.A THORNTON & CO, Chartered Patent Agents, Northumberland House, 303/306 High Holborn, London, WC 1 V 7 LE.

Printed for Her Majesty's Stationery Office, by Croydon Printing Company Limited Croydon, Surrey, 1981.

Published by The Patent Office 25 Southampton Buildings, London WC 2 A l AY, from which copies may be obtained.