JPS5939062B2 - electronic cash register - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic cash register which has an internal clock function and which operates an alarm at a preset time.

Conventionally, there are cases in which charges differ only during a certain period of time from other times, such as early morning service hours at a coffee shop or the like, or charges at night or late at night.

Further, for example, in supermarkets and the like, operators of electronic cash registers are changed at predetermined intervals.
However, conventional electronic cash registers do not have a clock function, and are unable to notify when the above-mentioned special fees or operator change times arrive. For this reason, the operator must always be aware of the current time, which is extremely troublesome. The present invention has been made in view of the above points, and is equipped with an internal clock function and an alarm function that notifies the operator when a preset time has been reached, thereby reducing the burden on the operator. The purpose is to provide a cash register.

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows the configuration of the front operation unit 10 of the electronic cash register, where 11 is a ticket, 12 is a department key for specifying the department for each product, 13 is a clear key for clearing the number data, and 14 is a time and date key. Keys to specify date "#", unit price "5", correction "revise", currency exchange "change", 15 is % key to instruct percentage calculation, 16a, 16b are % key 15 "publication "1", i.e. Key to instruct premium and discount, 1Ta
For example, is the SV key for setting the service time zone, 17b is the T key for setting the time zone for aggregation, 17c is the AL key for setting the alarm time, 18 is the person in charge switch indicating the person in charge, 19 is the deposit, withdrawal, Key to indicate sales and inventory, 2
0a and 20b are keys for instructing credit sales such as credit or credit sales, 21 is a subtotal key for calculating addition or total, and 22 is a key for calculating total or change and issuing a receipt. In addition, 23 is a master switch that can be set to "OFF", "Preset", "
Switch and select the functions of ``Registration'', ``Inspection'', and ``Payment''.
``OFF'' in the master switch 23 is when the cash register is not in use, ``PRESET'' is to preset data, ``REGISTER'' is to perform normal money collection operations, and ``INSPECTION'' is to destroy stored data. When checking without checking, "Payment" is used to perform payment and clear the stored data. In order to summarize the various keys, all keys except tick key 11, department key 12 and master switch 23 are set to function key 2.
It is called 5. Furthermore, 24 is a zeta display section, which can display the amount and product category. Next, the internal configuration of the present invention will be explained with reference to FIG.

31 is an I/O (input/output) controller, and this I/O controller 31 controls the keyboard 32 and the printing section 33.

A sampling signal is given to the keyboard 32 from the I/O controller 31, and when a key operation is performed on the keyboard 32, the sampling signal is selected according to the operation key and sent to the I/O controller 31 as a key input signal. Sent. The 1/0 controller 31 is connected to an arithmetic processing unit (hereinafter abbreviated as CPU) 34, and when a key input signal is given from the keyboard 32, it is stored in an internal I/0 buffer and then sent to the CPU 34.
Transfer to. In addition, the I/O controller 31
When print data is given from 34, this print data is temporarily stored in the I/0 buffer and then sent to the driver 35 of the print section 33 for printing. The printing section 33 includes a receipt printer 36 and a journal printer 37. The printers 36 and 37 include print drums 38 and 39 coaxially coupled to each other.
, 39, receipt paper 41 and journal paper 42 are arranged, respectively. In addition, the printing drum 38,
On the side of 39 are receipt paper 41 and journal paper 4.
A printing hammer (not shown) is disposed so as to face each other with 2 interposed therebetween. Further, the printing drums 38, 39 are driven by a motor 43, and the printing drums 38, 39 are driven by a motor 43.
When 39 rotates once, receipt paper 41 and journal paper 42 are fed by one line. A rotational position detector 44 is provided at one end of the printing drum 38, and detects the rotational position of the printing drums 38, 39.
A detection signal from the rotational position detector 44 is sent to the I/O controller 31 via an amplifier 45. The I/O controller 31 matches the rotational position detection signal with the print data and sends a drive signal to the driver 35 to drive a predetermined print hammer. The receipt paper 41 is led out of the electronic cash register according to the printing operation, and the printed portion can be cut off after printing is completed.

Further, on the receipt paper 41, for example, ``Thank you for your purchase'' is printed in stang. On the other hand, the journal paper 42 is used to record sales, and the same information as the receipt is printed thereon, and is wound around a shaft 46 inside. In addition, the above C
The PU 34 includes a memory (RAM) 47 and a clock circuit 48.
is connected.

A DC power supply 49 and a reference frequency oscillator, such as a crystal oscillator 50, are externally connected to the clock circuit 48. The memory 47 and the clock circuit 48 are each composed of one chip, and the chip enable signal CE from the CPU 34
The chip is specified by l, CE2, and the read/write
A read or write operation is designated by write signal R/W. The clock circuit 48 has a function of obtaining date information as well as time information, and this information is read out to the CPU 34 as necessary. When issuing a receipt, the CPU 34 reads date information from the clock circuit 48 and prints the date. Moreover, the time information of the clock circuit 48 is
Used as time segmented data when performing hourly aggregation. The CPU 34 performs a receipt issuing process in accordance with key input signals from the keyboard 32, and the processing data at that time is sent to the I/O controller 31 as print data as well as to the display unit 24 via the display driver 51. displayed. moreover. The clock circuit 48 outputs an alarm signal in accordance with a command from the CPU 34 when a preset time is reached, and sends it to the amplifier 52.

An alarm speaker 53 is driven by the output of the amplifier 52. FIG. 3 shows details of the clock circuit 48.

This clock circuit 48 includes a memory 60 that stores preset time data and the like in addition to current day, month, and day data and current time data. This memory 60 is connected to the CPU 34
The address is specified by the upper 1 and lower 1 address data set in the register 61 from C.
A read or write operation is specified by an R/W command from the PU 34. In addition, the register 61 has the following information:
Address data and an R/W command are given from a control unit 59 provided in the clock circuit 48, and the address of the memory 60 is specified. The serial data output from the memory 60 is sent to the serial/parallel conversion circuit 56 via the gate circuit 55 and converted into parallel data. The parallel data output from the serial/parallel conversion circuit 56 is applied to the set terminal S of the flip-flop 58 via the OR circuit 57, and the output of the flip-flop 58 is sent as an alarm signal to the amplifier 59 as described above.
The flip-flop 58 is reset by operating a reset key (for example, the AL key 17c) provided on the keyboard 32. Further, data output from the memory 60 is sent to a buffer 63 via a gate circuit 62 and also to a gate circuit 64.

This gate circuit 64 includes the output of the buffer 63, a one-second pulse for timing from the timing generation circuit 65, and a control section 59.
A code signal is given from The timing generating circuit 65 operates according to the reference signal from the crystal oscillator 50, and generates timing signals specifying the operation timings of various parts in addition to the one second pulse. Then, the gate circuit 64
selects an input signal according to the control signal from the control section 59 and supplies it to the adder circuit 66. This adder circuit 66 performs an addition or subtraction operation according to a command from the control section 59, and sends the result to the memory 60 via a gate circuit 67.
Give it as write data to. Further, the addition/subtraction results and the carry signal output from the adder circuit 66 are, for example, 6
The data is sent to a judgment circuit 68 which judges whether the storage format is 0-base or 24-base and whether the time matches. The judgment result of this judgment circuit 68 is sent to the control section 59. Further, data read from the memory 60 is sent to the CPU 34 via a gate circuit 69. The operations of the gate circuits 67, 69 and the register 61 are controlled by a chip enable signal CE2 from the CPU 34. In addition, the gate circuit 5
5, 62, 64, 67 and adder circuit 66, judgment circuit 6
8 is controlled by a signal from a control section 59. In addition,
The gate circuit 67 is controlled by the chip enable signal CE2 and a signal from the control section 59. Thus, the memory 60 has four rows and eight rows, for example, as shown in FIG. 4a.
Each column B1 to B8 is designated by a lower address L, and each row is designated by an upper address U. In the first to third rows, each two columns are used as one unit, that is, B8-B7, B6B5, B4-
Each two columns of B3 and B2-B1 are considered as one unit [
It is designed to store time data in hours and minutes. In this case, the first line contains time data T1~
The second line contains alarm time data ALl~AL4,
The third line contains time data SVl to SV for service time.
It is divided so that 4 is memorized. The above time data T1
~T4 specifies the sales aggregation time range, time data ALl~AL4 specifies the alarm time,
The time data SV, to SV4 specify service times such as discounts. Also, in the fourth row of the 6 memory 60, B
8. In the B7 column, the flags Flagl and Flag2 that indicate the match between the current time and the specified time, and in the B6, B5, and B4 columns, the current day's [Year], "Month", and in the B3, B2, and B1 columns. Memorizes the time ``hours'' [minutes] and ``seconds.'' The fourth row, B7 column of the memory 60 that stores the flag Flag2 stores the first bit b1 when the current time matches the alarm time ALl, and the second bit b1 when the current time matches the alarm time AL2, as shown in FIG. 4b. One bit is set in bit B2, the third bit B3 is set when the alarm AL3 is matched, and the fourth bit B4 is set when the alarm time AL4 is matched. Further, in the fourth row and column B8 of the memory 60 that stores the flag Flagl, the first to fourth bits b1 to B4 are used as a counter for specifying alarm times ALl to AL4, as shown in FIG. 4C. Ru. Next, the operation of the present invention configured as described above will be explained.

The clock circuit 48 performs a timekeeping operation according to a reference signal given from a crystal oscillator 50. That is, the reference signal output from the crystal oscillator 50 is output from the timing generation circuit 6.
5, and this timing generation circuit 65 outputs a one-second pulse and various timing pulses. The 1 second pulse outputted from this timing generation circuit 65 is applied to an adder circuit 66 via a gate circuit 64. On the other hand, the control unit 59 specifies the fourth row of the memory 60 and reads out all of its contents to the buffer 63 via the gate circuit 62. Then, the gate circuit 64 selects the output of the buffer 63 and the 1-second pulse from the timing generation circuit 65 and adds them to the adder circuit 66, thereby adding the 1-second pulse to the second data in column B1. The output of this adder circuit 66 is the gate circuit 67
The data is sent to the memory 60 via the memory 60 and written in the fourth line. In this way, the contents of the fourth line of the memory 60 are constantly rewritten. Further, the output of the adder circuit 66 is sent to a determination circuit 68, which determines whether the addition result has reached a predetermined value, and the control operation of the control section 59 is performed based on the determination result. For example, by adding the above seconds, B in the fourth row
When the first column, that is, the second data reaches 60 seconds, this state is determined by the determination circuit 68, and the control unit 59
The contents of the row B2 column, that is, the minute data, are incremented by [+1], and the second data is cleared. Similarly, minutes → hours → days →
Carry control is performed in the order of month → year, and timekeeping operations are performed for the time and year, month, and day. Furthermore, when starting the clock circuit 48, the correct date and time are set. This setting operation changes the Masudas iTutch 23 in Figure 1 to "
In this state, enter data in the order of year → month → day → hour → minute → second by operating the numeric keypad 11. Each time you enter each unit zeta, press the time and date keys. Operate "#" 14. The above key operations, that is, data input from the keyboard 32, are sent to the CPU 34 via the 61/O controller 31 and set in 6 input/output registers (not shown). The input data stored in this input/output register is sent to the clock circuit 48 and written to the fourth row, B6 column to B1 column of the memory 60 via the gate circuit 67. In this way, the memory 6 of the clock circuit 48
Year, month, day, and time data are written to 0, and thereafter the timekeeping operation as described above is performed. Also, when writing time data for time aggregation, time data for service time, and time data for alarm into the memory 60, the SV key 17a. T key 1
7b. While operating the AL key 17c, the SV key 17a
．． After operating the T key 17b or AL key 17c ("
The time data can be written in a predetermined position in the memory 60 by inputting time order designation data using the numeric keypad 11 (after inputting "minute").

For example, after inputting time data in "hours" using the numeric keypad 11, operate the AL key 17c, then input time zeta in "minutes" manually, and after operating the AL key 17c, press the AL key 17c.
When the time order designation data "1" is inputted by 1, the first row B7B, column of the memory 60 is designated and the "hour" and "minute" of the alarm time data AL1 are written. When performing processing, set the master switch 23 to the [Register] position, and normally press the number key 1.
1. Manually calculate the price of sold products.

Then, when you operate the department key 12 to which the product belongs,
The above input data is sent to the printing section 33 and is sent to the receipt paper 4.
1 and the journal paper 42, and the CPU 3
4 and the display driver 5t on the display unit 24, and are sequentially accumulated within the CPU 34. Furthermore,
Data in the memory 47 corresponding to the address specified by the department key 12 is read by the CPU 34 and added to the manually entered data, and the result is written to the memory 47 at the specified address. In this way,
The same operations as described above are repeated by operating the numeric keypad 11 and the department key 12 for each product sold. After inputting the prices of all sold products and specifying the department, the user operates the key 22 to obtain the total or change and issue a receipt. As a result, the total amount accumulated by the CPU 34 as described above is displayed on the display section 24, and is also sent to the printing section 33 via the I/O controller 31 and printed on the receipt paper 41 and the journal paper 42. In addition, when processing is performed using departmental preset data preset for each department as described above without inputting the price of the product using the numeric keypad 11, simply operating the department key 12 allows you to enter the product price for this department. The same process as described above is performed using the preset data of the address corresponding to the key 12 as input data. Next, the alarm operation will be explained with reference to FIGS. 1 to 4 and FIGS. 5 and 6.

When an alarm operation is to be performed, as described above, by operating the numeric keypad 11 and the alarm time setting AL key 17c, the alarm time data AL1 to AL4, such as the operator change time, is stored in the fourth line of the memory 60. Set.

FIG. 6 shows alarm time data AL1 in the memory 60 at 10 o'clock, AL2 at 12 o'clock, AL3 at 14 o'clock,
This shows the state when the current time reaches 12:00 when data is set at 16:00 as AL4. Therefore, the clock circuit 48 receives the alarm time data A.
It constantly compares L1 to AL4 with the current time, and outputs an alarm signal when any of the alarm times coincides with the current time.The operation will be performed according to the flowchart shown in FIG. 5 below. The control section 59 performs operation control as shown in the flowchart of FIG. 5 by utilizing the idle time of the timekeeping operation control. First, as shown in step A of FIG. 5, the fourth row of the memory 60 is The flag Flagl in
Clear the contents of. Next, proceed to step B and perform the above F.
It is determined whether the content of lagl is "4". That is, by addressing the fourth row B8 column of the memory 60,
The contents of agl are read and applied to the adder circuit 66 via the gate circuit 64. At this time, the adder circuit 66 is given a code signal of numerical value "4" from the control section 59 via the gate circuit 64, and also given a subtraction command to "Flagl-4".
]. Then, this subtraction result is sent to the judgment circuit 68 to judge whether it is "O" or not. Based on the judgment result of this judgment circuit 68, the content of Flagl is "4".
You can know whether or not it is, and then proceed to the next step. At this point, the contents of Flagl are cleared and "
0" (), so the judgment result of step B is NO.
Then, proceed to step C. In this step C, the contents of Flagl are read out from the memory 60 to the adder circuit 66, and a code signal of "1" and an addition command are given to the adder circuit 66 from the control section 59 to change the contents of Flagl to "
1” is added. When this step C is completed, as shown in step D, addresses are specified for the fourth row B3 and B2 column of the memory 60, and the time data "hour",
[minutes] is read out to the buffer 63 via the gate circuit 62 as shown in step E. Then proceed to step F.
The second row B8-B1 of the memory 60 according to the contents of lagl
The column is addressed and its contents, that is, alarm time data AL, -AL4, are read out and added to the adder circuit 66. At this time, the buffer 6 is added to the adder circuit 66 in step E.
3 is supplied with the current time stored in the alarm time data, the current time is subtracted from the alarm time data, and the result is sent to the judgment circuit 68, which makes a judgment as to whether or not it is "o". That is, as shown in step G4, it is determined whether the alarm time data read from the memory 60 and the current time temporarily stored in the buffer 63 match. At this point Fla
Since the content of gl is "1", alarm time data ALl is compared with the current time.

Now, as shown in Figure 6a, the current time is 12:00.
If the alarm time data AL1 is 10:00, the judgment result at step G is inconsistent, and the process returns to step B. Therefore, no writing is performed to Flag2, and the contents of Flag2 are held in the 0' state. FIG. 6b shows Flagl. at this time. Current time read out to buffer 63, alarm time data ALl, Flag2
This shows the state of The same goes for step B above.
-G operation is repeated, and a match between the current time and the alarm time data AL1 to AL4 is detected. Then, when the current time and the alarm time data AL1 to AL4 are compared and the two times match, the process advances from step G to step H, and Flag2 is set to "1" according to the contents of Flagl. For example, in Step C, “Flagl+”
Due to the addition operation of the moon, Flagl as shown in Figure 6c.
When the content of ``2'' is specified and the alarm time data AL2 is specified, the content of AL2 is 12:00, which matches the current time 12:00 read out to the buffer 63. Therefore, the judgment operation in step G detects that the alarm time AL2 matches the current time, and the process proceeds to step H, where the B2 bit of Flag2 is set to ``1''.
Figure 6d shows the buffer 63 when Flagl is [4].
, AL4, and F1ag2. When the checks on AL1 to AL4 are completed using Flagl in this manner, the content of Flagl becomes "4", the determination result at step B becomes YES, and the process proceeds to step I.

In this step I, Flag2 in the memory 60 is read out to the serial/parallel converter circuit 56 via the gate circuit 55, and the flip-flop 58 is set by the output of the serial/parallel converter circuit 56. That is, the alarm time data AL
If any of l to AL4 matches the current time, Flag
Since 8F' is set in any of the bits b1 to B4 of 2, the flip-flop 58 is set by the set signal. When flip-flop 58 is set, its output signal is sent to amplifier 52, which drives speaker 53. The driving of the speaker 53 causes an alarm sounding operation to notify the operator that the current time has reached a preset time. In order to stop the above alarm sounding operation, the flip-flop 58 is reset by operating the reset key on the keyboard 32. Thereafter, alarm operations are performed for the alarm time data AL, -AL4 in the same manner.

In the above embodiment, a speaker is used to perform the alarm operation, but the sounding means is not limited to this, and any sounding means may be used as long as it generates sound by electro-mechanical vibration conversion. There is no limitation, and it may be performed optically.

Further, in the above embodiment, the alarm setting is performed by the operator's operation, but for example, the clock circuit 48
The flip-flop 58 may be automatically reset after the alarm operation has been performed for a certain period of time using the clock signal.

As described above, according to the present invention, it is equipped with an internal clock function and an alarm function that notifies the operator when a preset time is reached. It is possible to notify the time period of special charges, operator change times, etc. Therefore, the operator does not need to always pay attention to the time, and the burden on the operator can be reduced.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention; FIG. 1 is a diagram showing the arrangement of keys on the front operation section of an electronic cash register, FIG. 2 is a block diagram showing the overall circuit configuration, and FIG. Figure 3 is a circuit diagram showing details of the clock circuit in Figure 2, Figure 4A,
5 is a flowchart for explaining the alarm operation, and FIG. 6 is a state diagram showing the flag and buffer contents at the time of the alarm operation. 10...Operation unit, 11...Numeric keypad,
23... Master switch, 31...
I/0 controller, 32...Keyboard, 3
4...CPU, 47, 60...Memory, 48...Clock circuit, 52...Amplifier, 56...Serial-to-parallel conversion circuit, 68...
・Judgment circuit.

Claims (1)

[Claims] 1. In an electronic cash register that performs various cumulative calculations on sales items, a timekeeping circuit, a memory that stores preset alarm time data, and a comparison between the set time data of this memory and the timekeeping data of the above-mentioned timekeeping circuit. 1. An electronic cash register comprising: a coincidence detecting means for detecting a coincidence; and a notifying means for performing a notifying operation based on a coincidence detection signal obtained by the means.