JPS58112167A - Data totalizing system - Google Patents

Abstract

PURPOSE:To confirm easily the total of sales data, by designating plural storage regions within a storage means that stores the input data for each sort and totalizing and delivering the data of the designated storage regions. CONSTITUTION:A timing signal KP is fed to an input part 1 from an I/O port 2. The port 2 includes an input buffer IB, a display buffer HB and a print buffer PB. The buffers HB and PB are connected to a display part 3 and a pring part 4 respectively. The port 2, a total memory 6 and a timepiece circuit 7 are connected to a CPU5 via a data bus DB and an address bus AB. The fed data are stored in the memory 6 based on the sort. The stored data are read out by designating the storage region and then delivered in the form of the total of the sales data of the prescribed plural time bands or the total of the sales data of specific plural departments.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data accumulation method for reading and accumulating a plurality of data stored in one category.

In general, electronic registers that have a prefectural accounting function for each hour of the day have Yllll! It is divided into time zones, and the data sold within the valley is stored in storage areas for each time zone. If it is desired to check the data in the storage area for each time period, this can be done by specifying the inspection mode on the VC and printing the data for all time periods on recording paper. However, when you want to know the total sales from one time period to another among the plurality of time periods, conventionally, the recording paper on which data from all the time periods are printed is used. There was a problem in that the operator had to manually output the sales total data.

This invention was made based on the above-mentioned circumstances.In order to achieve its purpose, it is possible to cumulatively output data stored in a plurality of arbitrarily specified areas among a plurality of data stored by classification. It is to provide a data accumulation method.

The following is a partial embodiment of the present invention shown in FIG. KP is selected according to the operation key, and the key input signal KI is inputted as a key input signal KI for I10)2. In addition to the input buffer IB, the I/(J boat z contains the display buffer H
B. The print buffer PB is connected to the display section 413, and the display buffer HB is connected to the display section 413, and the print buffer PB is connected to the width section 4.

The display unit 3 displays amount data and the like V* in accordance with the digit signal DG from the I10 port z and the segment signal SG obtained by decoding the data in the display buffer HB.

The printing section 4 receives a printing position signal T P@I / (J boat! IC) from a printing drum (not shown) provided therein.
From the I/Ll boat 2, internally, it is sent to the printing section all 1 MDt printing school 4, which is generated by the coincidence of the printing position signal TP and the data in the printing buffer PB, and the amount data is recorded on the paper. to be printed. :' Further, reference numeral 5 is a CPU, and to this CPU 5 are connected a data bus DB, an address bus ABy, a total memory 6, and a clock circuit 7. and,
The CPU 5 outputs the signal No. 17/WM to the J port 21, the total memory 6, and the clock circuit 7, and also outputs the chip designation signal C8I to the total memory 6, and the chip designation signal C8■ to the clock circuit 7, respectively. , CPU1s and I10
Data is exchanged between the boat 2 and the total memory 6, and current time data is sent from the clock circuit 7 to the CPU 5. In addition, the clock circuit 7t-r updates the current hour and minute data every 1 second and prepares for it 7;l:
The current hour and minute data is stored in the TM register.

Figure @2 shows the operation panel of the input section 1, which includes number keys 8a, departmental orders 8b, function group 8C1 time zone keys 9 for specifying time zones, etc. A mode switch 10 for specifying various operation modes such as ",""inspection," and "payment" is provided.

In addition, the third column shows the format of the time zone memory provided in the total memory 6, and the storage area M (0)...M (1B
) corresponds to the 7 o'clock floor, 8 o'clock, 8 o'clock to 9 o'clock, etc.
・.

i! The total sales data for each customer input in each time period from 2:00 to 23:00 is accumulated. In addition, total memory 6
Vcd sales data is classified and stored by department; transaction data such as departmental memory, cash sales, lending sales, etc. are stored by classification.
c) The transaction-specific memory that is stored has been overlooked.

FIG. 4 shows a detailed circuit configuration diagram of the CPU 5, and reference numeral 11 in the figure is a ROM in which various microinstructions are stored. This ROMII outputs an address signal to the addressing circuit 12 via line tl, and also outputs a line t! ? via opcode and ROMII
The control circuit 13 sends a next address signal specifying the next address of
Output to ``f'' too.

=-Sait1-yen And the next address signal is the control circuit 1
3 to RUMxx via line tsyg (1
Addresses the next microinstruction.

In addition to specifying the address of BIAMI 4, the address specification circuit 12 also specifies the address (I/
(The addresses of the J port 11 total memory 6 and clock circuit 7 are specified, and when the address specification is completed, the IC outputs a completion signal Y to the control circuit 13 via line t4.

m RAM14, c B X % Y *
nt Lu ” m * F *8
Each register is provided, and the data read from this IltIAM 14 is output to the arithmetic circuit 15.

It is also sent to I10 port 2 and memory 6 via data bus Dt3v. The arithmetic circuit 15 performs various specified arithmetic operations, and the arithmetic results are sent to R via line t1%'.
It is input to AM14.

The control circuit 13 reads input 1 or operation code wW4, and outputs a designation signal for designating addition or subtraction to the arithmetic circuit 15 via line t6v. It was.

Control circuit 13tl! It outputs an R/W signal to the LAM 14 (via the line T and Y), and changes the next address according to the data input via the line and the presence or absence of a carry. Sara K f! III A signal designating countdown is output to the address count up t in the address designation circuit 12 via the line L- to the # circuit 13. In addition, the control circuit 13 outputs the R/W signal, chip designation signals CaI, and C3lf.

Next, the operation of this invention will be explained. first.

In the state where the "mode switch 1ovr setting" mode is designated, the time 7 o'clock for starting the cumulative total Y for each zone is input, and this start time "7" is stored in the 8 register of the RAM 14. After this, mode switch 1
oy Specify "development" mode and check sales data? When inputting the current/deposit V*-V operation, the total sales data for one customer is accumulated in the storage area of the time slot memory 6 that includes the time at the time of the operation.

On the other hand, when the power switch of the electronic register is turned on, the operation according to 70- in FIG. ! Wait until there is a key operation in step 1, and if it is determined that there is a key operation, step 8
s iC, move. In step 8g, operation key r1
A judgment is made as to whether or not the time zone key is 9, and the 1 hour zone $
If it is determined to be -9, the process moves to step 8m. Step 8-
In step S4, it is determined whether the mode switch 10 is set to the "inspection" mode, and if the determination is YES, the process moves to step S4. In step 5aeC, the numeral data in 2 registers of the RAM 14 that stores the data entered by the 19 digits in the operation of the numeric key group Sa in the input section 1 is read out, and this numeral data is stored in the 8 registers. A judgment is made as to whether or not the start time data is large, and if it is judged as negative, the process moves to step 8. If it is determined in step 8avc that the mode is not "inspection", the process also moves to step 8@, where the operated key is treated as an error, and then the process moves to step St. In step S4, if the number data of the two registers, that is, the designated time data, is greater than the start time data, the process moves to step SsK. It is stored in step S and a judgment is made as to whether it is μ or not, and if it is judged as YEI, Sde Tsubu 8
Move to ma. In the execution of step 8, the start time data in register 8 is subtracted from the specified time data in register 2, and the difference is written to the nl register of 8mm M14 as address data that specifies a storage area of 6m in total for each time zone. It will be done. Next - move to step 8m p, RIAM1
Data rlJ indicating that the time period key to be operated next time is an even-numbered operation is written in the 40F register, and then the process returns to step 81.

In step S, each of the same registers is rOJ.
If it is determined that this is not the case, the process moves to step S-.

In the execution of step S, data rOJ indicating that the time period key to be operated next time is the odd-numbered operation is written in the F register. Next, the process moves to step S10, where the start time data in the 8th register is subtracted from the specified time data in the 2nd register, and the difference is written into the RAM 140nl register as address data specifying the storage area of the total memo 176m for each time zone. Then, the process moves to step Su, where it is determined whether the address redundancy data of the nl register is greater than the address designation data of the nl register, and if it is determined no, it is determined YES at step 8tmvc. and step 8ssiC
*Iru. In step 8sm, the addressing data of the nl register and the addressing data of the i1m register are exchanged with each other, and then the process moves to step 8ss. In the execution of step 8ss, the total memo 136 m by time period specified by the addressing data of the nl register is
The total sales data stored in storage area M (old) of RA
Transferred to the X register of M14. Then step St
Move to execution of a? The total sales data of %X register and the contents of the X register are added, and the result of this addition is written to the X register. Next, proceed to the execution of step Sts,
Il'' is added to the addressing data of the old register. Next, step 8s@ is executed 1c11), and a judgment is made as to whether or not the addressing data of the nl register is greater than the addressing data of the nm register. If it is determined that the total sales data for the designated time period has not been completed yet, the process returns to step Ss-, and if it is determined that 1YE8, it is assumed that the cumulative total of all sales data for the specified time period has been completed. Return to step 8siC.

If it is determined in step 8m that the operation key is not the time zone key 9, the process moves to step 81m.

According to the operation key πOther key manual processing is executed ft,
After that, return to step 8tK.

If you want to check the total sales data for the time period from 7:00 a.m. to 10:00 p.m., first use the method shown in Figure 6 α).
After inputting the information by pressing t, press the time period key 9. Then, as a result of sequentially executing steps 81 to 84 and 81 to Sm, the start time data "7" stored in the 2nd register is
” to the start time data of the time period aggregation of 8 registers “7
” is subtracted, and the difference rOJ or n1 register is 1111
be included.

Following the above-mentioned key operation, the last time period of the above-mentioned inspection time period is 9:00-10w! When the time zone key 9 is operated one hour later to input the start time tIl of P by operating the number key circle.

Step 81 ws a, 8 m, 8 s to 8 tt in order v
<Execution is completed, after this step 8tsSs・sequentially 3[
As a result of 111 repeated executions, 7:00 to 8:00, 8:00 to 9:00, and 9:00 are stored corresponding to M(1), M(s), respectively, in the storage areas M(su), M(1), and M(s) of 6 time period memories. The total sales data from 10:00 to 10:00 is sequentially read to the X register and accumulated to the Y register.As a result, as shown in Figure 5 ■, the designated mode ``inspection'' is displayed on the recording paper, and the designated mode 11JIWrT
After each printing from 10 hours to 10 hours is performed.

Total sales data from 7:00 to 10:00 in the Y register is printed.

By the way, when inputting the time zone from 7 o'clock to 10 o'clock, 7 o'clock was input first, but 9FI8'l' may also be inputted first, and in this case, the address of n register is specified in step S As a result of mutually exchanging the data "3" and the addressing data rOJ of the nt register, printing is performed on the recording paper in exactly the same manner as described above. By the way, the 5X mentioned above! In the example, we explained the case where the specified time period is a continuous π * scale 0 time period,
A plurality of time slots separated from each other may be arbitrarily designated, and the designated time slots may be accumulated.

In addition, in the above embodiment, the case where sales data stored for each time period is accumulated over multiple time periods was shown, but in this case, for example, multiple departments (of total sales data stored for each department) (For example, when a food category is divided into a plurality of departments and the department is designated, etc.) Y may be arbitrarily designated and cumulatively totaled.

ζ et al. The present invention is applicable not only to electronic registers but also to various electronic devices having means for storing a plurality of classification data Y in a plurality of classification storage areas.

As explained above, according to the present invention, it is possible to designate a plurality of storage areas in the storage means for storing input data by category, and to cumulatively output the data in the specified plurality of storage areas. I don't want to.

For example, the total sales data for multiple time periods,
The total sales data of multiple departments at a certain rate is definitely M! I can do f things.

[Brief explanation of the drawing]

@ Figures 1 to 6 show an embodiment of this invention, and the first
@ is a schematic system configuration diagram of an electronic register. FIG. 2 is a schematic plan view of the input section of the electronic register, and FIG. 3 is a time zone memory format. Fig. 4 is a detailed circuit configuration diagram of the CPU, Fig. 5 is a flowchart, and Fig. 6 (I) (D is a diagram of the key operator i@printing state. l... Input section, 4 ...Printing section, 5...C
P.U. 6...Total memory, 6m...Memo by time zone 1). 9...Time-zone key, 11...ROM,
14...RAM, 1B...Arithmetic circuit. Patent applicant Casio Computer Co., Ltd.

Claims (1)

[Claims] Specify a storage means for storing input data Y in a plurality of storage areas according to classification, and a plurality of storage areas in which data to be read is stored among each storage area within this storage means. an input means for inputting specified data for the input, and a totalizing means for extracting a plurality of data Yd in a storage area specified by the specified data inputted from the input means and totalizing each data. A data accumulation method comprising a command output means for outputting the accumulated data accumulated by the accumulation means.