GB1594067A - Semiconductor devices and their manufacture - Google Patents

Semiconductor devices and their manufacture Download PDF

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Publication number
GB1594067A
GB1594067A GB976878A GB976878A GB1594067A GB 1594067 A GB1594067 A GB 1594067A GB 976878 A GB976878 A GB 976878A GB 976878 A GB976878 A GB 976878A GB 1594067 A GB1594067 A GB 1594067A
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insulating layer
pattern
metallisation
semiconductor
metallisation pattern
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Koninklijke Philips NV
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Philips Gloeilampenfabrieken NV
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)

Description

(54) SEMICONDUCTOR DEVICES AND THEIR MANUFACTURE (71) We, N.V. PHILIPS GLOEILAM PENFABRIEKEN, a limited liability Company, organised and established under the laws of the Kingdom of Netherlands, of Emmasingel 29, Eindhoven, the Netherlands do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The invention relates to semiconductor devices having a semiconductor body comprising an integrated circuit with first and second metallisation patterns. The invention also relates to a method of manufacturing such semiconductor devices.
It is to be noted that where the expression a "metallisation pattern", is used in this Specification and in the appended Claims, said metallisation pattern need not necessarily consist of a metal but, as is known in the semiconductor device art, it may also consist of polycrystalline silicon or similar conductive materials.
It is known to use more than one metallisation pattern in a semiconductor device comprising a plurality of circuit elements arranged in an integrated circuit. In such cases, one metallisation pattern is often not sufficient for the contacting and interconnection of the various circuit elements.
The use of several metallisation patterns may solve this problem. In this case, a first metallisation pattern which is connected to the zones of the semiconductor circuit elements via contact windows is situated on an insulating layer covering the semiconductor body. Over said first metallisation pattern is situated a second metallisation pattern which is separated from the first metallisation pattern by a second insulating layer and is contacted therewith, where necessary, via contact windows.
The disadvantage of this solution is that the resulting surface is generally uneven, and it is difficult to provide the second metallisation pattern in a sufficiently reliable manner in places where crossing connections occur.
Such reliability problems may result from mechanical stresses in the metal or from insufficient layer thickness of the metallisation in these places.
A semiconductor device in which such disadvantages are mitigated is disclosed in German Auslegeschrift DT-AS 20 49 908.
In this device a first electrically insulating layer is situated on the surface of the semiconductor body, and a first metallisation pattern is sunk in this layer so that the surface of the metallisation coincides substantially with the surface of the first insulating layer. The metallisation pattern is sunk throughout the thickness of the first insulating layer and hence contacts the underlying semiconductor zones. On said first insulating layer and said first metallisation pattern are situated a second insulating layer and a second metallisation pattern; the second metallisation pattern is separated from the first metallization pattern by insulating material.
The disadvantage of such a device is that the first metallisation pattern is sunk in the first insulating layer throughout its thickness and hence is in direct contact with the semiconductor body. This means that the shape of said first metallisation pattern is strictly limited by the lay-out of the underlying circuit elements. Such circuit elements generally have semiconductor junctions which are exposed at the surface and which can be short-circuited by an overlying part of the metallisation pattern.
A second disadvantage is that the second metallisation pattern is sunk entirely in the second insulating layer so that an insulated crossing connection between a conductor track of the first metallisation pattern and a conductor track of the second metallisation pattern is not possible as such.
According to a first aspect of the invention there is provided a semiconductor device having a semiconductor body comprising an integrated circuit having a number of semiconductor circuit elements, in which device at least a part of the surface of the surface of the semiconductor body has a first electrically insulating layer, a first metallisation pattern which is sunk in the first insulating layer only over part of the thickness of the first insulating layer, the surface of which first metallisation pattern coincides substantially with that of the first insulating layer, a second insulating layer overlying the first insulating layer and the first metallisation pattern, and a second metallisation pattern overlying the first metallisation pattern and being separated therefrom by insulation material, only the second metallisation pattern contacting at least one semiconductor zone belonging to the semiconductor circuit elements via at least one contact hole in at least the second of the underlying insulating layers.
Thus, in a device in accordance with the invention, the first metallisation pattern can be simply provided in such manner that no undesirable contact occurs with the underlying semiconductor zones, and it is even possible to save a mask step in manufacturing such semiconductor devices. Such undesirable contact is avoided by sinking the first metallisation pattern only over a part of the thickness of the first insulating layer so that the short-circuit problem no longer exists.
Since, in devices in accordance with the invention, the second metallisation pattern overlies the first metallisation pattern and is separated therefrom by insulating material, crossing connections are possible in a semiconductor device in accordance with the invention. Therefore, at least one track of the first metallisation pattern may cross a track of the second metallisation pattern.
In one advantageous form of such a structure the contact windows, via which the second metallisation pattern contacts the semiconductor zones, are provided only in the second insulating layer so that a more compact structure is possible due to smaller tolerances. This can be realised in a particularly advantageous manner when the semiconductor elements directly underlie the second insulating layer and are laterally surrounded by the first insulating layer. Therefore, the first electrically insulating layer may consist of a pattern of electrically insulating material which is locally sunk over at least part of its thickness in the semiconductor body.
The metallisation shapes are so chosen that the semiconductor zones contact only the second metallisation pattern via the said contact windows. As will become apparent hereinafter, this may save a mask in the manufacture of the semiconductor device as compared with prior art methods of manufacturing such semiconductor devices.
Alternatively, a part of the first metallisation pattern may be so proportioned so as to form a plate of a capacitor. Such a capacitor can often be used effectively in integrated circuits, for example, in manufacturing a memory element.
According to a second aspect of the invention there is provided a method of manufacturing semiconductor devices in accordance with the first aspect, in which a plurality of semiconductor circuit elements having zones adjoining a surface of the semiconductor body are provided in a semiconductor body, the surface of the semiconductor body is provided at least partly with a first electrically insulating layer, said first insulating layer is provided, by a material-removing treatment, with grooves extending only over a part of the thickness of the first insulating layer, a first metallisation pattern is then formed by providing a first conductive layer in the grooves in such a thickness that the surface of the first conductive layer coincides substantially with that of the first insulating layer, a second electrically insulating layer is then provided on the first insulating layer and the first conductive layer, after which a second conductive layer is provided on the second insulating layer and is given the shape of a second metallisation pattern, contact holes being provided in at least the second of electrically insulating layers, via which contact holes the second metallisation pattern adjoins one or more zones of the semiconductor elements.
Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 is a plan view of part of a semiconductor device in accordance with the first aspect of the invention; Figure 2 is a diagrammatic cross-sectional view of part of the semi-conductor device shown in Figure 1 taken on the line II-II of Figure 1; Figure 3 is a diagrammatic cross-sectional view of another semiconductor device in accordance with the first aspect of the invention with the same plan view as shown in Figure 1 and taken on the same line II-II, Figures 4 to 7 are diagrammatic crosssectional views of the part of the semiconductor device shown in Figure 1 in successive stages of manufacture using a method in accordance with the second aspect of the invention, and Figures 8 to 11 are diagrammatic crosssectional views of semiconductor device in successive stages of manufacture using a known method of manufacturing semiconductor devices with two metallisation patterns. The Figures are diagrammatic and not drawn to scale, and for clarity particularly some dimensions in the direction of thickness are strongly exaggerated in the crosssectional views. Semiconductor regions of the same conductivity type are generally shaded in the same direction in the crosssectional views; in the Figures, reference to corresponding components is generally made using the same reference numerals.
The device of Figures 1 and 2 comprises a semiconductor body 1 having an integrated circuit with a plurality of semiconductor elements. A part of the surface 2 of the semiconductor body has a first electrically insulating layer 3. A first metallisation pattern 4 is sunk in the first electrically insulatinn layer, and its surface coincides substantiaywith the surface 5 of the first insulating layer.
In this example the semiconductor body consists of silicon, the first insulating layer of silicon oxide and the first mettallisation pattern of aluminium. In this example the semiconductor circuit elements are formed by bipolar transistors having a collector zone 10, a base zone 8, an emitter zone 9 and a collector contact zone 11 and by a capacitor (4b, 7b). The first insulating layer in this example is formed by a sunken pattern 3 of electrically insulating material, in this example silicon oxide, which is locally sunk at least partly in the semiconductor body.
The semiconductor body 1 furthermore comprises a second insulating layer 6, in this example of silicon oxide, overlying the first insulating layer 3 and the first metallisation pattern 4. A second metallisation pattern 7 overlies the first metallisation pattern 4 and for the most part is separated therefrom by the insulating material of the layers 3 and 6.
Metallisation pattern 7 contacts semiconductor zones (8, 9, 11) belonging to the semiconductor circuit elements.
In this example the semiconductor body 1 consists of a substrate 14 on which an epitaxial layer 10 is provided. In this example, the sunken oxide pattern 3 is provided in the epitaxial layer 10 and extends down to the substrate 14. In this example the sunken oxide is also the first electrically insulating layer. Transistors are provided in the epitaxial layer. In this example the substrate 14 is p-type. The collector zones 10 are n-type, in which, in order to reduce the collector series resistance, highly doped n-type buried layers 15 are provided. The base zones 8 arep-type, while the emitter zones 9 and the collector zones 11 are n±type. The surface 2 which bounds the semiconductor material is not flat in this example, but is recessed as shown in Figure 2.
The first metallisation pattern 4 is not sunk throughout the thickness of the first insulating layer but only over a part of its thickness.
As a result of this an important advantage is obtained in that undesirable contact between the first metallisation pattern and the underlying semiconductor zones which could cause short-circuit can be avoided. In this example, windows 12 are provided in the insulating material, via which windows parts of the second metallisation pattern 7 contact semicon ductorzones (8, 9, 11) belonging to the semiconductor circuit elements an contact the first metallisation pattern 4 (e.g. part 4c).
In this example the track 4a of the first metallisation pattern forms a crossing connection with the track 7a of the second metallisation pattern 7. The part 4b of the first metallisation pattern in this example also constitutes a plate of a capacitor. A part 7b of the second metallisation pattern forms the second plate of the capacitor, the second insulating layer 6 serving as a dielectric.
In the modification shown in Figures 1 and 3 the insulating layer 3 is not formed by a sunken oxide pattern but by a thick layer of silicon oxide which is provided on the semiconductor body. In this example the surface 2 is covered entirely with an insulating layer 3. The transistors are separated by isolation zones 13 which may consist, for example, of sunken oxide. In the specific example shown in Figure 3, however, these isolation zones consist of p-type zones 13 which form with the adjoining semiconductor material a p-n junction 16 which is reversely biased in the operating condition.
In both the embodiments of Figures 2 and 3 the first metallisation pattern 4 is sunk in the insulation layer 3 but only over a part of the thickness of said insulation layer 3. Thus undesirable contact with the underlying semiconductor zones is avoided, while the surface of said first metallisation pattern 4 coincides substantially with the surface 5 of the insulating layer. The second metallisation pattern 7 is separated from the first metallisation pattern 4 by the second insulating layer 6, which permits crossing connections (4a, 7a in Figures 1, 2, 3).
The device shown in Figures 1 and 2 can be manufactured by the following method in accordance with the second aspect of the invention.
A plurality of semiconductor circuit elements having zones adjoining the surface 2 of a semiconductor body 1 are provided in the semiconductor body.
For this purpose, the process may start from a semiconductor body which in this example may be ap-type silicon substrate 14 (Figure 4) having a resistivity between 2 and 5 Ohm. cm. At the area where the collector zones are to be formed, buried layers 15 are provided, for example, by arsenic deposition.
In this example, these buried layers have a thickness of approximately 3 microns (micrometres) and a sheet resistance between 25 and 30 Ohm per square. An n-type epitaxial layer 10 having a resistivity of approximately 1 Ohm.cm and a thickness of approximately 2 microns is then provided on the semiconductor body.
An electrically insulating layer 3 is then sunk in the epitaxial layer layer 10. This may be done, for example, by selectively etching the silicon down to a depth of approximately 1 micron, for example, m an etching mixture containing hydrofluoric acid and nitric acid, or by means of plasma etching. A silicon nitride mask, for example, is used as an etch ing mask. Local oxidation is then effected in a wet nitrogen atmosphere at a temperature of 1000"C, while masking by the silicon nitride mask. The resulting oxide pattern has approximately twice the volume of the oxidized silicon. This treatment is continued until the thickness of the sunken pattern is approximately 2 microns. The epitaxial layer is now divided into a plurality of collector regions 10 which are separated from each other by the sunken oxide 3. The semiconductor body 1 whose surface 2 is not flat, as stated above, but is recessed is provided in this manner with an electrically insulating layer 3.
Base zones 8 are then provided in the collector zones 10, for example, by means of boron diffusion. The base zones have a thickness of approximately 0.8 micron and a sheet resistance between 200 and 800 Ohms per square, in this example 400 Ohms per square.
Emitter zones having a thickness of approximately 0.5 micron and a sheet resistance of approximately 20 Ohms per square are then provided in said base zones. Simultaneously with the provision of these emitter zones which are obtained, for example, by means of diffusion, collector contact zones 11 are provided in the collector regions 10.
The semiconductor device structure shown in Figure 4 is thus obtained.
The first electrically insulating layer 3 is now provided with a pattern of grooves 23 by a material-removing treatment, for example, by chemically etching or plasma etching over a part of the thickness of the layer 3, in this example to a depth of for example 0.7 ym. A first conductive layer 4 is then provided in said grooves so as to form a first metallisation pattern. This may be done, for example, by sputtering or vapour-depositing a conductive layer example aluminium, while using the same mask as was used for defining the grooves, so that the grooves are filled with aluminium until the surface of the conductive layer 4 coincides substantially with that of the first insulating layer 3.
As a result of this, the metal of the first metallisation pattern 4 can advantageously be provided using the same mask as is used for defining the grooves.
Preferably, the first metallisation pattern 4 may be formed by providing an auxiliary layer 22 (Figure 5) on the first electrically insulating layer. A pattern 23 corresponding to that of the grooves to be formed is then provided in said auxiliary layer. In this example said pattern 23 is provided in an auxiliary layer of photosensitive material by means of known photochemical methods in a thickness of approximately 1 micron. Using the auxiliary layer 22 as a mask, grooves are provided according to the pattern 23 in the first electrically insulating layer, which, in this example consists of silicon oxide, by means of a chemical etching treatment or via plasma etching, down to a depth of approximately 0.7 micron (Figure 5).
A layer 24 of conductive material having a thickness of approximately 0.7 micron is then provided over the whole surface, for example by vapour-depositing aluminum from a preferably punctiform source at a substrate temperature of 1500C. Said aluminium is deposited in the grooves in the apertures of the pattern 23, while it remains elsewhere on the auxiliary layer (Figure 6). The auxiliary layer 22 is then removed, for example, by boiling in smoking nitric acid. The aluminium remains in the grooves and thus forms the sunken first metallisation pattern 4.
The auxilary layer 22 may also be formed by a layer of metal, for example tantalum or titanium, or another suitable material which can be etched and removed by agents which do not attack the underlying insulating material.
Polycrystalline silicon may also be used for the sunken metallisation pattern. In this case, for example, aluminium may be used as an auxiliary layer 22, and the aluminium can be removed using a mixture of acetic acid and nitric acid.
After removing the auxiliary layer 22, a second electrically insulating layer 6 is provided on the first insulating layer 3 and the first conductive layer 4. The second electrically insulating layer 6 in this example covers the whole surface and consists in this example of silicon oxide although it may alternatively be silicon nitride.
Contact holes 12 (Figure 7) are then provided in the second electrically insulating layer 6. These contact holes expose both parts of the semiconductor zones 8, 9, 11 of the underlying transistors and parts of the first metallisation pattern 4. A second conductive layer 7 for forming the second metallisation pattern is then provided on the second electrically insulating layer 6. This metallisation pattern may be formed, for example using a photolithographic and etching technique and is connected electrically, via the contact holes 12, to the said semiconductor zones 8, 9, 11 and to the metallisation pattern 4. The structure shown in Figure 2 is then obtained.
This method saves one mask as compared with the more conventional method now to be described.
Figures 8 to 10 are cross-sectional views in successsive steps during manufacture of the semiconductor device shown in Figure 11 using a known method not in accordance with the present invention. This semiconductor device which is not in accordance with the present invention has the same circuit elements as the semiconductor device shown in Figures 1 and 2 but a different structure of the two-layer metallisation. The starting material in this case is a type silicon substrate 14 (Figure 8) having a resistivity between 2 and 5 Ohm.cm. At the area of the collector zones to be formed a buried layer 15 is provided, for example by arsenic deposition. An epitaxial layer of the n-type is then grown on the substrate, for example by epitaxial growth from the gaseous phase. Isolation regions 13 (Figure 8) are provided in said epitaxial layer so that the layer is divided into collector regions 10 of the n-type. P-type base zones 8, n-type emitter zones 9 and n-type collector zones 11 are then provided herein by means of, for example, diffusion or ion implantation (Figure 4).
According to a conventional method of providing a multilayer metallisation pattern, the semiconductor body is then covered with an insulating layer 17, of, for example, silicon oxide, in which apertures 12 are then etched by means of a first mask (Figure 8). Via said apertures, the resulting exposed semicoductor zones are connected to a first metallisation pattern 18 (Figure 9) which in this example interconnects inter alia the collector contact zones 11 of two transistors separated by the isolation region 13. This metallisation pattern may be obtained, for example, by vapour-deposition and then selectively etching aluminium, by means of a second mask.
The body is then covered again with an insulating layer 19 in which apertures 20 are provided by means of a third mask (Figure 10) so that parts of the metallisation pattern 18 are exposed which can be contacted to a second metallisation pattern 21 (Figure 11) via the apertures 20. Said metalhsation pattern can be obtained by vapour-depositing aluminum and then selectively etching said aluminium by means of a fourth mask.
In the previously-described method of manufacturing a semiconductor device, however, only three instead of four masks are necessary to manufacture the same semiconductor device by using different metallisation structure. These masks are first of all the masks for defining and etching the grooves in which the first metallisation pattern 4 is provided (which is comparable to the fourth mask of the conventional method), secondly the mask for defining the contract holes 12 (which is comparable to the combination of the above-mentioned first and third masks of the conventional method) and thirdly the mask for defining the second metallisation pattern (which is comparable to the second mask of the conventional method). The method in accordance with the invention enables the saving of one mask in that in this method contact holes to the semiconductor zones 8, 9. 11 and connections between the first and the second metallisation pattern are realised in one step.
It will be obvious that the invention is not restricted to the examples described, but that many variations are possible to those skilled in the art without departing from the scope of this invention.
The semiconductor body need not necessarily be silicon, but other semiconductor materials, for example germanium and semiconductor materials of the III-V type, for example gallium arsenide, may alternatively be used for some devices. In the embodiments the conductivity types of all the semiconductor zones and semiconductor regions lb replaced by their may (simultaneously) be replaced by their opposite types. These and as well as the collector contact zones may alternatively be provided by ion implantation instead of by diffusion.
Besides bipolar transistors, the circuit elements may be, for example, MOS transistors or other active or passive elements, for example resistors, diodes etc. and, when using sunken oxide, channel stoppers may be provided, if necessary, below the sunken oxide isolation regions 13.
WHAT WE CLAIM IS: 1. A semiconductor device having a semiconductor body comprising an integrated circuit having a number of semiconductor circuit elements, in which device at least a part of the surface of the semiconductor body has a first electrically insulating layer, a first metallisation pattern which is sunk in the first insulating layer only over part of the thickness of the first insulating layer, the surface of which first metallisation pattern coincides substantially with that of the first insulating layer, a second insulating layer overlying the first insulating layer and the first metallisation pattern, and a second metallisation pattern overlying the first metallisation pattern and being separated therefrom by insulation material, only the second metallisation pattern contacting at least one semiconductor zone belonging to the semiconductor circuit elements via at least one contact hole in at least the second of the insulating layers.
2. A semiconductor device as claimed in Claim 1, in which at least one track of the first metallisation pattern crosses a track of the second metallisation pattern.
3. A semiconductor device as claimed in Claim 1 or Claim 2, in which the first electrically insulating layer consists of a pattern of electrically insulating material at least partly sunk locally in the semicoductor body.
4. A semiconductor device as claimed in any of the preceding Claims, in which a part of the first metallisation pattern forms part of a capacitor.
5. A semiconductor device as claimed in any of the preceding Claims, in which at least one of the metallisation patterns consists of polycrystalline silicon.
6. A method of manufacturing a semi
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (11)

**WARNING** start of CLMS field may overlap end of DESC **. the two-layer metallisation. The starting material in this case is a type silicon substrate 14 (Figure 8) having a resistivity between 2 and 5 Ohm.cm. At the area of the collector zones to be formed a buried layer 15 is provided, for example by arsenic deposition. An epitaxial layer of the n-type is then grown on the substrate, for example by epitaxial growth from the gaseous phase. Isolation regions 13 (Figure 8) are provided in said epitaxial layer so that the layer is divided into collector regions 10 of the n-type. P-type base zones 8, n-type emitter zones 9 and n-type collector zones 11 are then provided herein by means of, for example, diffusion or ion implantation (Figure 4). According to a conventional method of providing a multilayer metallisation pattern, the semiconductor body is then covered with an insulating layer 17, of, for example, silicon oxide, in which apertures 12 are then etched by means of a first mask (Figure 8). Via said apertures, the resulting exposed semicoductor zones are connected to a first metallisation pattern 18 (Figure 9) which in this example interconnects inter alia the collector contact zones 11 of two transistors separated by the isolation region 13. This metallisation pattern may be obtained, for example, by vapour-deposition and then selectively etching aluminium, by means of a second mask. The body is then covered again with an insulating layer 19 in which apertures 20 are provided by means of a third mask (Figure 10) so that parts of the metallisation pattern 18 are exposed which can be contacted to a second metallisation pattern 21 (Figure 11) via the apertures 20. Said metalhsation pattern can be obtained by vapour-depositing aluminum and then selectively etching said aluminium by means of a fourth mask. In the previously-described method of manufacturing a semiconductor device, however, only three instead of four masks are necessary to manufacture the same semiconductor device by using different metallisation structure. These masks are first of all the masks for defining and etching the grooves in which the first metallisation pattern 4 is provided (which is comparable to the fourth mask of the conventional method), secondly the mask for defining the contract holes 12 (which is comparable to the combination of the above-mentioned first and third masks of the conventional method) and thirdly the mask for defining the second metallisation pattern (which is comparable to the second mask of the conventional method). The method in accordance with the invention enables the saving of one mask in that in this method contact holes to the semiconductor zones 8, 9. 11 and connections between the first and the second metallisation pattern are realised in one step. It will be obvious that the invention is not restricted to the examples described, but that many variations are possible to those skilled in the art without departing from the scope of this invention. The semiconductor body need not necessarily be silicon, but other semiconductor materials, for example germanium and semiconductor materials of the III-V type, for example gallium arsenide, may alternatively be used for some devices. In the embodiments the conductivity types of all the semiconductor zones and semiconductor regions lb replaced by their may (simultaneously) be replaced by their opposite types. These and as well as the collector contact zones may alternatively be provided by ion implantation instead of by diffusion. Besides bipolar transistors, the circuit elements may be, for example, MOS transistors or other active or passive elements, for example resistors, diodes etc. and, when using sunken oxide, channel stoppers may be provided, if necessary, below the sunken oxide isolation regions 13. WHAT WE CLAIM IS:
1. A semiconductor device having a semiconductor body comprising an integrated circuit having a number of semiconductor circuit elements, in which device at least a part of the surface of the semiconductor body has a first electrically insulating layer, a first metallisation pattern which is sunk in the first insulating layer only over part of the thickness of the first insulating layer, the surface of which first metallisation pattern coincides substantially with that of the first insulating layer, a second insulating layer overlying the first insulating layer and the first metallisation pattern, and a second metallisation pattern overlying the first metallisation pattern and being separated therefrom by insulation material, only the second metallisation pattern contacting at least one semiconductor zone belonging to the semiconductor circuit elements via at least one contact hole in at least the second of the insulating layers.
2. A semiconductor device as claimed in Claim 1, in which at least one track of the first metallisation pattern crosses a track of the second metallisation pattern.
3. A semiconductor device as claimed in Claim 1 or Claim 2, in which the first electrically insulating layer consists of a pattern of electrically insulating material at least partly sunk locally in the semicoductor body.
4. A semiconductor device as claimed in any of the preceding Claims, in which a part of the first metallisation pattern forms part of a capacitor.
5. A semiconductor device as claimed in any of the preceding Claims, in which at least one of the metallisation patterns consists of polycrystalline silicon.
6. A method of manufacturing a semi
conductor device as claimed in any of the preceding Claims, in which a plurality of semiconductor circuit elements having zones adjoining a surface of the semi-conductor body are provided in a semicoductor body, the surface of the semiconductor body is provided at least partly with a first electrically insulating layer, said first insulating layer is provided, by a material-removing treatment, with grooves extending only over a part of the thickness of the first insulating layer, a first metallisation pattern is then formed by providing a first conductive layer in the grooves in such a thickness that the surface of the first conductive layer coincides substantially with that of the first insulating layer, a second electrically insulating layer is then provided on the first insulating layer and the first conductive layer, after which a second conductive layer is provided on the second insulating layer and is given the shape of a second metallisation pattern, contact holes being provided in at least the second of the electrically insulating layers, via which contact holes the second metallisation pattern adjoins one or more zones of the semiconductor elements.
7. A method as claimed in Claim 6, in which the provision of both the grooves and the first metallisation pattern is carried out by providing on the first electrically insulating layer an auxiliary layer in which a mask pattern is formed, after which grooves according to said pattern are provided in the first electrically insulating layer, a layer of: conductive material is then provided on the whole surface of the body, and after removing the auxiliary layer said conductive material remains in the grooves to form the sunken first metallisation pattern.
8. A method of manufacturing a semiconductor device substantially as described with reference to Figures 4 to 7 or Figures 8 to 11 of the accompanying C:vice drawings.
9. A semiconductor device manufac- tured by a method claimed in any of Claims 6 to 8.
10. A semiconductor device substantially as described with reference to Figures 1 and 2 of the accompanying drawings.
11. A semiconductor device substantially as described with reference to Figures 1 and 3 of the accompanying drawings.
GB976878A 1977-03-16 1978-03-13 Semiconductor devices and their manufacture Expired GB1594067A (en)

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NL7702814A NL7702814A (en) 1977-03-16 1977-03-16 SEMI-CONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THIS.

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GB1594067A true GB1594067A (en) 1981-07-30

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CA (1) CA1102923A (en)
DE (1) DE2809411A1 (en)
FR (1) FR2384355A1 (en)
GB (1) GB1594067A (en)
NL (1) NL7702814A (en)

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Publication number Priority date Publication date Assignee Title
DE3214991A1 (en) * 1982-04-22 1983-11-03 Siemens AG, 1000 Berlin und 8000 München Semiconductor chip with discrete capacitor
FR2634318B1 (en) * 1988-07-13 1992-02-21 Commissariat Energie Atomique METHOD FOR MANUFACTURING AN INTEGRATED MEMORY CELL

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3988214A (en) * 1968-06-17 1976-10-26 Nippon Electric Company, Ltd. Method of fabricating a semiconductor device
GB1364677A (en) * 1970-07-10 1974-08-29 Philips Electronic Associated Semiconductor devices and methods of making semiconductor devices
JPS5088980A (en) * 1973-12-10 1975-07-17

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JPS53114686A (en) 1978-10-06
DE2809411A1 (en) 1978-09-21
NL7702814A (en) 1978-09-19
CA1102923A (en) 1981-06-09
FR2384355A1 (en) 1978-10-13

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