DE2809411A1 - CONDUCTOR ARRANGEMENT AND METHOD OF MANUFACTURING IT - Google Patents

Description

PHN. 8718. VA / E VH.

-> - U September 3, 1977 »

"Semiconductor device and method for their production"

The invention relates to a semiconductor arrangement having a semiconductor body with an integrated circuit with a number of semiconductor circuit elements, wherein at least a part of the surface of the semiconductor body with a first electrically insulating layer, a first metallization pattern, which in the first insulating layer is sunk and its surface practically with that of the

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first insulating layer collapses, a second insulating layer overlying the first insulating layer and the first metallization pattern, and a second metallization pattern is provided overlying and from the first metallization pattern is separated by insulating material.

The invention further relates to a method for producing such semiconductor arrangements .

It should be noted that where a metallization pattern is mentioned in this application, this metallization pattern need not necessarily consist of a metal, but rather can also consist of polycrystalline silicon or such conductive materials.

Semiconductor arrangements with multiple metallization patterns are mainly used when integrating a number of circuit elements into one Circuit must work together. Included

often a single metallization for contacting and interconnecting the various circuit elements is not enough.

Applying multiple metallization patterns can solve this problem. This is on an insulating layer covering the semiconductor body, a first metallization pattern, which via contact windows with the zones of

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Semiconductor circuit elements is connected. On top of this metallization pattern lies a second metallization pattern, which is separated by a second insulating layer from the first metallization pattern is separated and, where necessary, contacted with this pattern via contact windows.

This solution has the disadvantage that the final surface has unevenness and that in places where there are intersecting connections, the second metallization pattern is difficult to apply in such a way that this metallization is sufficiently reliable at the points mentioned. These reliability problems can arise as a result of mechanical stresses in the metal or an insufficient layer thickness of this metallization on this Bodies surrender.

A semiconductor arrangement of the type mentioned at the outset, in which these disadvantages are met, is from the German Auslegeschrift 20 4 ° - 908 known.

In the arrangement described therein lies on the surface of the semiconductor body, a first electrically insulating layer, in which a first metallization pattern is sunk, the surface of which practically with the Surface of the first insulating layer collapses. The metallization pattern is over the entire thickness of the sunk first insulating layer and therefore forms a contact with the underlying semiconductor zones. On this

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A second insulating layer and a second are located on the first insulating layer and this first metallization pattern Metallization pattern, which is separated from the first metallization pattern by insulating material.

This arrangement has the disadvantage that the first metallization pattern over the entire thickness of the first Insulating layer is sunk therein and is thereby in direct contact with the semiconductor body. This means, that the shape of this first metallization pattern strictly follows the "layout" of the underlying circuit elements is bound; there are generally semiconductor junctions therein which are exposed at the surface and through a part of the metallization pattern lying thereon can be short-circuited.

A second disadvantage is that the second metallization pattern is completely integrated into the second insulating layer is sunk, so that an isolated crossing connection between a conductor track of the first metallization pattern and a conductor track of the second metallization pattern cannot easily be achieved.

The purpose of the invention is to remedy these disadvantages in whole or in part.

The invention is based, inter alia, on the knowledge that the first metallization pattern can be created in a simple manner can be attached in such a way that no undesirable

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Contact is formed with the underlying semiconductor zones is, whereby even a mask can be saved in the production of such semiconductor arrangements can.

A semiconductor arrangement of the type mentioned at the outset is therefore characterized according to the invention, that only the second metallization pattern has at least one contact hole in the underlying Insulating layer with at least one of the semiconductor zones belonging to the semiconductor circuit elements is in contact, and that the first metallization pattern is only over part of the thickness of the first insulating layer is sunk in it.

Because the first metallization pattern now only covers part of the thickness of the first insulating layer is sunk in it, this pattern can no longer in undesired places with the underlying Semiconductor zones come into direct contact, so there is no risk of an undesired short circuit there is more.

Contact windows can be provided in the second insulating layer, e.g. on this second insulating layer, as is the case, for example, when the second metallization pattern via such a contact window only with the first one Metallization pattern is in contact. Can with advantage

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but also a contact window through the two insulating layers be attached through. As a result, the semiconductor zones can be connected to the second metallization pattern contacted and can therefore zones of different circuit elements over this second metallization pattern are connected to one another.

Since, according to the invention, the second metallization pattern over the first metallization pattern and is separated from this by insulating material, crossing connections are easily in one Semiconductor arrangement according to the invention possible. A preferred embodiment according to the invention is then also characterized in that at least one track of the first metallization pattern is a track of the second metallization pattern crosses.

A suitable improvement of this structure is further obtained when the contact window over the the second metallization pattern is in contact with the semiconductor regions only in the second insulating layer be attached so that a more compact structure is possible through lower tolerances. This can be done with a particularly preferred embodiment according to the Invention can be achieved in which the semiconductor circuit elements lie directly under the second insulating layer and are surrounded by the first insulating layer.

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This preferred embodiment is thus characterized that the first electrically insulating layer of a locally at least partially in the Semiconductor bodies sunk layered patterns electrically insulating material.

The forms of metallization are selected according to the invention such that the semiconductor zones over said contact windows only with the second metallization pattern get connected. As will be apparent from the following, this can result in the manufacture of the Semiconductor arrangement in comparison to known methods for producing such semiconductor arrangements a Mask can be saved.

A part of the first metallization pattern can also be dimensioned in such a way that a plate-shaped Part is formed which forms part of a capacitor. In integrated circuits can Such a capacitor is often used successfully, for example in the manufacture of a storage element.

Another preferred embodiment according to the invention is therefore characterized in that part of the first metallization pattern is part of a capacitor forms.

The invention further relates to a particularly suitable method for producing the semiconductor circuit elements of the type described above. This

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The method is characterized according to the invention, that in a semiconductor body a number of semiconductor circuit elements are also attached to a surface of the semiconductor body bordering zones is attached; that the surface of the semiconductor body is at least partially is provided with a first electrically insulating layer; that this first insulating layer through a Removal treatment is provided with grooves that extend over only part of the thickness of the first insulating layer extend; that then to form a first metallization pattern in the grooves a first conductive layer is applied with such a thickness that the surface of the first conductive layer practically coincides with that of the first insulating layer; that then on the first insulating layer and a second electrically insulating layer is applied to the first conductive layer, after which the Second insulating layer, a second conductive layer is applied which is in the form of a second metallization pattern is brought, and that contact holes in the two electrically insulating layers are applied, over which the second metallization pattern is attached to one or more zones of the semiconductor circuit elements connects.

Some embodiments of the invention are shown in in the drawing are shown in more detail below

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described. Show it:

Fig. 1 is a plan view of a semiconductor device according to the invention,

FIG. 2 schematically shows a cross section through the semiconductor arrangement according to FIG. 1 along the line H-II,

3 schematically shows a cross section through another embodiment of a semiconductor arrangement according to FIG Invention with the same plan view as in Fig. 1 and along the same line II-II,

FIGS. H to 7 show schematically in cross section the semiconductor arrangement according to FIG. 1 in successive stages of a production method according to the invention, and

8 to 11 schematically in cross section a semiconductor arrangement with two metallization patterns in FIG successive stages of a known manufacturing process . .

The figures are drawn schematically and not to scale, for the sake of clarity in FIG Cross-sections, in particular the dimensions in the direction of thickness, are shown exaggerated. Semiconductor areas of the same conductivity type are hatched in the cross-sections generally in the same direction; in Parts corresponding to the figures are generally denoted by the same reference numerals. Fig. 1 shows in plan view and Fig. 2 shows

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schematically in cross section along the line II-II a semiconductor device according to the invention. The arrangement consists of a semiconductor body 1 with an integrated circuit with a number of semiconductor circuit elements, at least part of the surface 2 of the semiconductor body being provided with a first electrically insulating layer and a first metallization pattern k which is sunk into the first electrically insulating layer and the surface of which practically coincides with the surface 5 of the first insulating layer.

In the present example, the semiconductor body consists of silicon, and the first insulating layer consists of Silicon oxide and the first metallization pattern made of aluminum. The semiconductor circuit elements are in the present Example by bipolar transistors with a collector zone 10, a base zone 8, an emitter zone 9 and a Collector contact zone 11 and through a capacitor (^ b, 7b) educated. The first insulating layer is in the present example by a locally at least partially in the Semiconductor body countersunk pattern 3 from electrically insulating material, in this example silicon oxide.

Furthermore, the semiconductor body 1 contains a second insulating layer 6, in this example made of silicon oxide, and a second metallization layer, which lies over the first insulating layer 3 and the first metallization pattern k.

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pattern 7> which lies above the first metallization pattern 4 and is separated from it by the insulating material of layers 3 and 6, with at least one of the metallization patterns, in the present example the pattern 7 »with semiconductor zones belonging to the semiconductor circuit elements (8, 9> 11 ) is in contact. In the present example, the semiconductor body 1 consists of a substrate Ik on which an epitaxial layer 10 is produced. In the present example, the sunk oxide pattern 3 is applied in this epitaxial layer and continues up to the substrate. In the present example, the sunk oxide is also the first electrically insulating layer. Transistors are placed in the epitaxial layer. In the present example, the substrate Tk has the p ^ conductivity type. The collector zones 10 are of the η type, with highly doped η-conductive buried layers 15 being applied to reduce the collector series resistance. The base zones 8 are of the p-type, while the emitter zones 9 and the collector contact zones 11 are of the η -type. In the present example, as can be seen from FIG. 2, the surface 2 which delimits the semiconductor body is not flat, but more or less rectangular.

According to the invention, the first metallization pattern k is now not over the entire thickness, but only over part of the thickness of the first insulating layer therein

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sunk. The main advantage is obtained here, that the first metallization pattern is no longer in direct undesired contact with the underlying semiconductors— zones and can cause short circuits in them. In this example there are contact windows in the insulating material 12 attached, over the parts of the second metallization pattern 7 with to the semiconductor circuit elements appropriate semiconductor zones are in contact (8, 9 »11) ·

The track 4a of the first metallization pattern forms a crossing connection with in this example the track 7a of the second metallization pattern 7

In this example, only the second metallization pattern 7 is via contact windows 12 with the semiconductor zones of the semiconductor body connected.

In the present example, part kb of the first metallization pattern forms a plate of a capacitor. A part 7b of the second metallization pattern forms the second plate of the capacitor, the second insulating layer 6 acting as a dielectric.

In another embodiment with the same Top view like FIG. 1, but with a cross section according to FIG. 3> the insulating layer 3 is not sunk by a Oxide pattern, but formed by a thick silicon oxide layer that is attached to the semiconductor body will. In this example, the surface 2 is complete

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covered with an insulating layer 3. The transistors are separated from one another by separation zones 13, e.g. may consist of buried oxide. In the example according to FIG. 3, however, these separation zones consist of p-conducting Zones 13 »which, with the adjoining semiconductor material, form a pn junction 16 which, in the operating state, is in the Blocking direction is biased.

In both embodiments, the first metallization pattern k is sunk into the insulating layer 3, but only over part of the thickness of this insulating layer 3 '. This avoids contact with the underlying semiconductor zones, while the surface of this first metallization pattern h practically coincides with the surface 5 of the insulating layer . The second metallization pattern 7 is separated from the first metallization pattern k by the second insulating layer 6, as a result of which crossing connections (4a, 7a in FIGS. 1, 2, 3) are made possible.

The arrangement according to the invention according to FIGS. 1 and 2 can according to the invention in the following way getting produced.

In a semiconductor body 1, a number of semiconductor circuit elements are connected to the surface 2 of the • Zones bordering the semiconductor body attached.

For this purpose, a semiconductor body, in this example a p-conducting silicon substrate 14 (Fig. 4)

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with a specific resistance between 2 and 5 - ^ - «cm went out. At the points of the collector zones to be formed, buried layers I5 are created, e.g. by arsenic deposition appropriate. In this example, these buried layers have a thickness of about 3 µm and one Sheet resistance between 25 and 30 - ^. on. On the The semiconductor body then becomes an η-conductive epitaxial layer 10 with a specific resistance of approximately 1 - / L.cm and a thickness of about 2 / µm.

In this epitaxial layer, an electrically insulating layer 3 is then applied in such a way that that she is immersed in it. This can be done, for example, by applying the silicon selectively over a depth of about 1 / µm, e.g. in one containing hydrogen fluoride and nitric acid Etch mixture, etched off or a plasma etching treatment is carried out. A silicon nitride mask, for example, is used as an etching mask used. Then local oxidation is carried out in a humid nitrogen atmosphere at a temperature of 1000 ° C with masking by the silicon nitride mask. ': -The oxide pattern obtained has about one twice larger volume than the oxidized silicon. This treatment continues until the thickness of the submerged Pattern is about 2 µm. The epitaxial layer is now divided into a number of collector regions 10, which are separated from one another by the sunk oxide 3.

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The semiconductor body 1, the surface 2 of which, as mentioned above, is not flat, but more or less rectangular, is thus at least partially provided with an electrically insulating layer 3.

In the collector zones 10 are then base zones

e.g. attached with the help of board diffusions. The base zones have a thickness of about 0.8 / µm and a sheet resistance between 200 and 800 -Q- and in this example equal to 400 - ^ - on.

After that, emitter zones are created in these base zones

with a thickness of about 0.5 / µm and a sheet resistance of about 20 - ^ - attached. At the same time as these emitter zones, which are obtained, for example, by diffusion, collector contact zones 11 are applied in the collector regions 10. The semiconductor arrangement according to FIG. K is thus obtained.

The first electrically insulating layer 3 will now be provided by a material removal treatment with a pattern of grooves 23, for example by chemical etching or plasma etching through a part of the thickness of the layer 3 'in the present example, about 0.7 / ^um>. In these

A first conductive layer h is then placed in grooves to form a first metallization pattern. This can be done, for example, by using the same mask that is used to define the grooves, a conductive layer, for example made of aluminum, by sputtering or

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Vapor deposition is applied so that the grooves are filled with aluminum until the surface of the conductive layer h practically coincides with that of the first insulating layer 3. The metal of the first metallization pattern h can thereby advantageously be applied by means of the same mask that is used to define the grooves.

According to a preferred embodiment of the

According to the method according to the invention, this metallization pattern can be applied to the first electrically insulating layer an auxiliary layer 22 (Fig. 5) attached will. A pattern 23 is then applied in this auxiliary layer which corresponds to that of the grooves to be applied. This pattern 23 is in the present example by means of known photochemical techniques in an auxiliary layer made of photosensitive material with a thickness of about 1 / µm. Using the auxiliary layer 22 as Mask become electrical according to "the pattern 23 grooves in the first insulating layer, which in the present example consists of silicon oxide, by chemical etching or plasma etching mounted to a depth of about 0.7 / µm (Fig. 5)

A layer 24 of conductive material with a thickness of about 0.7 μm is then applied over the entire surface, for example by vapor deposition of ^{aluminum from a preferably point source at a substrate temperature of 150 ° C.} In the

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Openings of the pattern 23, this aluminum is deposited in the grooves, while it remains elsewhere on the auxiliary layer (Fig. 6). This auxiliary layer is then removed, for example by boiling in fuming nitric acid. The aluminum remains in the grooves and thus forms the sunk first metallization pattern h.

A layer of metal, e.g. tantalum or titanium, or another suitable layer can also be used as an auxiliary layer Material can be used that is etchable and can be removed by means that do not affect the underlying Isoliei-τ attack material.

Polycrystalline silicon can also be used for the

Recessed metallization patterns can be used. For example, aluminum is used as an auxiliary rail, which with the help of a mixture of acetic acid and nitric acid can be removed.

After the auxiliary layer has been removed, the first insulating layer 3 and the first conductive layer 4 a second electrically insulating layer 6 attached.

This second electrically insulating layer covers the entire surface in this example and here consists of Silicon oxide, but can also consist of silicon nitride.

Then 6 contact holes 12 are made in the second electrically insulating layer (FIG. 7). These Contact holes lay parts of the semiconductor zones 8, 9 »11

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of the underlying transistors as well as parts of the first metallization pattern k free. A second conductive layer 7, which is brought into the shape of the second metallization pattern, is applied to this second electrically insulating layer. This pattern is applied photochemically, for example, and is electrically connected to the semiconductor zones 8, 9, 11 and to the metallization pattern 4 via the aforementioned contact holes. The structure according to FIG. 2 is thus obtained.

The method described above saves a mask in comparison with the conventional methods.

FIGS. 8 to 10 show, in cross section, the semiconductor arrangement according to FIG. 11 with two-layer wiring in successive stages of a known process.

This semiconductor device contains the same elements as the semiconductor device according to FIGS. 1 and 2, but has a different structure of the metallization.

In this example, it is made of a silicon substrate 14 (FIG. 8), here of the p-type, with a specific Resistance assumed to be between 2 and 5 & cm. In the places A buried layer 15 is applied to the collector zones to be formed, for example by means of arsenic deposition. On the Substrate. An η-conductive epitaxial layer is then deposited e.g. by epitaxial growth from the gas phase.

In this epitaxial layer, separation areas I3 (Fig. 8)

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attached so that this layer in collector regions 10 is subdivided by the η-type. Then, in a manner known per se, p-conducting base zones 8, n-conducting Emitter zones 9 and η-conductive collector contact zones 11 with With the help of e.g. diffusion or ion implantation attached (Fig. 4).

By a common method of attachment

the semiconductor body becomes a multilayer metallization pattern now covered with an insulating layer 17 made of e.g. silicon oxide, in which openings are then made with the aid of a first mask be etched (Fig. 8). The semiconductor zones exposed as a result are connected to a first metallization pattern 18 (FIG. 9)> that in the present example inter alia the collector contact zones 11 of two transistors separated from one another by the separating region 13 connects. This metallization pattern can e.g. by vapor deposition and the subsequent selective etching of aluminum can be obtained with the aid of a second mask. The body is then covered with an insulating layer 19 again coated, in which openings 20 are made with the aid of a third mask (FIG. 10), through the parts of the metallization pattern 18 are exposed, which via the openings 20 with a second metallization pattern 21 can be contacted (Fig. 11). This metallization pattern can be produced by the vapor deposition of aluminum and the

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subsequent selective etching of this aluminum with the help a fourth mask can be obtained.

In the method for manufacturing a semiconductor device according to the invention, however, only three masks instead of four are required in order to manufacture the same semiconductor device with a different metallization structure. These masks are firstly the mask for defining and etching the grooves in which the first metallization pattern k is applied (which is comparable to the fourth mask of the conventional method), secondly the mask for defining the contact holes 12 (those with the combination of the first and the third mask of the conventional method is comparable) and thirdly the mask for defining the second metallization pattern (which is comparable to the second mask of the conventional method). The method according to the invention enables a mask to be saved due to the fact that in this method contact holes to the semiconductor zones 8, 9j 11 and connections between the first and the second metallization pattern are formed in a single step.

It is clear that the invention is not restricted to the examples described above, but rather that within the scope of the invention, many modifications are possible for the person skilled in the art.

So the semiconductor body does not necessarily need

2.5 to be made of silicon, but also other semiconductor

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materials such as germanium and III-V type semiconductor materials such as gallium arsenide can be used. The conduction types of all semiconductor zones and regions (at the same time) can also pass through in the exemplary embodiments the opposite types are replaced. The base and emitter zones, as well as the collector contact zones, can flow by ion implantation rather than diffusion.

The circuit elements can, instead of bipolar transistors, e.g. MOS transistors or other active or passive elements, e.g. resistors, diodes, etc., with 13 If necessary, channel stoppers are attached.

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Claims (1)

^{PHN 87} " ¹⁸ 1/17/78 PATENT CLAIMS ; \ 1y Semiconductor arrangement with a semiconductor body with an integrated circuit with a number of semiconductor circuit elements, wherein at least a part of the surface of the semiconductor body with a first electrically insulating layer, a first Metallization pattern that is sunk into the first insulating layer and its surface is practical with which the first insulating layer coincides, one over the first insulating layer and the first Metallization pattern lying second insulating layer and a second metallization pattern is provided, which lies over the first metallization pattern and is separated from this pattern by insulating material, that only the second metallization pattern has at least one contact hole in the underlying insulating layer in contact with at least one of the semiconductor zones belonging to the semiconductor circuit elements and that the first metallization pattern only covers part of the thickness of the first insulating layer is sunk in it. 2. Semiconductor arrangement according to claim 1, characterized characterized that at least one ball of the first Metallization pattern crosses a path of the second metallization pattern. 3 · - semiconductor arrangement according to one of claims 1 or 2 _t , characterized in that the first 809838/0660 PHN 87Ί8 28Ü9411 17.1.78 electrically insulating layer composed of a locally at least partially sunk into the semiconductor body layered pattern made of electrically insulating material, k. Semiconductor arrangement according to one of Claims 1 to 3, characterized in that part of the first metallization pattern forms part of a capacitor. 5. Semiconductor arrangement according to one of claims 1 to 4, characterized in that at least one the metallization pattern consists of polycrystalline silicon. 6. A method for producing a semiconductor arrangement according to one or more of the preceding claims, characterized in that in a semiconductor body a number of semiconductor circuit elements with zones adjoining a surface of the semiconductor body is attached that the surface the semiconductor body is at least partially provided with a first electrically insulating layer, that this first insulating layer is provided with grooves by a material removal treatment, which extend only over part of the thickness of the first insulating layer, that then to form a First metallization pattern in the grooves, a first conductive layer with such a thickness is applied 809838/0660 PHN 8718 is that the surface of the first conductive layer practically coincides with that of the first insulating layer that subsequently on the first insulating layer and a second electrically insulating layer is applied to the first conductive layer, after which the Second insulating layer, a second conductive layer is applied, which is in the form of a second metallization pattern is brought, and that contact holes in the two electrically insulating layers are attached, via which the second metallization pattern is attached to one or more zones of the semiconductor circuit elements connects. 7 «Method according to claim 6, characterized in that that the application of the first metallization pattern takes place in that an auxiliary layer on the first electrically insulating layer is applied, a pattern being formed in this auxiliary layer, after which grooves are made in the first electrically insulating layer according to this pattern, and that then a layer of conductive material is applied over the entire surface of the body, after which Removal of the auxiliary layer, this conductive material remains in the grooves and so the first sunk Forms metallization pattern. 809838/0690