GB1587917A

GB1587917A - Heart pacers

Info

Publication number: GB1587917A
Application number: GB40202/77A
Authority: GB
Original assignee: ARCO Medical Products Co
Current assignee: ARCO Medical Products Co
Priority date: 1976-09-29
Filing date: 1977-09-27
Publication date: 1981-04-15
Also published as: IE45875B1; CH627081A5; JPS5342484A; FR2366012A1; NL7710571A; CA1100580A; IT1089836B; DE2738871A1; FR2366012B1; BE859086A; IE45875L; SE7710869L

Abstract

The stimulation pulse generator (12) of this pacemaker is triggered by a digital computer (10, 11) which determines the pulse interval and the pulse width for the pacemaker pulses transmitted to the heart electrodes via the output terminal (13) by repeatedly running a program. The digital computer comprises a read-only memory (11) with a stored program and a microprocessor (10) which is connected to the stimulation pulse generator (12). The pacemaker can be fully implanted into the body of a patient. <IMAGE>

Description

(54) IMPROVEMENTS IN HEART PACERS (71) We, ARCO MEDICAL PRODUCTS COMPANY, a corporation organized under the laws of the State of Delaware, United States of America, whose post office address is P.O.

Box 546, Leechburg, State of Pennsylvania, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to heart pacers.

Heart pacers have been recently proposed which employ digital circuitry, for example, J-K flip-flops, clock pulse generators, shift registers, and the like. More recently, heart pacers have been proposed which include digital control circuits for enabling a fully implanted heart pacer to be controlled from a location external to the patient to vary, for example, the operating parameters of the pacer.

None of the pacers advanced to date, however, include digital computer means for controlling the operation of the pacer.

According to the invention there is provided a heart pacer adapted to be connected to electrodes to a patient's heart, comprising: a stimulation pulse generator having an output for connection to said electrodes to deliver heart stimulation pulses thereto, a microprocessor having an output connected to control the output of said stimulation pulse generator and having a clock to control the speed at which said microprocessor executes instructions applied thereto, a memory having a program loaded thereinto having predetermined instructions therein to be executed by said micorprocessor, said microprocessor being operative to select certain program instructions from said memory and execute the selected instructions, including an instruction to produce an output to control the output of the stimulation pulse generator to produce a heart stimulation pulse, said instruction to control the output of the stimulation pulse generator being repeated and executed after a predetermined number of instructions have been executed, the order of instructions of said predetermined number of instructions being directed by said microprocessor and by the instructions of said program, whereby the time or the execution of the selected instructions of the program by the microprocessor determines the timing of the pulses of said stimulation generator.

The invention will now be described, by way of example, with reference to the accompanying drawing, which is an electrical schematic diagram of the heart pacer, in accordance with the invention.

As shown in the sole accompanying drawing, the heart pacer, in accordance with a preferred embodiment of the invention, includes a microprocessor circuit 10 connected to a read only memory (ROM)1 1. The microprocessor 10 in combination with the ROM 11 produces an output to trigger a stimulation pulse generator circuit 12 to produce an output to electrodes (now shown) upon output line 13.

In simplest terms. a microprocessor is a monolithic (one-chip) processor, a processor being a device which fetches and executes instructions. The microprocessor 10 described hereinbelow is a COSMAC processor of the type RCA-CDP 1802, although it will be apparent to those skilled in the art that other microprocessors can be equally advantageously employed.

The microprocessor 10 includes eight memory address outputs designated MAO-MA7 and eight data input/output lines designated BUSO-BUS7.

The ROM 11 hereinbelow described is of the type RCA-CDP 1831, although, again, any ROM compatible with the particular microprocessor employed can be used, as will be apparent to those skilled in the art.

The RCA-CDP 1802 and CDP 1831 are particularly advantageously employed in.conjunction with use in a heart pacer because of the low current requirements of the CMOS devices their circuits comprise.

The microprocessor 10 includes an internal digital clock (not shown). the frequency of which is determined by a crystal 20 connected between the clock and the XTAL input terminals to the micorprocessor 10. The crystal 20 may, for example, provide a frequency of 2 MHz. A resistor 21 is connected in parallel with the crystal 20.

The internal clock produces clock pulses at various times, one train of which appears at the terminal TPA. The TPA terminal of the microprocessor 10 is connected to the clock terminal of the ROM 11.

A resistor 47 is connected in series with a capacitor 48, the series being interconnected between the negative terminal 33 and round (VDD). The junction between the resistor 47 and capacitor 48 is connected to the CLEAR terminal to assure that the microprocessor is initialized properly when first connected to the batteries. Thus, the program will begin at memory location zero. Initially the capacitor has no charge, so that the Cl EAR signal is low (asserted). Then it charges up to make CLEAR high (not asserted) and the system begins to run.

The frequency of the clock pulses is of importance since the time the microprocessor utilizes in executing the instructions is directly dependent on the clock frequency. As will become apparent below, the time of execution of the various steps of the program loaded into the ROM 11 controls the width and period of the stimulation pulses generated by the pacer.

The output signal at the MRD terminal of the microprocessor 10 is connected to the ROM 11 to enable a memory read cycle whenever required by the microprocessor. The ROM 11, as mentioned above, has its address terminals connected to the memory address terminals of the microprocessor 10. Likewise. the various data terminals are connected to the BUS terminals of the microprocessor 10.

The various flag, wait, interrupt and clear terminals are tied high. The output of the microprocessor is derived at the Q output. which is connected to trigger or control the stimulation pulse generator 12.

The stimulation pulse generator 12 includes two n-p-n transistors 30 and 31. The transistor 30 has its emitter connected to a negative potential at terminal 33 and its collector connected via series resistor 34 to a ground terminal 35. The collector of the transistor 30 is connected to the emitter of the transistor 31. The transistor 31 has its base connected by a resistor 39 to a negative terminal 33, and its emitter connected by resistor 41 to the negative terminal 33.

The collector of the transistor 31 is connected by a resistor 43 to the ground terminal 35. A capacitor 44 is connected between the collector of the transistor 31 and the output terminal 13.

A zener diode 45 is connected between the output terminal 33 and the ground terminal 35 to protect the circuit against defibrillation voltages which may appear at the terminal 13.

The stimulation pulse generator 12, as mentioned above, is triggered by a pulse appearing on the Q output line of the microprocessor 10 applied via resistor 46 to the base of the transistor 30. When. however, the transistor 30 is triggered into conduction, the transistor 31 additionally conducts. The voltage built up upon the capacitor 38 between pulses is connected in series with the voltage of the power supply, thereby producing at the output terminal 13 a stimulation pulse of voltage determined by the sum of the voltage on the capacitor 38 and the supply voltage.

In order for the microprocessor 10 to control the stimulation pulse generator 12, electrical instruction signals are introduced into preselected address locations of the ROM 11. Thus electrical signals are introduced in accordance with the following table.

ROM Address ROM Contents Symbolic Instructions (hexadecimal) (hexadecimal) 00 7B Begin: SEQ 01 F8 19 LDI 25 03 A3 PLO R3 04 23 Delay 1: DEC R3 05 C4 NOP 06 83 GLO R3 07 3A 04 BNZ Delay 1 09 7A REQ OA F8 65 LDI 101 OC B3 PHI R3 OD .23 Delay 2 DEC R3 OE C4 NOP OF 93 GRI R3 10 3 A OD BNZ Delay 2 12 30 00 BRBegin 14 on Not Applicable The microprocessor 10 operates on and in response to the particular electrical signals within the ROM, in accordance with the predetermined instruction responses provided by the microprocessor manufacturer, substantially as follows. The first instruction at address 00 is 7B, which sets the Q output of the microprocessor to 1 (or high state). This triggers the transistor 30 of the stimulation pulse generator 12 into conduction, thereby producing an output pulse, in the manner above described. The transistor 30 will remain in the conducting state so long as the output on the Q terminal remains high.

The next instruction at address 01 loads the number at the ROM address 02 into the D accumulator (not shown) of the microprocessor 10. (The number 19 in hexadecimal notation corresponds to the decimal number 25.) The instruction at the ROM address 03 then transfers the number in the D accumulator into the low order byte of scratch pad register R(3) (not shown). The instruction at address 04 decrements the number in the low order byte of the R(3) scratch pad register by 1. Then, the instruction at the ROM address 06 fetches the number then existent in the low order byte of the scratch pad register R(3), and inserts it into the D register. The instruction at the address 07 in the ROM then dictates that if the number obtained from the R(3) scratch pad register is not zero, the program will return to address 04, which will decrement the R(3) contents by 1.

The process continues until a zero is found during the execution of the instruction at ROM address 07. Then, in accordance with the instruction at ROM address 09, the Q output is set to zero.

The setting of the Q output to zero will cause the transistor 30 to discontinue conduction.

and remain in a non-conducting state until the Q output again becomes high. Thus, the decrementing loop set forth by the instructions in the ROM addresses 01-07 essentially count the clock pulses produced by the clock until a sufficient time corresponding to the width of the pulse has been counted.

Then, the instruction contained in the ROM address OA is executed. That instruction dictates that the number contained in the ROM address OB is loaded into the D register. The number in the ROM address OB is the hexadecimal number 65, corresponding to the decimal number 101.

The operation dictated by the instruction at ROM adress OC moves the number in the D register to the high order byte of the scratch pad register R(3) (not shown). The instruction at the ROM address OD decrements the number in the scratch pad register R(3) by one. The instruction in the ROM address OF then brings the number in the upper byte of the scratch pad register R(3) back to the D register. Instruction at ROM address 10 then determines whether the number fetched is zero, and, if not, moves back to ROM address OD to repeat the decrementing process until the number in the upper byte of scratch pad register R(3) becomes zero. At that time, the program pointer points to the ROM address 12, which reinitiates the program moving back to ROM address 00, setting the Q output of the microprocessor 10 to a high state to again initiate conduction of the transistor 30.

Thus. the second portion of the instructions in the ROM addresses OA-12 repeats for a time corresponding to the period between the stimulation pulses desired. (Since the pulse width is initially counted in sequence with the time between the pulses, the time that the program is executing the second loop [instructions at ROM address OA- 12] is not strictly the period of the pulses, but, rather the time at which the Q output is at a low state.) The period, strictly speaking, is the time for execution of the entire program, including the repetitive looping within instructions 01-07 and OA-12.

It should be noted that the scratch pad register R(3) is two bytes (16 bits) long. The DEC R3 instruction's execution decrements the entire 16-bit quantity. In the first program section (locations 01-08), it is unimportant what is in the upper byte of R3. The lower byte is merely initialized and continually decremented and tested until it reaches zero. However, in the second program section (locations OA-13), the upper byte of R(3) is initialized, (the lower byte now being zero). The upper byte decrements by 1 for every 256 executions of the DEC R3 instruction (i.e., every time the lower byte decrements from 00 to FF). This along with the initialization value of 101, provides the long 819 MSEC delay.

Thus, the stimulation pulse generator 12 produces output pulses upon the terminal 13 in accordance with the instruction in the ROM 11 as read and executed by the microprocessor 10. It should be additionally pointed out that the instructions in the ROM 11 addresses illustrated serve two purposes. First, they provide instructions and data to the microprocessor 10, in a fashion ordinarily employed in microprocessor operations. Additionally, the execution of the various instructions, data fetch and the like, in conjunction with the clock pulses, provides the timing of the output produced at the Q terminal of the microprocessor 10. That is, the time of execution of the instructions in the ROM addresses 01-07 defines the width of the stimulation pulse produced at the output terminal 13. And, in like fashion. the time of execution of the instructions in the ROM addresses 09-12 defines the time period between the stimulation pulses. Consequently, the pulse timing of the stimulation pulses is controlled not only by the particular instructions in the ROM, but by the fact of the existance of the instructions and their execution as well. The importance of the clock frequency employed can therefore be appreciated. With a clock frequency of 2 MHz the instruction time for the RCA-CDP 1802 is 8 microseconds (using 16 clock cycles per instruction). Therefore. the stimulation pulses generated will be about 816 microseconds in width and be spaced about 819 milliseconds apart.

Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example. and that numerous changes in the details of construction and the combination and arrangement of parts may be resorted to without departing from the scope of the invention as hereinafter claimed.

WHAT WE CLAIM IS: 1. A heart pacer adapted to be connected to electrodes to a patient's heart. comprising: a stimulation pulse generator having an output for connection to said electrodes to deliver hear stimulation pulses thereto, a microprocessor having an output connected to control the output of said stimulation pulse generator and having a clock to control the speed at which said microprocessor executes instructions applied thereto, a memory having a program loaded thereinto having predetermined instructions therein to be executed by said microprocessor.

said microprocessor being operative to select certain program instructions from said memory and execute the selected instructions. including an instruction to produce an output to control the output of the stimulation pulse generator to produce a heart stimulation pulse, said instruction to control the output of the stimulation pulse generator being repeated and executed after a predetermined number of instructions have been executed, the order of instructions of said predetermined number of instructions being directed by said microprocessor and by the instructions of said program, whereby the time of the execution of the selected instructions of the program by the microprocessor determines the timing of the pulses of said stimulation generator.

2. The heart pacer of claim 1 wherein said program includes two portions. the time of execution of each of which corresponds respectively to the width of the stimulation pulse and the time between stimulation pulses produced by said stimulation pulse generator.

3. A heart pacer constructed. arranged and adapted to operate substantiaaly as hereinbefore described with reference to. and as illustrated in. the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. width is initially counted in sequence with the time between the pulses, the time that the program is executing the second loop [instructions at ROM address OA- 12] is not strictly the period of the pulses, but, rather the time at which the Q output is at a low state.) The period, strictly speaking, is the time for execution of the entire program, including the repetitive looping within instructions 01-07 and OA-12. It should be noted that the scratch pad register R(3) is two bytes (16 bits) long. The DEC R3 instruction's execution decrements the entire 16-bit quantity. In the first program section (locations 01-08), it is unimportant what is in the upper byte of R3. The lower byte is merely initialized and continually decremented and tested until it reaches zero. However, in the second program section (locations OA-13), the upper byte of R(3) is initialized, (the lower byte now being zero). The upper byte decrements by 1 for every 256 executions of the DEC R3 instruction (i.e., every time the lower byte decrements from 00 to FF). This along with the initialization value of 101, provides the long 819 MSEC delay. Thus, the stimulation pulse generator 12 produces output pulses upon the terminal 13 in accordance with the instruction in the ROM 11 as read and executed by the microprocessor 10. It should be additionally pointed out that the instructions in the ROM 11 addresses illustrated serve two purposes. First, they provide instructions and data to the microprocessor 10, in a fashion ordinarily employed in microprocessor operations. Additionally, the execution of the various instructions, data fetch and the like, in conjunction with the clock pulses, provides the timing of the output produced at the Q terminal of the microprocessor 10. That is, the time of execution of the instructions in the ROM addresses 01-07 defines the width of the stimulation pulse produced at the output terminal 13. And, in like fashion. the time of execution of the instructions in the ROM addresses 09-12 defines the time period between the stimulation pulses. Consequently, the pulse timing of the stimulation pulses is controlled not only by the particular instructions in the ROM, but by the fact of the existance of the instructions and their execution as well. The importance of the clock frequency employed can therefore be appreciated. With a clock frequency of 2 MHz the instruction time for the RCA-CDP 1802 is 8 microseconds (using 16 clock cycles per instruction). Therefore. the stimulation pulses generated will be about 816 microseconds in width and be spaced about 819 milliseconds apart. Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example. and that numerous changes in the details of construction and the combination and arrangement of parts may be resorted to without departing from the scope of the invention as hereinafter claimed. WHAT WE CLAIM IS:

1. A heart pacer adapted to be connected to electrodes to a patient's heart. comprising: a stimulation pulse generator having an output for connection to said electrodes to deliver hear stimulation pulses thereto, a microprocessor having an output connected to control the output of said stimulation pulse generator and having a clock to control the speed at which said microprocessor executes instructions applied thereto, a memory having a program loaded thereinto having predetermined instructions therein to be executed by said microprocessor.