GB1575814A - Electronic cross-conection panel - Google Patents

Electronic cross-conection panel Download PDF

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Publication number
GB1575814A
GB1575814A GB3086/77A GB308677A GB1575814A GB 1575814 A GB1575814 A GB 1575814A GB 3086/77 A GB3086/77 A GB 3086/77A GB 308677 A GB308677 A GB 308677A GB 1575814 A GB1575814 A GB 1575814A
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inputs
outputs
store
control
output
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Expired
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GB3086/77A
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Licentia Patent Verwaltungs GmbH
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Licentia Patent Verwaltungs GmbH
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Publication of GB1575814A publication Critical patent/GB1575814A/en
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04HBROADCAST COMMUNICATION
    • H04H60/00Arrangements for broadcast applications with a direct linking to broadcast information or broadcast space-time; Broadcast-related systems
    • H04H60/02Arrangements for generating broadcast information; Arrangements for generating broadcast-related information with a direct linking to broadcast information or to broadcast space-time; Arrangements for simultaneous generation of broadcast information and broadcast-related information
    • H04H60/04Studio equipment; Interconnection of studios

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Studio Circuits (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Electronic Switches (AREA)

Description

(54) AN ELECTRONIC CROSS-CONNECTION PANEL (71) We, LICENTIA PATENT VERWALTUNGS-GESELLSCHAFT MIT BESCHRANKTER HAFTUNG, a company organised under the laws of Germany, of Theodor-Stern-Kai 1, 6 Frankfurt/Main 70, Germany do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to electronic cross-connection panels for the selective connection of a plurality of inputs to a plurality of outputs.
In sound studio technique there exists the general problem of connecting numerous sources of input signals, such as microphones, record players and tape recorders, selectively to various output channels. In known manner there serve for this purpose so-called cross-connection panels, which have a controllable switch point for every possible input-output combination. If therefore twenty input sources are to be capable of connection to thirty output channels, a corresponding cross-connection panel includes 600 switch points.
In the connecting up of audio frequency leads via these switch points, frequently not only the useful LF signals but also control signals e.g. for the control of tape recorders must be connected up. In this manner the necessary expenditure on switch points corresponding to the number of addition switch points per useful LF signal increases in a multiplicative manner.
The inventor has realised that at the switch points for the control signals the demands made as regards the switching properties are not so great as those made at the switch points for the useful LF signal leads. Hence fewer switch points can be used, if they are operated in time multiplex.
The object of the invention is to provide an electronic cross-connection panel for the selective connection of any one of a plurality of inputs to any one of a plurality of outputs, in which the number of switch points is reduced in comparison with a conventional cross-connec tion panel and in which, with comparatively low expenditure on control means, there is achieved multiple use of the switch points and at the same time the possibility of selective association of the inputs and outputs with one another.
According to the invention there is provided an electronic cross connection panel, for use in a recording studio, for selectively connecting control signals and/or signals to be recorded from a plurality of first circuit points to a plurality of second circuit points, wherein the first and second circuit points are each connected, via controllable first and second switch means respectively, to a common bus bar, and wherein a control circuit is provided to control said selective connection, the control circuit including a cyclically running electronic counting means, the outputs of which are connected, on the one hand, to control inputs of the first switch means and, on the other hand, to inputs of a random access memory signal store, and wherein outputs of the signal store are connected to an output decoder provided for converting the store contents into numbers, the outputs of the decoder being connected to control inputs of the second switch means.
In order that the invention may be clearly understood and readily carried into effect, one embodiment thereof will now be described, by way of example only, with reference to the accompanying drawings, of which Figure 1 shows a circuit diagram of the principles of a cross-connection panel according to one example of the invention and Figure 2 is a block circuit diagram of a practical example of the invention.
In Figure 1 there is shown a block circuit diagram that serves to explain the principle of the cross-connection panel according to one example of the invention. It relates to an electronic equivalent of a conventional crossconnection panel which, for example, in a sound studio serves for the selective connection of a plurality of inputs 4 to a plurality of outputs 32 for the purpose of transmitting control signals. In the simplest case there are fed, via the connections of the inputs 4 to the outputs 32 to be established, digital control signals e.g.
for the control of tape recorders.
For greater clarity, of the inputs 4 only three inputs 1, 2 and 3 are shown. Each of these inputs is connected to a common bus-bar 11 via input switching means that consist of respective electronic switches 5,6 and 7. The switches 5, 6 and 7 are provided with respective control inputs 8,9 and 10 via which they can be switched on and off. The said control inputs are connected via control leads 12 to the outputs 14 of a ring counter 13. In the case in which the ring counter 13 has encoded outputs, a decoder is connected between these outputs and the control leads 12.
The electronic ring counter 13 is so constructed that at its outputs there appears a signal continuously in cyclic succession, which signal is utilised to control the switches 5,6 and 7. It will be appreciated that the switches 5,6 and 7 are switched on in succession in cyclic manner, so that correspondingly the inputs 1, 2 and 3 are connected in succession to the busbar 11.
The outputs 14 of the ring counter 13, which control the switches 5,6 and 7, are furthermore connected to the inputs 15 of a control device 34 which includes a so-called random access memory store (RAM store) 36. The control device 34 is so constructed that each of its inputs 15 has an associated storage location in which the address or the number of one of the outputs 21 of the control device 34 can be stored. When an input of the control device 34 is energised, there appears at its output a signal the address or number of which is stored in the storage location associated with the energised input.
The control device 34 also has a control input 20, via which it can be switched over from 'read' to 'write'. When therefore a signal is applied to this control input 20 the control device 34 switches over from the above described reading operation to "write". The association of the inputs with the outputs, i.e. the occupation of the storage locations of the control device 34, is then variable. For this purpose the control device 34 has one or more inputs 16, via which these storage locations can be selected, into which the address or number of the output to be associated can be delivered via further inputs 17. The selection of the storage locations is effected by a device 18 whilst the determination of the individual outputs is effected by a device 18 whilst the determination of the individual outputs is effected by a device 19.For changing over the mode of operation of the control device 34 there is provided a commutator 33 connected to the control input 20.
For the attainment of the above-described functions of the control device 34 this device includes, as has previously been mentioned a socalled RAM store 36. Such stores are commercially available and, in this example, the store 36 is so constructed that it includes a plurality of storage locations which are selectable via binary encoded inputs 38. In 'read' operation of such a store, there appears at the outputs 39 of the store 36 the contents of the storage location selected via the inputs 38. In the operation 'write', information located in write inputs 40 of the store 36 is loaded into the respective storage location selected via the binary encoded inputs 38. The number of storage locations in the present case equals the number of inputs 4.
In order to be able to deal with the information e.g. with continuous numbering I to 1 applied to the inputs 1 5 of the control device 34 viz. the number of the respective controlled input in the store 36, there is provided before the inputs 38 of the store 36 an encoder 35 for converting the numbers I to 1 into binary numbers. Correspondingly there is provided, between the outputs 39 of the store 36 and the outputs 21 of the control device 34, a decoder 37 for the conversion of binary numbers into continuous numbers 1 to m.
It is of course also possible to use, instead of the ring counter 13, a counter having binary encoded outputs, the outputs of which counter are connected to the inputs 38 of the store 36 without the intermediary of an encoder. In this case, however, a decoder is necessary which is connected between the outputs of the binary encoded ring counter and the control leads 12 of the switches 5,6 and 7.
The output signals of the control device 34 are used for controlling a plurality of electronic switches 24, 26 and 28, for which purpose the outputs 21 of the control device 34 are connected via control leads 22 to the respective control inputs 23,25 and 27 of the said switches.
The switches 24, 26 and 28 connect the bus-bar 11 to the outputs 29,30 and 31 respectively.
The cross-connection panel described therefore has the effect that the inputs 4 are connected cyclically to the bus-bar 11 and that, at the individual times at which an input 4 is connected to the bus-bar 11, in accordance with the relationship determined in the control device 34, a particular output 32 is likewise connected to the bus-bar 11. The frequency at which the counter 13 effects this connection of the inputs 4 to the outputs 32 is selected to be high such that the signals located on the inputs 4, are, in accordance with the sampling theorem, still switched to the outputs 32 with sufficient certainty.
In Figure 2 is illustrated a block diagram of a practical cross-connection panel according to one example of the invention. It relates to a panel for the selective connection of inputs 43 to outputs 83. The inputs 41 and 42 are connected, via electronic switches 45 and 47 respectively, to a common bus-bar 48. The outputs 84 and 85 are likewise connected, via respective electronic switches 86 and 88, to the bus-bar 48. The control inputs 44 and 46 of the input switches are connected to the outputs 49 of a decoder, the outputs I and I of the decoder 50 each being connected to a switch. Four further outputs I + I to 1+4 of the decoder 50 are used for controlling further functional groups described below.
The binary (20... .2n) inputs 51 of the decoder 50 are connected to the likewise binary encoded outputs 56 of a binary counter 55.
The decoder 50 serves for the conversion of the binary information on its inputs 51 into a continuously numbered number I to 1 + 4 on its outputs 49.
The binary counter 55 is controlled at its counting input 53 by a clock generator 52. It is so connected that it continuously passes cyclically through the range up to 1+4 in the manner of a ring counter. This is effected by a clearing input 54 (clear) of the binary counter 55 being connected to the output I + 4 of the decoder 50. In this manner the switches 44 to 46 are switched on successively in cyclic manner.
For the control of the switching of the output switch means 86 to 88 in synchronism with the switching of the input switch means 45 to 47 a RAM store 75, of the type described above, is provided. The binary encoded outputs 77 of the store 75 are connected to the binary encoded inputs 80 of a decoder 81, the continuously numbered outputs 82 (1 to k) of which are connected to the control inputs 87 to 89 of the switches 86 to 88.
The binary encoded addressing inputs 76 of the store 75 can be selectively connected to the outputs 56 of counter 55 by means of a commutator, or connected to the binary encoded outputs 66 of an intermediate store 67 used as an addressing store. The intermediate store 67 serves to accept and pass on the address located on its inputs 68, which address determines in which storage location of the RAM store 75 information is to be written during the "write" operation, to achieve association of the required outputs 83 with the inputs 43.
The said commutator device includes, for each input 76 of the store 75, two switches e.g.
the switches 58 and 63 or 60 and 65. The control inputs of the two switches associated at any time with an input 76 of the store 75, e.g. the control inputs 57 and 62 of the switches 58 and 63 or the control inputs 59 and 64 of the switches 60 and 65, are connected to the output of an inverting OR circuit 79, the control inputs 57 and 59 of the switches 58 and 60 located between the inputs 76 of the store 75 and the outputs 56 of the binary counter 55 being connected directly to the output of the said inverting OR circuit 79, and the control inputs 62 and 64 of the switches 63 and 65 located between the inputs 76 of the store 75 and the outputs 66 of the intermediate store 67 being connected via an inverter 61 to the output of the inverting OR circuit 79. In this manner the switches 58 and 60 are closed when the switches 53 and 65 are open, and conversely.
The inputs of the inverting OR circuit 79 are connected to the outputs I + I, l + 2 and I + 3 of the decoder 50, i.e.so long as there is a signal on one of these outputs the switches 63 and 65 are conducting. In contrast, so long as there is a signal on one of the inputs I to I of the decoder 50, the switches 58 and 60 are conducting. The meaning of this case to the store 75 is that the "read" operation is effective. The store 75 is so constructed that it stores information, via the inputs 74, only when there is a signal on the control input 78.
In "read" operation, the store 75 is therefore connected to the binary counter 55, i.e. the switches 86 to 88 are, corresponding to the relationship stored in the store 75, connected to the inputs 43 synchronously with these.
When after the passage of the outputs I and I of the decoder 50 a signal appears at the output I + I, the inputs 76 of the store 75 are switched over to the outputs 66 of the intermediate store 67. At the same time the intermediate store 67 is controlled at its control input 69 and a further intermediate store 71 is controlled at its control unit 70 in such manner that these intermediate stores take up the information on their inputs 68 and 73 respectively and store it at their outputs 66 and 72 in readiness for taking off. Upon the appearance of a signal at the output 1 + 3 of the decoder 50 the store 75 is, via its input 78, switched over momentarily to "write" operation, so that via the inputs 74 the information of the intermediate store 71 is loaded into the storage location that is selected by means of the information of the intermediate store 67.
In this way an output 83 different from the previous one is associated with one of the inputs 43.
When no new association is to occur during the running of the binary counter 55 the intermediate stores 67 and 71 are not supplied with information.
The relatively long lasting connection of the inputs 76 of the store 75 to the outputs 66 of the intermediate store 67 during three counting steps of the binary counter 55 has been selected in order to ensure sufficient security against differences in running times in the system described.
For this purpose the control inputs 87, 89 of the output switch means 86, 88 may advantageously be connected via the first inputs of logical linking members to the outputs 82 of the output decoder 81. The second inputs of the linking members are then connected to the clock generator 52. The linking members are so constructed that a signal appears at the output switch means 86, 88 only in the event of coincidence of clock and output signal at the output decoder 81.
It is possible to use, instead of the store 75 described, with the binary encoded inputs and outputs, a circuit which includes the decoder 50 and/or 81. However, this has point only when the number of storage locations of the store 75 is not too large, since an input and an output must then be provided for each storage location.
This would involve a relatively high expenditure on connections.
In addition to the transmission of digital control signals, the circuit arrangements described may be use for the switching of analog signals.
For the case in which LF signals are to be transmitted, the LF signals may advantageously be applied to the inputs of analog/digital converters. The outputs of these analog/digital converters are then connected to the input switch means of the cross-connection panels described, a separate connecting lead with associated input and output switch means being provided for each output of the analog/digital converter.
The control of these switch means may be effected by a common central control device with a RAM store.
The cross-connection panel described with reference to the two Figures may also be operated otherwise than with the direction of signal flow described, without alterations being necessary. Such operation enables, in advantageous manner, a plurality of outputs to be simultaneously associated with one input. In Figure 1 the circuit points 29 to 31 are then to be connected as inputs and the circuit points 1 to 3 as outputs, whilst in Figure 2, correspondingly, the circuit points 84, 85 are connected as inputs and the circuit points 41,42 as outputs. This means, e.g. in the panel according to Figure 1, that upon running of the counter 13 a plurality of the circuit points (outputs) 1 to 3 are connected to the same circuit point (input) 29.
If desired, there may be connected, to each of the circuit points connected up as outputs, a store which stores the state of the circuit points, connected up as inputs, conveyed by the busbar, until the next run of the counter.
WHAT WE CLAIM IS: 1. An electronic cross-connection panel, for use in a recording studio, for selectively connecting control signals and/or signals to be recorded from a plurality of first circuit points to a plurality of second circuit points, wherein the first and second circuit points are each connected, via controllable first and second switch means respectively, to a common bus-bar, and wherein a control circuit is provided to control said selective connection, the control circuit including a cyclically running electronic counting means, the outputs of which are connected, on the one hand, to control inputs of the first switch means and, on the other hand, to inputs of a variable random access memory signal store, and wherein outputs of the signal store are connected to an output decoder provided for converting the store content into numbers, the out puts of the decoder being connected to control inputs of the second switch means.
2. A panel according to claim 1, wherein the electronic counting means consists of a binary counter, the counting input of which is connected to the output of a clock generator.
3. A panel according to either of claims 1 or 2, wherein addressing inputs of the signal store, which can be used both for reading and writing, can be; connected, via electronic switch means, on the one hand to the outputs of the counting means and on the other hand to outputs of an addressing store via which the storage locations of the signal store to be programmed are controllable.
4. A panel according to claim 3, wherein the electronic switch means each consists of a commutator which includes an electronically controllable switch for each of the two signal paths that can be connected, and that a control voltage controlling the commutator is connected directly to the control input of the one electronic switch and is connected via an inverter to the control input of the other electronic switch.
5. A panel according to any of the preceding claims, wherein the counter is binary encoded, and between the outputs of the counter and the control inputs of the first switch means there is arranged a first decoder for the conversion of binary numbers into continuous numbers.
6. A panel according to claim 5, wherein the addressing inputs of the signal store are likewise binary encoded and that each output of the counter and a corresponding output of the addressing store are connected via a commutator to a corresponding addressing input of the signal store.
7. A panel according to claim 5 or any claim dependent thereon wherein control inputs of the commutator are connected to at least one additional output of the first decoder so that the mode of operation of the signal store is variable in each run of the counter.
8. A panel according to any preceding claim, wherein the signal store is provided with data inputs, which are binary encoded, for the reading of data for programming.
9. A panel according to claim 7, wherein a particular additional output of the first decoder is connected to a change-over control input of the signal store for changing the signal store from operation in the 'read' mode to operation in the 'write' mode and conversely, a signal appearing in each run of the counter first at one other additional output of the first decoder and thereupon at the particular additional output.
10. A panel according to claim 7, wherein a plurality of additional outputs are united via an OR circuit and are connected to the control
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (15)

**WARNING** start of CLMS field may overlap end of DESC **. output switch means 86, 88 only in the event of coincidence of clock and output signal at the output decoder 81. It is possible to use, instead of the store 75 described, with the binary encoded inputs and outputs, a circuit which includes the decoder 50 and/or 81. However, this has point only when the number of storage locations of the store 75 is not too large, since an input and an output must then be provided for each storage location. This would involve a relatively high expenditure on connections. In addition to the transmission of digital control signals, the circuit arrangements described may be use for the switching of analog signals. For the case in which LF signals are to be transmitted, the LF signals may advantageously be applied to the inputs of analog/digital converters. The outputs of these analog/digital converters are then connected to the input switch means of the cross-connection panels described, a separate connecting lead with associated input and output switch means being provided for each output of the analog/digital converter. The control of these switch means may be effected by a common central control device with a RAM store. The cross-connection panel described with reference to the two Figures may also be operated otherwise than with the direction of signal flow described, without alterations being necessary. Such operation enables, in advantageous manner, a plurality of outputs to be simultaneously associated with one input. In Figure 1 the circuit points 29 to 31 are then to be connected as inputs and the circuit points 1 to 3 as outputs, whilst in Figure 2, correspondingly, the circuit points 84, 85 are connected as inputs and the circuit points 41,42 as outputs. This means, e.g. in the panel according to Figure 1, that upon running of the counter 13 a plurality of the circuit points (outputs) 1 to 3 are connected to the same circuit point (input) 29. If desired, there may be connected, to each of the circuit points connected up as outputs, a store which stores the state of the circuit points, connected up as inputs, conveyed by the busbar, until the next run of the counter. WHAT WE CLAIM IS:
1. An electronic cross-connection panel, for use in a recording studio, for selectively connecting control signals and/or signals to be recorded from a plurality of first circuit points to a plurality of second circuit points, wherein the first and second circuit points are each connected, via controllable first and second switch means respectively, to a common bus-bar, and wherein a control circuit is provided to control said selective connection, the control circuit including a cyclically running electronic counting means, the outputs of which are connected, on the one hand, to control inputs of the first switch means and, on the other hand, to inputs of a variable random access memory signal store, and wherein outputs of the signal store are connected to an output decoder provided for converting the store content into numbers, the out puts of the decoder being connected to control inputs of the second switch means.
2. A panel according to claim 1, wherein the electronic counting means consists of a binary counter, the counting input of which is connected to the output of a clock generator.
3. A panel according to either of claims 1 or 2, wherein addressing inputs of the signal store, which can be used both for reading and writing, can be; connected, via electronic switch means, on the one hand to the outputs of the counting means and on the other hand to outputs of an addressing store via which the storage locations of the signal store to be programmed are controllable.
4. A panel according to claim 3, wherein the electronic switch means each consists of a commutator which includes an electronically controllable switch for each of the two signal paths that can be connected, and that a control voltage controlling the commutator is connected directly to the control input of the one electronic switch and is connected via an inverter to the control input of the other electronic switch.
5. A panel according to any of the preceding claims, wherein the counter is binary encoded, and between the outputs of the counter and the control inputs of the first switch means there is arranged a first decoder for the conversion of binary numbers into continuous numbers.
6. A panel according to claim 5, wherein the addressing inputs of the signal store are likewise binary encoded and that each output of the counter and a corresponding output of the addressing store are connected via a commutator to a corresponding addressing input of the signal store.
7. A panel according to claim 5 or any claim dependent thereon wherein control inputs of the commutator are connected to at least one additional output of the first decoder so that the mode of operation of the signal store is variable in each run of the counter.
8. A panel according to any preceding claim, wherein the signal store is provided with data inputs, which are binary encoded, for the reading of data for programming.
9. A panel according to claim 7, wherein a particular additional output of the first decoder is connected to a change-over control input of the signal store for changing the signal store from operation in the 'read' mode to operation in the 'write' mode and conversely, a signal appearing in each run of the counter first at one other additional output of the first decoder and thereupon at the particular additional output.
10. A panel according to claim 7, wherein a plurality of additional outputs are united via an OR circuit and are connected to the control
inputs of the commutator.
11. A panel according to claim 5, or any preceding claim dependent thereon, wherein the first decoder has an additional output on which a signal appears in each run of the counter and which is connected to an input of the counter for clearing the counter.
12. A panel according to claim 2 or any preceding claim dependent thereon, wherein control inputs of the second switch means are connected via logical linking members and their first input to the outputs of a second decoder, that second inputs of the linking members are connected to the clock generator and that the linking members are so constructed that only in the event of coincidence of clock and output signal at the second decoder does a signal appear at the second switch means.
13. A panel according to claim 2 or any preceding claim dependent thereon, wherein the frequency of the clock generator is at least as high as the product from the number of first circuit points and the highest frequency occurring at the first circuit points.
14. A panel according to any of the preceding claims, wherein there is connected, to each of the circuit points connected up as outputs, a store which stores the state of the circuit points, connected up as inputs, conveyed by the bus-bar, until the next run of the counter.
15. A electronic cross-connection panel substantially as herein described with reference to the accompanying drawings.
GB3086/77A 1976-01-28 1977-01-26 Electronic cross-conection panel Expired GB1575814A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2603081A DE2603081C3 (en) 1976-01-28 1976-01-28 Circuit arrangement for the optional connection of several inputs with several outputs

Publications (1)

Publication Number Publication Date
GB1575814A true GB1575814A (en) 1980-10-01

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GB3086/77A Expired GB1575814A (en) 1976-01-28 1977-01-26 Electronic cross-conection panel

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BE (1) BE850756A (en)
DE (1) DE2603081C3 (en)
DK (1) DK35177A (en)
FR (1) FR2340011A1 (en)
GB (1) GB1575814A (en)
IT (1) IT1085901B (en)
NL (1) NL7700699A (en)
SE (1) SE413166B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5516520A (en) * 1978-07-20 1980-02-05 Sony Corp Digital signal mixer

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1410916A (en) * 1971-10-05 1975-10-22 Emi Ltd Signal processing arrangements

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DK35177A (en) 1977-07-29
DE2603081B2 (en) 1979-10-11
FR2340011A1 (en) 1977-08-26
IT1085901B (en) 1985-05-28
BE850756A (en) 1977-05-16
DE2603081C3 (en) 1980-06-19
DE2603081A1 (en) 1977-08-04
NL7700699A (en) 1977-08-01
SE413166B (en) 1980-04-21
SE7700881L (en) 1977-07-29

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PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee