GB1573539A - Digital data processing apparatus - Google Patents

Digital data processing apparatus Download PDF

Info

Publication number
GB1573539A
GB1573539A GB20890/77A GB2089077A GB1573539A GB 1573539 A GB1573539 A GB 1573539A GB 20890/77 A GB20890/77 A GB 20890/77A GB 2089077 A GB2089077 A GB 2089077A GB 1573539 A GB1573539 A GB 1573539A
Authority
GB
United Kingdom
Prior art keywords
data
line
memory
signal
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB20890/77A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1573539A publication Critical patent/GB1573539A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Memory System (AREA)
  • Bus Control (AREA)
GB20890/77A 1976-06-07 1977-05-18 Digital data processing apparatus Expired GB1573539A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/693,816 US4095265A (en) 1976-06-07 1976-06-07 Memory control structure for a pipelined mini-processor system

Publications (1)

Publication Number Publication Date
GB1573539A true GB1573539A (en) 1980-08-28

Family

ID=24786235

Family Applications (1)

Application Number Title Priority Date Filing Date
GB20890/77A Expired GB1573539A (en) 1976-06-07 1977-05-18 Digital data processing apparatus

Country Status (6)

Country Link
US (1) US4095265A (https=)
JP (1) JPS52149445A (https=)
DE (1) DE2723467A1 (https=)
FR (1) FR2354597A1 (https=)
GB (1) GB1573539A (https=)
IT (1) IT1115319B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2308469A (en) * 1995-12-22 1997-06-25 Motorola Inc Power conserving clocking system

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US4174536A (en) * 1977-01-21 1979-11-13 Massachusetts Institute Of Technology Digital communications controller with firmware control
US4316244A (en) * 1978-11-08 1982-02-16 Data General Corporation Memory apparatus for digital computer system
US4234934A (en) * 1978-11-30 1980-11-18 Sperry Rand Corporation Apparatus for scaling memory addresses
US4390946A (en) * 1980-10-20 1983-06-28 Control Data Corporation Lookahead addressing in a pipeline computer control store with separate memory segments for single and multiple microcode instruction sequences
US4503491A (en) * 1981-06-29 1985-03-05 Matsushita Electric Industrial Co., Ltd. Computer with expanded addressing capability
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JPS5999505A (ja) * 1982-11-29 1984-06-08 Mitsubishi Electric Corp 電子ミシンの制御装置
US4631659A (en) * 1984-03-08 1986-12-23 Texas Instruments Incorporated Memory interface with automatic delay state
US4683551A (en) * 1984-03-28 1987-07-28 Minnesota Mining And Manufacturing Company Ram clock switching circuitry for a laser beam printer
US4918586A (en) * 1985-07-31 1990-04-17 Ricoh Company, Ltd. Extended memory device with instruction read from first control store containing information for accessing second control store
US5168558A (en) * 1986-01-29 1992-12-01 Digital Equipment Corporation Apparatus and method for providing distributed control in a main memory unit of a data processing system
US4954946A (en) * 1986-01-29 1990-09-04 Digital Equipment Corporation Apparatus and method for providing distribution control in a main memory unit of a data processing system
US4884198A (en) * 1986-12-18 1989-11-28 Sun Microsystems, Inc. Single cycle processor/cache interface
US5325513A (en) * 1987-02-23 1994-06-28 Kabushiki Kaisha Toshiba Apparatus for selectively accessing different memory types by storing memory correlation information in preprocessing mode and using the information in processing mode
US4918587A (en) * 1987-12-11 1990-04-17 Ncr Corporation Prefetch circuit for a computer memory subject to consecutive addressing
US5537602A (en) * 1988-09-16 1996-07-16 Hitachi, Ltd. Process system for controlling bus system to communicate data between resource and processor
US5335337A (en) * 1989-01-27 1994-08-02 Digital Equipment Corporation Programmable data transfer timing
US5247636A (en) * 1990-05-31 1993-09-21 International Business Machines Corporation Digital processor clock circuit
US5280587A (en) * 1992-03-31 1994-01-18 Vlsi Technology, Inc. Computer system in which a bus controller varies data transfer rate over a bus based on a value of a subset of address bits and on a stored value
JPH11272606A (ja) * 1998-03-19 1999-10-08 Fujitsu Ltd バス制御装置
US6081904A (en) * 1998-04-30 2000-06-27 International Business Machines Corporation Method for insuring data integrity during transfers
US6732203B2 (en) 2000-01-31 2004-05-04 Intel Corporation Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus
KR100464034B1 (ko) * 2002-07-19 2005-01-03 엘지전자 주식회사 클록 동기화 방법
US7334116B2 (en) * 2004-10-06 2008-02-19 Sony Computer Entertainment Inc. Bit manipulation on data in a bitstream that is stored in a memory having an address boundary length
KR20150019268A (ko) * 2013-08-13 2015-02-25 에스케이하이닉스 주식회사 데이터 입출력 장치 및 이를 포함하는 시스템

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US3641328A (en) * 1966-06-23 1972-02-08 Hewlett Packard Co Keyboard entry means and power control means for calculator
US3535560A (en) * 1967-06-09 1970-10-20 Nasa Data processor having multiple sections activated at different times by selective power coupling to the sections
US3659275A (en) * 1970-06-08 1972-04-25 Cogar Corp Memory correction redundancy system
US3688280A (en) * 1970-09-22 1972-08-29 Ibm Monolithic memory system with bi-level powering for reduced power consumption
FR2109452A5 (https=) * 1970-10-16 1972-05-26 Honeywell Bull Soc Ind
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US3753232A (en) * 1972-04-06 1973-08-14 Honeywell Inf Systems Memory control system adaptive to different access and cycle times
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US3900836A (en) * 1973-11-30 1975-08-19 Ibm Interleaved memory control signal handling apparatus using pipelining techniques
DE2364408C3 (de) * 1973-12-22 1979-06-07 Olympia Werke Ag, 2940 Wilhelmshaven Schaltungsanordnung zur Adressierung der Speicherplätze eines aus mehreren Chips bestehenden Speichers
US3943495A (en) * 1973-12-26 1976-03-09 Xerox Corporation Microprocessor with immediate and indirect addressing
FR2256705A5 (https=) * 1973-12-27 1975-07-25 Cii
US4025771A (en) * 1974-03-25 1977-05-24 Hughes Aircraft Company Pipe line high speed signal processor
US3911424A (en) * 1974-09-05 1975-10-07 Ibm Alphanumeric character display scheme for programmable electronic calculators
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US3983544A (en) * 1975-08-25 1976-09-28 International Business Machines Corporation Split memory array sharing same sensing and bit decode circuitry

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2308469A (en) * 1995-12-22 1997-06-25 Motorola Inc Power conserving clocking system

Also Published As

Publication number Publication date
FR2354597B1 (https=) 1980-02-08
FR2354597A1 (fr) 1978-01-06
DE2723467A1 (de) 1977-12-22
US4095265A (en) 1978-06-13
IT1115319B (it) 1986-02-03
JPS52149445A (en) 1977-12-12

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee