GB1573293A - Switching device - Google Patents

Switching device Download PDF

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Publication number
GB1573293A
GB1573293A GB913878A GB913878A GB1573293A GB 1573293 A GB1573293 A GB 1573293A GB 913878 A GB913878 A GB 913878A GB 913878 A GB913878 A GB 913878A GB 1573293 A GB1573293 A GB 1573293A
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GB
United Kingdom
Prior art keywords
switching
operational amplifier
switching elements
operational
amplifiers
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Expired
Application number
GB913878A
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Individual
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Individual
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Priority to GB913878A priority Critical patent/GB1573293A/en
Publication of GB1573293A publication Critical patent/GB1573293A/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor

Description

(54) SWITCHING DEVICE (71) I, ANATOLY VASILIEVICH FURMAN of kvartira 6, 21, ulitsa Chkalova, Zhukovsky Moskovskoi oblasti, Union of Soviet Socialist Republics (U,S.S.R.) a citizen of the U.S.S.R., do hereby declare the invention, for which I pray that a patent may be granted to me, and the method by which it is to be performed to be particularly described in and by the following statement-: The present invention relates to means for switching electrical signals and more particularly it relates to a switching device.
It may be advantageously used in precision DC signal commutators and especially so in electrical signal multiplexers.
The object of this invention is to provide a switching device with a low and stable value of residual voltage across the contacts of the active switching circuit in the closed state.
The above and other objects of the inventions are attained in a switching device in accordance with the invention which comprises two identical active switching components and two identical operational amplifier null bias voltage memory circuits, each active switching component being formed by an operational amplifier and switching elements connected with the operational amplifier to provide 100% negative feedback when said switching elements are conducting; and in which an input of each of the memory circuits is connected to an output of the switching component operational amplifiers and an output of each of the memory circuits is connected to a non-inverting input of the switching component operational amplifiers, the output of the first memory circuit being connected to the non-inverting input of the operational amplifier to whose output is connected the second memory circuit, and the output of the second memory circuit being connected to the noninverting input of the operational amplifier to whose output is connected the first memory circuit.
Each operational amplifier null bias voltage memory circuit may comprise a capacitor one of the leads thereof being connected to a center tap of the operational amplifier supply source, while the other lead is connected through a switching element to the non-inverting input of one operational amplifier and through a charging switching element, to the output of the other operational amplifier, and two switching elements adapted to short-circuit the inputs of the operational amplifier at the moment of memorizing, one of said switching elements being connected between the output of the operational amplifier and the inverting input thereof, while the other, between the non-inverting input and the center tap of the operational amplifier supply sources.
Such an arrangement provides for drastic reduction of residual voltage and its instability across the closed active switching component.
The invention will now be explained in greater detail with reference to the embodiments thereof which are reprsented in the accompanying drawings, wherein: Figure 1 is a block diagram of the switching device according to the invention; Figure 2 is a schematic circuit diagram of the switching device according to the invention.
The switching device, according to the invention, comprises two active switching components and each consisting essentially of an operational amplifier 1, 2 (Figure 1), and two null bias voltage memory circuits 3, 4 of said amplifiers 1, 2. Each operational amplifier 1, 2 is connected in a 100 70 negative feedback circuit by switching elements 5, 6, 7, 8. The taps of con nection of the switching elements 5 and 6, 7 and 8 serve as output terminals 9 and 10 of the switching device. The inputs of the circuits 3 and 4 are connected to the outputs 11 and 12 of the amplifiers 1 and 2. The output of the circuit 3 is connected to the non-inverting input 13 of the operational amplifier 2, the output of the circuit 4 is connected to the non-inverting input 14 of the operational amplifier 1.
Each null bias voltage memory circuit 3 and 4 comprises respectively a capacitor 15, 16 (Figure 2), the first lead of said capacitor being connected to a center tap 17 of the operational amplifier 1, 2 supply sources 18, 19. The second lead of the capacitors 15, 16 is connected through a respective switching element 20, 21 to noninverting inputs 14, 13 of the amplifiers 1, 2, the lead of the capacitor 15 being connected through a switching element 20 to the non-inverting input 13 of the amplifier 2, and the lead of the capacitor 16 through a switching element 21 to the non-inverting input 14 of the amplifier 1.
Besides, the second lead of each capacitor 15, 16 is connected to the output 11, 12 of the amplifiers 1, 2 respectively through charging switching elements 22, 23.
Each null bias voltage memory circuit 3, 4 (Figure 1) also comprises two switching elements 24, 25 and 26, 27 (Figure 2) adapted to short-circuit the inputs of the operational amplifier 1, 2. The switching elements 24, 26 are connected between the outputs 11, 12 of the respective amplifier 1, 2 and the inverting input 28, 29 thereof, and the switching elements 25, 27 between the non-inverting input 14, 13 of the respective amplifier 1, 2 and the center tap 17 of the amplifier 1, 2 supply sources 18, 19.
The switching device operates as follows.
When a control unit (not shown) supplies a signal in the memory mode, the switching elements 22-27 are closed, now the non-inverting inputs 14, 13 of the operational amplifiers 1, 2 are connected to the center tap 17 of the supply sources 18, 19 of said operational amplifiers 1, 2. The switching elements 24, 26 connect the inverting inputs 28, 29 of the operational amplifiers to the outputs 11, 12 thereof thus providing the amplifiers with 100 percent negative feedback.
Voltages from the outputs 11, 12 of the operational amplifiers 1, 2 through the charging switching elements 22, 23 charge the capacitors 15 and 16 to a level of the null bias voltage of a corresponding operational amplifier. In the switching mode, the control unit signal closes the switching elements 5, 6, 7, 8, 20, 21 while the switching elements 22-27 open. The memorized values of the operational amplifiers 1, 2 null bias voltages are fed through the switching elements 20, 21 to the non-inverting inputs 14, 13 of the respective operational amplifiers 1, 2.In the switching mode the operational amplifiers 1, 2 are provided with 100 percent negative feedback by the switching elements 5, 6 and 7, 8 so that voltages equal to the algebraic sums of the original null bias voltage of one amplifier and the memorized value of the null bias voltage of the other operational amplifier exist at the outputs 11, 12 of the operational amplifiers 1, 2.
The null bias voltages of the operational amplifiers 1, 2 are inserted in said algebraic sums with the same sign, since the memorized values of the null bias voltage are applied to the non-inverting inputs of the operational amplifiers 1, 2. The connection of the active switching components is such that a difference between the algebraic sums of voltages existing at the outputs of the operational amplifiers 1, 2 appears between the input terminals 9, 10 and in as much as said sums include similar members with similar signs, the voltage difference between terminals 9, 10 is zeroed. Thus a complete compensation for a residual voltage, by which is meant the algebraic sum of the null bias voltage of both operational amplifiers 1 and 2, is effected across the input terminals 9, 10 of the switching device is effected.
WHAT WE CLAIM IS: 1. A switching device comprising two identical active switching components and two identical operational amplifier null bias voltage memory circuits, each active switching component being formed by an operational amplifier and switching elements connected with the operational amplifier to provide 100% negative feedback when said switching elements are conducting; and in which an input of each of the memory circuits is connected to an output of the switching component operational amplifiers and an output of each of the memory circuits is connected to a non-inverting input of the switching component operational amplifiers, the output of the first memory circuit being connected to the non-inverting input of the operational amplifier to whose output is connected the second memory circuit, and the output of the second memory circuit being connected to the non-inverting input of the operational amplifier to whose output is connected the first memory circuit.
2. A switching device as claimed in claim 1, wherein each operational amplifier null bias voltage memory circuit comprises a capacitor whose one lead is connected to
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (3)

  1. **WARNING** start of CLMS field may overlap end of DESC **.
    nection of the switching elements 5 and 6, 7 and 8 serve as output terminals 9 and 10 of the switching device. The inputs of the circuits 3 and 4 are connected to the outputs 11 and 12 of the amplifiers 1 and 2. The output of the circuit 3 is connected to the non-inverting input 13 of the operational amplifier 2, the output of the circuit 4 is connected to the non-inverting input 14 of the operational amplifier 1.
    Each null bias voltage memory circuit 3 and 4 comprises respectively a capacitor 15, 16 (Figure 2), the first lead of said capacitor being connected to a center tap
    17 of the operational amplifier 1, 2 supply sources 18, 19. The second lead of the capacitors 15, 16 is connected through a respective switching element 20, 21 to noninverting inputs 14, 13 of the amplifiers 1, 2, the lead of the capacitor 15 being connected through a switching element 20 to the non-inverting input 13 of the amplifier 2, and the lead of the capacitor 16 through a switching element 21 to the non-inverting input 14 of the amplifier 1.
    Besides, the second lead of each capacitor 15, 16 is connected to the output 11, 12 of the amplifiers 1, 2 respectively through charging switching elements 22, 23.
    Each null bias voltage memory circuit 3, 4 (Figure 1) also comprises two switching elements 24, 25 and 26, 27 (Figure 2) adapted to short-circuit the inputs of the operational amplifier 1, 2. The switching elements 24, 26 are connected between the outputs 11, 12 of the respective amplifier 1, 2 and the inverting input 28, 29 thereof, and the switching elements 25, 27 between the non-inverting input 14, 13 of the respective amplifier 1, 2 and the center tap 17 of the amplifier 1, 2 supply sources 18, 19.
    The switching device operates as follows.
    When a control unit (not shown) supplies a signal in the memory mode, the switching elements 22-27 are closed, now the non-inverting inputs 14, 13 of the operational amplifiers 1, 2 are connected to the center tap 17 of the supply sources 18,
    19 of said operational amplifiers 1, 2. The switching elements 24, 26 connect the inverting inputs 28, 29 of the operational amplifiers to the outputs 11, 12 thereof thus providing the amplifiers with 100 percent negative feedback.
    Voltages from the outputs 11, 12 of the operational amplifiers 1, 2 through the charging switching elements 22, 23 charge the capacitors 15 and 16 to a level of the null bias voltage of a corresponding operational amplifier. In the switching mode, the control unit signal closes the switching elements 5, 6, 7, 8, 20, 21 while the switching elements 22-27 open. The memorized values of the operational amplifiers 1, 2 null bias voltages are fed through the switching elements 20, 21 to the non-inverting inputs 14, 13 of the respective operational amplifiers 1, 2.In the switching mode the operational amplifiers 1, 2 are provided with 100 percent negative feedback by the switching elements 5, 6 and 7, 8 so that voltages equal to the algebraic sums of the original null bias voltage of one amplifier and the memorized value of the null bias voltage of the other operational amplifier exist at the outputs 11, 12 of the operational amplifiers 1, 2.
    The null bias voltages of the operational amplifiers 1, 2 are inserted in said algebraic sums with the same sign, since the memorized values of the null bias voltage are applied to the non-inverting inputs of the operational amplifiers 1, 2. The connection of the active switching components is such that a difference between the algebraic sums of voltages existing at the outputs of the operational amplifiers 1, 2 appears between the input terminals 9, 10 and in as much as said sums include similar members with similar signs, the voltage difference between terminals 9, 10 is zeroed. Thus a complete compensation for a residual voltage, by which is meant the algebraic sum of the null bias voltage of both operational amplifiers 1 and 2, is effected across the input terminals 9, 10 of the switching device is effected.
    WHAT WE CLAIM IS: 1. A switching device comprising two identical active switching components and two identical operational amplifier null bias voltage memory circuits, each active switching component being formed by an operational amplifier and switching elements connected with the operational amplifier to provide 100% negative feedback when said switching elements are conducting; and in which an input of each of the memory circuits is connected to an output of the switching component operational amplifiers and an output of each of the memory circuits is connected to a non-inverting input of the switching component operational amplifiers, the output of the first memory circuit being connected to the non-inverting input of the operational amplifier to whose output is connected the second memory circuit, and the output of the second memory circuit being connected to the non-inverting input of the operational amplifier to whose output is connected the first memory circuit.
  2. 2. A switching device as claimed in claim 1, wherein each operational amplifier null bias voltage memory circuit comprises a capacitor whose one lead is connected to
    a center tap of the operational amplifier supply sources and the other lead is connected through a switching element to the non-inverting input of the first operational amplifier and through a charging switching element to the output of the second operational amplifier, and two switching elements adapted to short-circuit the inputs of the operational amplifier at the moment of memorizing, one of said switching element being connected between the output of the operational amplifier and the inverting input thereof, and the other between the non-inverting input and the center tap of the operational amplifier supply sources.
  3. 3. A switching device substantially as herein described with reference to and as illustrated in the accompanying drawings.
GB913878A 1978-03-08 1978-03-08 Switching device Expired GB1573293A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB913878A GB1573293A (en) 1978-03-08 1978-03-08 Switching device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB913878A GB1573293A (en) 1978-03-08 1978-03-08 Switching device

Publications (1)

Publication Number Publication Date
GB1573293A true GB1573293A (en) 1980-08-20

Family

ID=9866108

Family Applications (1)

Application Number Title Priority Date Filing Date
GB913878A Expired GB1573293A (en) 1978-03-08 1978-03-08 Switching device

Country Status (1)

Country Link
GB (1) GB1573293A (en)

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PCNP Patent ceased through non-payment of renewal fee