GB1569594A

GB1569594A - Semiconductor data stores

Info

Publication number: GB1569594A
Application number: GB35104/76A
Authority: GB
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1975-09-08
Filing date: 1976-09-08
Publication date: 1980-06-18
Also published as: FR2323210A1; DE2539910B2; DE2539910A1; DE2539910C3

Description

(54) IMPROVEMENTS IN OR RELATING TO SEMICONDUCTOR DATA STORES (71) We, SIEMENS AKTIENGESELL- SCHAFT, a German Company of Berlin and Munich, German Federal Republic, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The invention relates to semiconductor data stores comprising a plurality of storage cells each provided with a storage capacitance.

It is known to construct semiconductor stores by MOS techniques. For example, the storage cells of such semiconductor stores consist of a storage capacitance and a MOS transistor, whose control electrode is connected to a word line. The two controlled electrodes of the MOS transistor lie between the storage capacitance and a bit line.

Storage cells of this type are usually referred to as one-transistor RAM cells (Random Access Memory cells).

Figure 1 shows the cross-section through one such known storage cell. A bit line BL is diffused in a semiconductor substrate SU.

A further diffused zone GE is arranged adjacent to the bit line BL in the semiconductor substrate. A part of the bit line BL and a zone GE form the two controlled electrodes of the MOS-transistor. A control electrode G is arranged on the substrate, but insulated from the diffused zones BL and GE, in a construction of this sort, to lie over a channel K of the MOS-transistor, which channel K is located between the zones BL and GE when the said transistor is rendered conductive. An electrode SE is provided to form a storage capacitance SK, this electrode SE being arranged parallel to the surface of the semiconductor substrate SU and insulated from the semi-conductor substrate by a silicon oxide layer. If a suitable voltage is connected to the electrode SE, a conductive inversion layer connected to the zone GE is formed at the surface of the semiconductor substrate.

The electrode SE, together with this inversion layer, then form the storage capacitance SK. The whole structure is covered with an insulating layer IS, consisting e.g. of SiO2.

The control electrode G is connected to a word line at a point which has not been shown.

A disadvantage of this one-transistor storage cell consists in that space is required for the diffused zones, e.g. the zone GE in each storage cell of an integrated module.

However, as many storage cells as possible are required to be arranged on one storage module in such semiconductor data stores, so it is desirable to design the individual storage cells to be as small as possible.

In a publication contained in the IEEE Journal of Solid State Circuits, Vol. SC 7 No. 5, October 1972, pages 330 to 335, a possibility of reducing the size of individual RAM-storage cells is disclosed, in which the storage capacitance is formed in the same way as described for the one-transistor storage cell. To this end a so-called storage electrode is arranged above the semi-conductor substrate, but insulated in relation to the substrate, in order to form the storage capacitance. Adjacent to the storage capacitance the bit line is diffused into the semiconductor substrate. In order to facilitate an exchange of charge between the storage capacitance and the bit line, the so-called transfer electrode is arranged on the semiconductor substrate and insulated from the latter, which transfer electrode at least partially overlaps the storage capacitance and the bit line. If corresponding voltages are connected to the storage electrode, the transfer electrode and the bit line, charges can be transferred between the bit line and the storage capacitance. As the construction and mode of operation of this storage cell is described in detail in the quoted publication, it will not be discussed in detail here.

Further it is known for the transfer electrode and the storage electrode to be formed by a common word line or by a common electrode connected to the word line, and to use one or more insulating layers to obtain the different spacings of the transfer electrode and the storage electrode from the semiconductor substrate surface and from the bit line in order to achieve a greater threshold voltage at the transfer electrode than at the storage electrode.

A disadvantage of the known storage cell constructions may consist in that the word line simultaneously forms the transfer electrode. As the spacing of the transfer electrode from the substrate between the storage electrodes and the bit line and of the transfer electrode to the bit line in the overlapped zone cannot be selected to be too great, in order to facilitate a satisfactory exchange of charge, the danger exists that capacitative couplings between a word line and a bit line will disturb the function of such a storage cell. A further disadvantage consists in that separate terminals are required for the electrodes and for the bit line of each cell.

One object of the present invention is to provide a construction of a data store comprising a storage cell which consists of a storage capacitance and a transfer electrode in such manner that the number of terminals per storage cell is reduced.

The invention consists in a semiconductor data store in which a plurality of storage cells addressed by bit lines and word lines are provided for the storage of respective items of information, each said cell containing a storage capacitance formed between a storage electrode arranged in insulated fashion above the semiconductor substrate and an inversion layer, a transfer electrode arranged in insulated fashion above the semi-conductor substrate to control the passage of a charge between the storage capacitance and a bit line, said transfer electrode being adjacent to the storage electrode and the bit line, and the arrangement being such that the threshold voltage connected to the transfer electrode which must be exceeded for the transmission of any charge from the bit line to the storage capacitance is greater than the threshold voltage which must be exceeded across the storage elec- trode for the production of the inversion layer, said transfer electrode and said storage electrode being electrically connected together, the said cells being arranged in a plurality of pairs, each of said pairs having either a common bit line region diffused in the semiconductor substrate or a common storage electrode, and the two cells of each pair of cells being symmetrically arranged with respect to the common bit line region or to the common storage electrode.

The transfer electrode and the storage electrode are thus connected to one another in respect of each storage cell and only require one outer terminal. Here it is expedient to select the thickness of the insulating layer between the transfer electrode and the surface of the semiconductor substrate to be greater than the thickness of the insulating layer between the storage electrode and the semiconductor substrate. The outcome is that the threshold voltage for the transfer electrode, which must be exceeded in order to instigate a charge transfer, is greater than the threshold voltage for the storage electrode which must be exceeded to form the storage capacitance.

Either holes or electrons can be used as charge carriers. If electrons are used as charge carriers, a negative substrate voltage is connected to the semiconductor substrate.

On the other hand, on the read-out of an item of information from a storage cell or the write-in of an item of information into a storage cell, a first voltage which is positive in relation to the substrate voltage is connected to the transfer electrode. In order to erase the information in the storage cell, on the transfer electrode the first voltage is switched over to the substrate voltage. The voltage of the inversion layer assigned to the storage electrode thus becomes temporarily more negative than the substrate voltage. The result is that the item of information stored in the storage capacitance is erased via the semiconductor substrate due to recombination of the charge carriers.

In the event of the non selection of the storage cell, the transfer electrode is operated by a second voltage the value of which is between the first voltage and the substrate voltage. Shortly before the read-out of an item of information from a storage cell, the bit line is supplied with the second voltage as preparation voltage. During the read-out of an item of information, the bit line is not connected to any supply voltage.

If the bit line is completely diffused into the semiconductor substrate, it is expedient to construct the transfer electrode and the storage electrode from a common line consisting of polysilicon and to arrange the word line above this common line and insulated therefrom. The word line is connected, through the insulating layer with the common line of the transfer electrode and the storage electrode.

If the bit line is diffused into the semiconductor substrate only in the region of the storage cell, it is expedient for the word line to simultaneously form the storage electrode and the transfer electrode. The word line and the storage electrode, and the transfer electrode, thus lie directly above but separated by an insulating layer from the surface of the semiconductor substrate. Then the remaining part of the bit line is arranged above the storage electrodes and the transfer electrodes, but separated therefrom by another insulating layer. This remaining part of the bit line is only connected, in the region of the storage cell, to that part of the bit line which is diffused into the semiconductor substrate, As the thickness of the insulating layer between the remaining part.

of the bit line and the transfer electrode and storage electrode and the word line can be selected to be considerable, the capacitive coupling between the bit line and the word line can be made small.

The invention will now be described with reference to the drawings in which: Figure 1 shows the cross-section of the known cell described above; Figure 2 schematically illustrates one exemplary embodiment of a storage cell forming part of a data store constructed in accordance with the invention, Figure 3 is a simplified circuit arrangement with the aid of which the function of the proposed storage cell will be explained.

Figure 4 is a set of explanatory voltage diagrams illustrating the function of the proposed storage cell.

Figure 5 is a set of explanatory symbols showing how the individual structures of the storage cells are represented in Figures 6 to 9; Figure 6 is a plan view which illustrates the etching structure of a first embodiment of a pair of storage cells forming part of a data store constructed in accordance with the invention Figure 7 is a cross-section through the storage cells shown in Figure 6; Figure 8 is a plan view which illustrates the etching structure of another exemplary embodiment of a pair of storage cell, and Figure 9 is a cross-section through the storage cells shown in Figure 8.

Figure 2 is a fundamental illustration of an exemplary storage cell forming part of a data store constructed in accordance with the invention. This storage cell consists of a storage electrode SP which is arranged above a semiconductor substrate SU, and a transfer electrode TE which is arranged above both the storage electrode SP and the semiconductor substrate. The transfer electrode TE and the storage electrode SP are insulated from the semiconductor substrate SU, but a connection is provided between the transfer electrode TE and the storage electrode SP. The thickness of the insulating layer between the transfer electrode and the surface of the semiconductor substrate SU is greater than the thickness of the insulating layer between the storage electrode SP and the surface of the semiconductor substrate SU. In the semiconductor substrate, a bit line BL is diffused in, at least in the region of the storage cell.

A storage capacitance SK is formed with the aid of the storage electrode SP. The exchange of charge between the storage capacitance SK and the bit line BL occurs with the aid of the transfer electrode TE, If charge is to be transferred between the bit line BL and the storage capacitance SK, the transfer electrode TE, in common with the storage electrode SP, is operated by a pulse. In dependence upon which potential exists on the bit line DL, there is either an exchange of charge with the bit line, or there is not.

Figure 3 shows a circuit arrangement which will serve to explain the function of the storage cell, making reference to the set of voltage diagrams shown in Figure 4.

The function of the transfer electrode is represented by a transier-MOS-transistor TM, whose control electrode is connected to a word line WL. The word line WL is also connected to the storage electrode SP which forms a storage capacitance CS.

As already described above, the storage capacitance is produced by inversion. An inversion layer E (Figure 7 or 9) is thereby formed at the substrate surface. This inversion layer E is connected to one of the operated electrodes of the transfer-MOStransistor. A capacitance also exists between the inversion layer E and the substrate. This capacitance is represented with the aid of a diode O and is a blocking layer capacitance. The substrate is connected to a substrate voltage VSUB. Also shown is a capacitance CB which exists between the bit line BL and the substrate SU.

It will also be noted that the effective capacitance which serves to store the information is composed of the storage capacitance and the blocking layer capacitance. However, the storage capacitance has the predominant influence on the effective capacitance.

Now, with reference to Figure 4, the function of the storage cell will be represented.

Here it has been assumed that electrons are used as charge carriers. As the thickness of the insulating layer between the transfer electrode and the surface of the semiconductor substrate is greater than that between the storage electrode and the surface of the semiconductor substrate, the threshold voltages for the transfer transistor TM and the storage capactor CS are different. For example, the thickness of the insulating layer between the transfer electrode and the surface of the semiconductor substrate can be selected to be 0.6 microns, and the thickness of the insulating layer between the storage electrode and the surface of the semiconductor substrate can be selected to be 0.1 microns. Then the threshold voltage UTT for the transfer transistor is, e.g. from 5 to 7 V, and the threshold voltage UTS for the storage capacitor is from 0.5 to 1.5 V. The substrate voltage VSUB can be selected to be -UTT = -5 V. The first voltage VH, which characterises the binary state "1" can be established as a voltage from 2 to 2.5 times UTT, and the second voltage VL, which characterises the binary state "0" can be established as a voltage of from 0 to 0.5 V.

Naturally, it is also possible to use positive holes as charge carriers, the quoted voltages being changed accordingly.

In Figure 4, voltages V are plotted against time t. The uppermost row shows the voltages of the word line WL the second row shows the voltages on the bit line BL, and the third row shows the voltages at the inversion layer E.

At a time to (Figure 4) the transfer transistor TM is not operated, the voltage VL is connected to the word line WL, and the bit line BL which is to be prepared for read-out carries the voltage VL. In dependence upon the stored item of information, the inversion layer E has a voltage value of VSUB ("0"') or VH-UTT ("1").

The transfer transistor TM is thus blocked, as its source, which in this case is the inversion layer E, always has a smaller potential relative to the control electrode (WL) than the requisite threshold voltage UTT.

At a time 11 the time in which an item of information is to be read out from the storage cell commences. Now the word line WL is raised from the voltage VL to the voltage VH. Accordingly, the storage electrode SP is also raised to the voltage VH.

As a result of a capacitive voltage distribution between the storage capacitance CS and the blocking layer capacitance CD, the inversion layer E is likewise raised in voltage, as shown in the third row of Figure 4.

However, the inversion layer E immediately discharges to the bit line BL, as the transfer transistor TM is driven conductive by the high voltage VH on the word line WL. In this case the bit line BL acts as source for the transfer transistor TM. In dependence upon the item of information in the storage cell which is shown as a solid line in the second and third rows of Figure 4 for the binary state "1" and as a broken line for the binary state "0", a different quantity of charge is transferred to the bit line BL, this producing varying degrees of change in the potential of the bit line. These conditions are represented in the second row of Figure 4. The potential on the bit line BL is fed to an amplifier. which is not illustrated in the Figure. This can for example be a pulsed flip-flop, as described in the publication IEEE International Solid-State Conference, Digest of Technical Papers, 1973, p.30, 31, 195. The read-out amplifier evaluates the potentials on the bit line, which it amplifies and feeds back to the bit line at a time tl*. The bit line B1 is hereby either brought to a voltage VH, in the case of the information state "1", or to the voltage VL in the case of the information state "0". As the transfer transistor TM is in the conductive state, the inversion layer E is influenced accordingly. It can either simply follow -UTT up to the potential VH in the case of "1", as otherwise the transfer transistor becomes blocked, or in the case of a "0" it is discharged via the transfer transistor TM to the voltage VL.

From a time t2 onwards, the information in the storage cell is erased. To this end, the word line WL is switched over from VH to the substrate voltage VSUB. As a result of the capacitive voltage division between the storage capacitance CS and the blocking layer capacitance CD, the inversion layer B is brought to such a potential that it becomes more negative than the semiconductor substrate SU. In this case the inversion layer E is poled in the forward direction in relation to the substrate, so that it is again raised to the potential VSUB by charge carriers from the substrate. This process is simulated by the diode O in Figure 3, In this way, the information contained in the inversion layer E has been overwritten and erased. The transfer transistor TM remains blocked during the whole of the "erase" process.

From a time t3 onwards, a pause is interposed, in which the word line WL is not operated, and reverts to the voltage VL.

The aforementioned capacitive voltage distribution between the storage capacitance CS and the blocking layer capacitance CD also raises the potential of the inversion layer E.

In any case the inversion layer now contains the information "1". Here too the transfer transistor TM remains blocked. Attention is drawn to the fact that the interposition of such a pause during the operation in the storage cell is not necessary. It is also possible to pass immediately from the erase process to the record process.

The record process commences at a time t4, when the word line WL is switched to the second voltage VH again. In dependence upon the item of information to be written in, the bit line BL carries the voltage VH or VL. In the former case, the inversion layer E is raised in potential by the capacitive voltage distribution between the storage capacitance CS and the blocking layer capacitance CD as the transfer transistor TM remains blocked. In the latter case, the inversion layer E is fixed at the voltage VL by the transfer transistor TM which has been rendered conductive.

At a time t5 the write-in process is ended and the storage cell returns to the rest state, the word line WL being switched back to the voltage VL. Independently of the item of information, the inversion layer E is reduced by the capacitive voltage division between the storage capacitance CS and the blocking capacitance CD. However, in the case of the information state "0" it is held at the voltage VL until the transfer transistor TM is blocked.

Thus it will be clear from the description of the function of the storage cell that the information in the storage cell is erased via the semiconductor substrate. Also the process can be such that only the information state "0" can be written into the storage cell.

In the function of the storage cell it has been stated that the differences in the threshold voltages of the transfer transistor TM and the storage capacitor CS can be established by the differing thicknesses of the insulating layer between the transfer electrode and the surface of the semiconductor substrate, and between the storage electrode and the surface of the semiconductor substrate. However, differences in the threshold voltages can also be produced by additional diffusion or implantation in the region of the transfer electrode.

In the following the technological construction of two exemplary storage cell constructions will be described.

Figure 5 illustrates the symbols used for the individual structures of the storage cells which are shown in the following Figures.

A chain-dotted line is used to outline the bit line BL diffused into the substrate Figures 6 to 9, the capacitors SK in Figures 6 and 8, and the transfer electrode TE in Figure 8, whilst a broken line represents the latter with the storage electrode SP (Figure 6 and 7), the word line WL, transfer electrode TE and storage electrode SP (Figure 8 and 9), whilst a continuous line is otherwise used to represent the contours of the word-line WL and the bit line BLM.

The etching structures of a symmetrical pair of storage cells can be seen from Figure 6. The individual etching structures can be recognised with the aid of the representation symbols shown in Figure 5. It will be clear that for the pair of storage cells, the transfer electrodes and the storage electrodes are connected to one another.

The bit lines BL and the inversion layers E for the storage capacitances SK are arranged in the substrate. Then the storage electrode SP and the transfer electrode TE, e.g. in the form of a polysilicon layer, are arranged on the substrate and insulated therefrom. As next layer the word line WL, which for example can be produced from metal, is applied in a manner to be insulated from the storage electrode SP and the transfer electrode TE. In order to connect the word line WL to the transfer electrode TE and the storage electrode SP, the word line WL is contacted through a window in the insulating layer, by a contact KT shown at the middle of Figure 6. Also shown are the transfer electrodes TE of the storage cells.

It will be clear from Figure 6 that the bit line BL and the word line WL ars arranged at right angles to one another, The extent of the storage capacitance 5K, the transfer electrode TE and the storage electrode SP are also shown.

Figure 7 is a cross-section through the storage cells on the line VIl-VIl indicated in Figure 6, and shows the manner in which the individual layers are arranged one above another.

The bit line B is diffused into the semiconductor substrate SU. The inversion layer E is arranged adjacent to the bit line BL, but not electrically conductively connected thereto. For the formation of the storage capacitance SK, the storage SP is arranged above the semiconductor substrate SU, and is insulated from the semiconductor substrate by an insulating layer 151, e.g. a silicon oxide layer. In the region of the storage capacitance SK this layer extends parallel to the substrate surface and at a relatively short distance therefrom. If a suitable voltage is connected to the storage electrode SP, in the manner explained, then an inversion layer E forms in the semiconductor substrate SU, and may be used to store an item of information.

The storage electrode SP extends further and merges into the transfer electrode TE.

The distance of the transfer electrode TE from the substrate surface is greater than the distance of the storage electrode SP from the substrate surface. The transfer electrode TE partly overlaps the bit line BL. The transfer electrode TE ensures that a charge can be transferred from the bit line BL to the storage capacitance SK, or vice versa.

-The distance of the transfer electrode TE from the bit line BL must be selected to be such that this transfer of charge is possible.

Finally the word line WL is arranged above the transfer electrode TE and the storage electrode SP, but is separated therefrom, and from the bit line, by an insulating layer IS2 consisting for example of silicon oxide. Only at the actual point at which it is necessary to connect the word line with the supply line to the storage electrode SP, is the word line WL contacted through a window in the insulating layer 152 at a contact point KT. The thickness of the insulating layer IS2 between the word line WL and the bit line BL can be selected to be such that only small capacitive couplings exist between the two lines.

As can be seen from Figures 6 and 7, two storage cells are arranged to form a symmetrical pair, with the storage electrodes SP of the two storage cells connected to one another. This type of design has the advantage that the word line WL need only be contacted once to the supply lines to the storage electrodes SP.

Figures 8 and 9 show the design of an alternative form of storage cell in which the bit line BL is diffused into the semiconductor substrate SU only in the region of each storage cell. The storage electrodes SP and the transfer electrodes TE form a part of the word line WL. The bit line member BLM, which is not diffused into the semiconductor substrate, lies at right angles to the word line WL. The word line WL, the storage electrode SP and the transfer eleo trode TE can be produced from polysilicon.

The bit line member BLM can consist of metal.

Figure 9 is a cross-section through the storage cell along the line IX-IX shown in Figure 8. Again two storage cells form a symmetrical pair and are commonly represented. In the region of the storage cell a part of the bit line BL is diffused into the semiconductor substrate SU. The transfer electrode TE is arranged adjacent to the bit line BL. This transfer electrode is separated from the semiconductor substrate surface by an insulating layer IS3. The transfer electrode TE overlaps the bit line BL.

The transfer electrode TE is connected to the storage electrode SP. An insulating layer IS4 is arranged between the storage electrode SP and the substrate surface. The storage electrode SP, the insulating layer IS4, and the inversion layer E form the storage capacitance SK. As can be seen from Figure 9, the thickness of the insulating layer IS3 is greater than the thickness of the insulating layer IS4.

Above the word line WL and storage electrode SP, and the transfer electrode TE is arranged the bit line member BLM which is separated from the latter by an insulating layer IS5. The bit line member BLM is contacted through the insulating layer IS5 to that region of the bit line BL which is diffused in the semiconductor substrate. The thickness of the insulating layer IS5 can be selected to be such that capacitive coupling between the bit line member BLM and the word line WL is slight.

WHAT WE CLAIM IS: 1. A semiconductor data store in which a plurality of storge cells addressed by bit lines and word lines are provided for the storage of respective items of information, each said cell containing a storage capacitance formed between a storage electrode arranged in insulated fashion above the semiconductor substrate and an inversion layer, a transfer electrode arranged in insulated fashion above the semiconductor substrate to control the passage of a charge between the storage capacitance and a bit line, said transfer electrode being adjacent to the storage electrode and the bit line, and the arrangement being such that the threshold voltage connected to the transfer electrode which must be exceeded for the transmission of any charge from the bit line to the storage capacitance is greater than

Claims

**WARNING** start of CLMS field may overlap end of DESC **. one another. This type of design has the advantage that the word line WL need only be contacted once to the supply lines to the storage electrodes SP. Figures 8 and 9 show the design of an alternative form of storage cell in which the bit line BL is diffused into the semiconductor substrate SU only in the region of each storage cell. The storage electrodes SP and the transfer electrodes TE form a part of the word line WL. The bit line member BLM, which is not diffused into the semiconductor substrate, lies at right angles to the word line WL. The word line WL, the storage electrode SP and the transfer eleo trode TE can be produced from polysilicon. The bit line member BLM can consist of metal. Figure 9 is a cross-section through the storage cell along the line IX-IX shown in Figure 8. Again two storage cells form a symmetrical pair and are commonly represented. In the region of the storage cell a part of the bit line BL is diffused into the semiconductor substrate SU. The transfer electrode TE is arranged adjacent to the bit line BL. This transfer electrode is separated from the semiconductor substrate surface by an insulating layer IS3. The transfer electrode TE overlaps the bit line BL. The transfer electrode TE is connected to the storage electrode SP. An insulating layer IS4 is arranged between the storage electrode SP and the substrate surface. The storage electrode SP, the insulating layer IS4, and the inversion layer E form the storage capacitance SK. As can be seen from Figure 9, the thickness of the insulating layer IS3 is greater than the thickness of the insulating layer IS4. Above the word line WL and storage electrode SP, and the transfer electrode TE is arranged the bit line member BLM which is separated from the latter by an insulating layer IS5. The bit line member BLM is contacted through the insulating layer IS5 to that region of the bit line BL which is diffused in the semiconductor substrate. The thickness of the insulating layer IS5 can be selected to be such that capacitive coupling between the bit line member BLM and the word line WL is slight. WHAT WE CLAIM IS:

1. A semiconductor data store in which a plurality of storge cells addressed by bit lines and word lines are provided for the storage of respective items of information, each said cell containing a storage capacitance formed between a storage electrode arranged in insulated fashion above the semiconductor substrate and an inversion layer, a transfer electrode arranged in insulated fashion above the semiconductor substrate to control the passage of a charge between the storage capacitance and a bit line, said transfer electrode being adjacent to the storage electrode and the bit line, and the arrangement being such that the threshold voltage connected to the transfer electrode which must be exceeded for the transmission of any charge from the bit line to the storage capacitance is greater than the threshold voltage which must be exceeded across the storage electrode for the production of the inversion layer, said transfer electrode and said storage electrode being electrically connected together, the said cells being arranged in a plurality of pairs, each of said pairs having either a common bit line region diffused in the semiconductor substrate or a common storage electrode, and the two cells of each pair of cells being symmetrically arranged with respect to the common bit line region or to the common storage electrode.

2. A semiconductor data store as claimed in Claim 1 in which the difference between the two threshold voltages is determined by mutually different thicknesses of the insulating layer disposed between the transfer electrode and the substrate surface, and an insulating layer disposed between the storage electrode and the substrate surface.

3. A method of operating a semiconductor data store as claimed in Claim 1 or Claim 2, in which a substrate voltage is connected to the semiconductor substrate such that if electrons are to serve as charge carriers, on the read-out of an item of information from a storage cell or the writein of an item of information into a storage cell, the transfer electrode is operated by a first voltage which is positive in relation to the substrate voltage, whilst for the erasure of the information in a storage cell the transfer electrode is operated with a voltage which is less than or equal to the substrate voltage so that the information is erased via the semiconductor substrate, and in any non-selected storage cell, the respective transfer electrode is operated with a second voltage lying between the first voltage and the substrate voltage.

4. A method as claimed in Claim 3, in which the second voltage is connected as a preparation voltage to the bit line prior to the read-out of an item of information from a storage cell.

5. A semi-conductor data store as claimed in Claim 1, in which in each cell the bit line is diffused into the semiconductor substrate, said transfer electrode and said storage electrode consist of a common line, and said word line is contacted through a window in its insulating layer to connect with the common line.

6. A semiconductor data store as claimed in Claim 5, in which said word line consists of metal.

7. A semiconductor data store as

claimed in Claim 5, in which said common line consists of polysilicon.

8. A semiconductor data store as claimed in any of Claim 1 and Claims 5 to 7, in which said word line simultaneously forms said storage electrodes and said transfer electrodes, said bit line only being diffused into the semiconductor substrate in the region of the storage cell, and otherwise being arranged above the word lines as a bit line member separated from the word lines by an insulating layer having a respective window in the region of the storage cell through which is contacted the bit line diffused into the semiconductor substrate.

9. A semiconductor data store as claimed in Claim 8, in which said bit line member consists of metal.

10. A semiconductor data store as claimed in claim 8, in which said word line consists of polysilicon.

11. A semiconductor data store substantially as described with reference to Figures 2, 3, 6 and 7, or Figures 2, 3, 8 and 9 of the accompanying drawings.

Reference has been directed in pursuance of section 9, subsection (1) of the Patents Act 1949, to Patent No. 1,374,721.