DE2539910B2 - Semiconductor memory - Google Patents

Description

The invention relates to a semiconductor memory which is described in the preamble of claim 1 specified type

It is known to build semiconductor memories using MOS technology. For example, the memory cells are made of such semiconductor memories from a storage capacity and a MOS transistor, its control electrode is connected to a word line. The two controlled electrodes of the MOS transistor are connected between the storage capacity and a bit line. Such memory cells are usually single transistor RAM cells called (DE-OS 24 22 136).

The cross section through such a memory cell is shown in FIG. 1, a device BL is diffused into a semiconductor substrate SU . A further diffused region GE is provided in the semiconductor substrate adjacent to the bit line BL. Part of the bit line BL and the area GE form the two controlled electrodes of the MOS transistor. The control electrode G is provided on the substrate but isolated from the diffused regions BL and GE. With a structure of this type, the so-called channel K of the MOS transistor is located between the areas BL and GE when it is switched on. Furthermore, an electrode SE is provided, with the aid of which the storage capacitance SK is formed. This electrode SE is arranged parallel to the surface of the semiconductor substrate SU and insulated from the semiconductor substrate by a silicon oxide layer.If a suitable voltage is applied to the electrode SE, a conductive layer is formed on the surface of the semiconductor substrate by inversion, which is connected to the area GE .

The electrode SE together with the inversion layer then result in the storage capacity SK. The whole previous structure is finally still by an insulating layer / 5, z. B. covered from SiO ₂ The control electrode G is connected to a word line at a point not shown.

A disadvantage of this single transistor memory cell is that for the diffused areas, e.g. B. GE, space is required in the memory module. However, since as many memory cells as possible should be arranged on a memory module in semiconductor memories, there is a tendency to make the individual memory cells as small as possible.

From IEEE Journal of Solid State Circuits, Vol. SC 7, No. 5, October 1972, pages 330 bis 335, a possibility has become known, according to which the

individual RAM memory cells can be reduced in size. In the solution given there, the Storage capacity formed in the same way as it has been described for the single transistor memory cell For this purpose, a so-called storage electrode is used to form the storage capacity above the semiconductor substrate, but isolated from this, placed adjacent to the storage capacitance is the bit line in the Semiconductor substrate diffused into it To enable Bitleitu & £, the so-called transfer electrode is placed on the semiconductor substrate and insulated from it arranged, which at least partially overlaps the storage capacity and the bit line to the Corresponding voltages are then applied to the storage electrode, the transfer electrode and the bit line charges can be transferred between the bit line and the storage capacitance. Since the construction and the mode of operation of this memory cell is described in detail in the cited literature reference will not be discussed further.

A disadvantage of the memory cell shown in the cited reference is that the Word line at the same time forms the transfer electrode Da is the distance between the transfer electrodes and the substrate between the storage electrodes and the bit line and the transfer electrode to the bit line in the overlapped The area chosen must not be too large in order to enable a flawless charge exchange the risk that capacitive couplings between the word line and the bit line the function of a interfere with such a memory cell. To eliminate this The disadvantage has been proposed (DE-OS 25 32 594), the thickness of the insulating layers between the word line and to choose the bit line or the transfer electrode to the bit line of different sizes. Another The disadvantage is that a separate electrode is used for both the storage electrode and the transfer electrode Connection is required

The object on which the invention is based is to provide a memory cell that consists of a storage capacity and a transfer electrode is to be constructed in such a way that the number of connections per memory cell is decreased. This task is given in accordance with the characterizing part of claim 1 Features solved

The transfer electrode and the storage electrode are therefore connected to one another for each storage cell and only need an external connection. It is useful to adjust the thickness of the insulating layer between so to choose the transfer electrode and the surface of the semiconductor substrate greater than the thickness of the Insulating layer between the storage electrode and the semiconductor substrate The consequence is that the initiation of the charge transfer to be exceeded threshold voltage for the transfer electrode is greater than that for Formation of the storage capacity threshold voltage to be exceeded for the storage electrode.

Both holes and electrons can be used as charge carriers. Are electrons called Charge carriers are used, then a negative substrate voltage is applied to the semiconductor substrate connected. On the other hand, when information is read from a memory cell, it is applied to the transfer electrode or when writing information in a memory cell, an opposite voltage to the substrate positive first voltage applied. To erase the information in the memory cell, the transfer electrode is pressed the substrate voltage applied. This means that the voltage at the storage electrode is assigned Inversion layer briefly more negative than the substrate voltage. The consequence is that in the storage capacity Stored information about the semiconductor substrate is deleted (recombination of the charge carriers). If the memory cell is not selected, the transfer electrode is subjected to a second voltage which is in its value between the first voltage and the substrate voltage is activated. The bit line is shortly before reading information from a memory cell with the second voltage as the preparation voltage supplied While information is being read, the bit line is not connected to any supply voltage.

If the bit line is completely diffused into the semiconductor substrate, then it is expedient to use the Build up the transfer electrode and the storage electrode from a common line made of polysilicon and to arrange the word line above this common line and isolated from it. The word line is through the insulating layer with the common line of the transfer electrode and the Contacted storage electrode

If the bit line only diffuses into the semiconductor substrate in the area of the memory cell, then it is expedient that the word line forms the storage electrode and the transfer electrode at the same time The word line or the storage electrode and the transfer electrode are thus separated by a Insulating layer directly over the surface of the semiconductor substrate. Above the storage electrodes and the transfer electrode is then, separated by a further insulating layer, the remaining part of the bit line arranged. This is only in the area of the memory cell that diffuses into the semiconductor substrate Part of the bit line contacted. Because the thickness of the insulating layer between the bit line and the transfer electrode or storage electrode or word line can be selected to be large, is the capacitive coupling between the bit line and the word line is low.

Further developments of the invention emerge from the subclaims.

The invention is further developed on the basis of exemplary embodiments which are shown in the figures explained it shows

F i g. 1 the already described cross section through a single transistor memory cell in MOS technology,

F i g. 2 shows a schematic diagram of the memory cell according to the invention,

F i g. 3 shows a circuit arrangement with the aid of which the function of the memory cell is explained,

F i g. 4 shows a voltage diagram to explain the function of the memory cell;

Fig.5 used in the following figures Types of representation of the individual structures of the memory cells,

F i g. 6 the etched structure of a first embodiment of the memory cell,

F i g. 7 shows a cross section through the memory cell according to FIG. 6,

F i g. 8 the etched structure of a further embodiment of the memory cell,

F i g. 9 shows a cross section through the memory cell of FIG. .

In Fig. 2 shows a basic diagram of the memory cell according to the invention. This memory cell consists of a storage electrode SP, which is arranged over the semiconductor substrate SU and a trans-

ferelectrode TE, which is arranged both above the storage electrode SP and the semiconductor substrate. The transfer electrode TE and the storage electrode SP are insulated from the semiconductor substrate SU. However, there is a connection between the transfer electrode TE and the storage electrode SR. The thickness of the insulating layer between the transfer electrode and the surface of the semiconductor substrate Si / is greater than the thickness of the insulating layer between the storage electrode SP and the surface of the semiconductor substrate SU.

The bit line BL is diffused into the semiconductor substrate at least in the area of the memory cell

With the help of the storage electrode SP storage capacity SK is formed The exchange of charge between the storage capacity of SK and the bit line BL by means of the transfer electrode TE target charge between the bit line BL and the storage SK are transferred, the transfer electrode TE is in common with the storage electrode SP controlled by an impulse. Depending on which potential exists on the bit line BL , a charge exchange with the bit line takes place or not

In Fig. 3 shows a circuit arrangement by means of which the function of the memory cell is explained. The voltage diagram in FIG. 4 is used as an aid for this purpose. The function of the transfer electrode is represented by a transfer MOS transistor TM , the control electrode of which is connected to the word line WL . The storage electrode SP, which forms a storage capacitance CS, is also located on the word line WL. The storage capacity is, as has already been described above, generated by inversion, is affixed to the substrate surface, an inversion layer E This inversion layer E is connected to one of the controlled electrodes of the transfer MOS transistor. Moreover, there is a capacitance between the inversion layer fund the substrate This capacitance is represented by means of a diode CD, it is a junction capacitance to the substrate is applied a substrate voltage VSUB is also still the Bitleitungskäpazität CB shown that exists between the bit line BL and the substrate

It should also be noted that the effective capacity for storing the information is derived from the storage capacity and the junction capacitance composed the predominant influence on the effective But capacity has the storage capacity

With the aid of FIG. 4, the function of the memory cell will now be shown. It is assumed that electrons are used as charge carriers. Since the thickness of the insulating layer between the transfer electrode and the surface of the semiconductor substrate is greater than that between the storage electrode and the surface of the semiconductor substrate, the threshold voltages for the transfer transistor TM and the storage capacitor CS are different. For example, the thickness of the insulating layer between the transfer electrode and the surface of the semiconductor substrate can be selected to be 0.6 μm and the thickness of the insulating layer between the storage electrode and the surface of the semiconductor substrate to be 0.1 μm. Then the threshold voltage UTT for the transfer transistor z. B. 5 to 7 volts, the threshold voltage UTS for the storage capacitor 0.5 to 1.5 volts. The substrate voltage VSUB = -UIT = -5 volts can be selected. The voltage from 2 to 2 ^ χ UTT can be set as the first voltage VH, which identifies the binary "1", and a voltage from 0 to 04 volts can be set as the second voltage VL, which identifies the binary "0".

It is of course also possible to use positive holes as charge carriers. Then they change specified voltages accordingly.

In Fig. 4 voltages V are plotted against time
applied. Row 1 shows the voltages on word line WL, row 2 shows the voltages on bit line BL and the third row shows the voltages on inversion layer E.

(G F i. 4) at time 1 0 is the Transfertransi sturgeon TM not driven Then Hegt to the word line WL, the voltage VL, the bit line BL should be prepared for reading and is located on the voltage VL The inversion layer E has, depending on the stored information a Voltage value of VSUB [M) or VK (»1«). The transfer transistor TM is blocked because its source, in this case the inversion layer E, always has a smaller potential distance to the control electrode (WL) than a threshold voltage t / TT

Are mixed with 1 1, the time begins in which information read from the memory cell is now to the word line WL of the voltage VL is increased to the voltage VH. Correspondingly, the storage electrode SP is also raised to the voltage VH . The voltage of the inversion layer E is also raised by a capacitive voltage division across the storage capacity CS and the junction capacity CL , as shown in line 3 of FIG. 4 is shown, but the inversion layer E discharges immediately again towards the bit line BL , since the transfer transistor TM is controlled to be conductive with the high voltage VH on the word line WL. In this case, the bit line BL acts as a source for the transfer transistor TM. Depending on the information in the memory cell - solid lines in lines 2 and 3 of FIG. 4 corresponds to a “1”, the dashed line corresponds to a “0” - if a charge of different sizes is transferred to the bit line BL , these charges cause changes in the potential of the bit line of different sizes. These ratios are shown in line 2 of Figure 4, the potential on the bit line BL is supplied to an amplifier, not shown in the figure This may. B. be a clocked flip-flop, as it emerges from the IEEE International Solid-State Conference, Digest of Technical Papers, 1973, pages 30, 31, 195 The sense amplifier evaluates the potentials on the bit line, amplifies them and carries them back to the bit line at the time rl *. The bit line BL is pulled either to the voltage VH for the information "1" or to the voltage VL for the information "0". Since the transfer transistor TM is in the conductive state, the inversion layer E is influenced accordingly. It can either only follow up to the potential VH -UTT with a "1", otherwise the transfer transistor is blocked or it is switched off with a "0" via the transfer transistor TM discharged to the voltage VL.

From the time ti, the information is deleted in the memory cell by the word line WL of VH after the substrate voltage VSUB is turned on by the capacitive voltage division over the memory CS and the Sperrschichtkapazitäl CD is the inversion layer E pulled so far to negative potentials, that it is more negative than the semiconductor substrate SU. In this case the inversion

layer E is polarized in the forward direction with respect to the substrate, so that it is raised again to the potential VSUB by charge carriers from the substrate. This process is indicated by the diode CD in FIG. 3 simulated. The information contained in the inversion layer E was thus overwritten and deleted. The transfer transistor TM remains blocked during the entire "delete" process.

From the point in time f3, a pause is again inserted, during which the word line WL is not activated. The word line WL is then switched back to the voltage VL . As a result of the capacitive voltage division already mentioned via the storage capacitance CS and the junction capacitance CD , the inversion layer £ is also raised in terms of potential. It now always contains the information "1". Here, too, the transfer transistor TM remains blocked. It should be noted that it is not necessary to insert such a pause when operating the memory cell. It is also possible to go from the "erase" process to the "write" process straight away.

The “writing” process begins at time 14. The word line IVL is now switched back up to the second voltage VH . The bit line BL is at voltage VH or VL depending on the information to be written. In the first case, the inversion layer E is raised in terms of potential by the capacitive voltage division across the storage capacitance CS and the junction capacitance CD , since the transfer transistor TM remains blocked. In the second case, the inversion layer E is held at the voltage VL by the conductive transfer transistor TM.

At time (5, the writing is finished and the memory cell returns to the idle state. For this purpose, the word line IVL is switched back to the voltage VL. The inversion layer E is lowered independently of the information by the capacitive voltage division across the storage capacitance CS and the junction capacitance CD However, with the information "0" it is held at the voltage VL until the transfer transistor TM is blocked

Thus, it can be seen from the description of the function of the memory cell that the information the memory cell is erased via the semiconductor substrate. Only information can also be stored in the memory cell "0" must be written in.

In the function of the memory cell it has been stated that the differences in the threshold voltages of the transfer transistor TM and the storage capacitor CS are determined by the different thicknesses of the insulating layer between the transfer electrode and the surface of the semiconductor substrate and between the storage electrode and the surface of the semiconductor substrate. However, differences in the threshold voltages can also be generated by additional diffusion (implantation) in the area of the transfer electrode.

In the following, the technological structure of the memory cell is described in two examples.

The individual structures of the memory cells, as shown in the following figures, result from FIG. Shown are the word line WL (FIGS. 6 and 7) and the bit line BLM (FIGS. 8 and 9), the bit line BL diffused into the substrate, the transfer electrode TE with the storage electrode SP (FIGS. 6 and 7 ) or the word line IVL, transfer electrode Tf and storage electrode SP ( FIGS. 8 and 9).

The etched structures of two memory cells arranged next to one another can be seen from FIG. On the basis of the modes of representation in FIGS. 5 the individual etched structures can be recognized. It can be seen that the transfer electrodes and the storage electrodes are connected to one another for the two memory cells lying next to one another.
The bit lines BL and the inversion layers F for

ίο the storage capacities SK are arranged in the substrate. On the substrate, the storage electrode SP and the transfer electrode TE are then insulated from the substrate, e.g. B. provided as a polysilicon plant. Insulated from the storage electrode SP and the transfer electrode TE

ι5 is the next layer the word line IVL, the z. B. can be made of metal, arranged. To connect the word line WL to the transfer electrode TE and the storage electrode SP, the word line WL is contacted through the insulating layer. Such a contact KT is in the middle of FIG. 6, the transfer electrodes TE of the memory cells are also shown

From Fig. 6 shows that the bit line BL and the word line WL are arranged perpendicular to one another.

The expansion of the storage capacitance SK, the transfer electrode TE and the storage electrode SP also results.

In Fig. 7 shows a cross section through the memory cells at point VII-VII

The individual layers are still on top of each other better recognized.

The bit line B, which has diffused into the semiconductor substrate, is located in a semiconductor substrate SU. The inversion layer E is arranged adjacent to the bit line BL, but not connected in an electrically conductive manner. In order to form the storage capacitance SK , the storage electrode SP is provided above the semiconductor substrate SU. The storage electrode SP is from the semiconductor substrate by an insulating layer / 51, e.g.

a silicon oxide layer, insulated. It runs in the area of the storage capacity SK parallel to the substrate surface and at a relatively small distance therefrom. If a suitable voltage is applied to the storage electrode SP , then, in the manner already explained, an inversion layer E is formed in the semiconductor substrate SU , which is used to store information.

The storage electrode SP is extended further and merges into the transfer electrode 72 :. The distance of the

so the transfer electrode TE to the substrate surface is greater than the distance between the storage electrode SP and the substrate surface. The transfer electrode TE somewhat overlaps the bit line BL. With the aid of the transfer electrode TE, it is achieved that the charge can be transferred from the bit line BL to the storage capacitance SK , or vice versa

Transfer electrode TE from bit line BL must be so

be chosen so that this charge transfer is possible

Above the transfer electrode TE or the

Finally, the storage electrode SP is also arranged with the word line WL. B. made of silicon oxide from the transfer electrode TE, the storage electrode SP and the bit line BL separated only at the point where contact between the word line and the lead to the storage electrode SP is necessary, the word line WL is contacted through the insulating layer / 52. This contact point is marked with / CT The thickness of the insulating layer

/ S 2 between the word line WL and the storage electrode SP or the transfer electrode TE can be selected so that only slight capacitive coupling exists between the two lines.

As can be seen from FIGS. 6 and 7, two storage cells are arranged next to one another. The storage electrodes SP of the two storage cells are connected to one another. Such an embodiment has the advantage that the word line WL only has to be contacted once with the leads to the storage electrode SP.

F i g. 8 and 9 show the design of the memory cell in the event that the bit line BL is only diffused into the semiconductor substrate SU in the region of the memory cell. The storage electrodes SP and the transfer electrodes TE are now part of the circuit WL. The bit line BLM, which is not diffused into the semiconductor substrate, is perpendicular to the word line WL. The word line WL, the storage electrode SP and the transfer electrode TE can be made of polysilicon. The bit line BLM , on the other hand, can consist of metal.

The cross section through the memory cell of FIG. 8 at the point IX-IX is shown in FIG. 9. Two memory cells are again arranged next to one another and shown together. In the area of the memory cell, a part of the bit line, which is denoted by BL , diffuses into the semiconductor substrate SU . The transfer electrode TE is arranged adjacent to the bit line BL. It is separated from the semiconductor substrate surface by an insulating layer / S3. The transfer electrode TE overlaps the bit line BL

The storage electrode SP is connected to the transfer electrode TE. Between the storage electrode SP

ίο and the substrate surface an insulating layer IS4 is arranged. The storage capacitance SK is formed by the storage electrode SP, the insulating layer / S 4 and the inversion layer £. As can be seen from FIG. 9, the thickness of the insulating layer / S3 is greater than the thickness of the insulating layer IS 4.

The bit line BLM , which is separated from them by an insulating layer / S 5, is arranged above the word line WL or the storage electrode SP and the transfer electrode TE. The bit line BLM is contacted through the insulating layer / 55 to the part of the bit line BL which is diffused in the semiconductor substrate. The thickness of the insulating layer / S 5 can be selected so that capacitive coupling between the bit line BLM and the word line WL is slight.

For this purpose 4 sheets of drawings

Claims (10)

Patent claims: 1. Semiconductor memory in which each memory cell for storing information contains a storage capacity formed with the aid of an insulated storage electrode arranged above the semiconductor substrate, and in which the charge is between the storage capacity and a bit line by means of an insulated over the semiconductor substrate, adjacent to the Storage electrode and the transfer electrode arranged on the bit line to be exchangeable, characterized in that the memory cell is designed so that the threshold voltage (UTT) to be exceeded on the transfer electrode (TE) for the transfer of charge from the bit line to the storage capacity is greater than that on the storage electrode (SP) threshold voltage to be exceeded (UTSX which is required to generate the storage capacity (SK) , and that the transfer electrode (TE) and the storage electrode (3 / ^ are electrically connected to one another. 2. Semiconductor memory according to claim 1, characterized in that the difference in the threshold voltages (UTT, UTS) is determined by a different thickness of the insulating layers between the transfer electrode (TE) and the substrate surface or the storage electrode (SP) and the substrate surface. 3. Semiconductor memory according to claim 1 or 2, characterized in that a substrate voltage (VSUB) is connected to the semiconductor substrate (SU) , that the transfer electrode (TE) in the case of electrons as charge carriers when reading information from or when writing information in a memory cell is driven by a first voltage (VH) that is positive with respect to the substrate voltage (VSUB), is driven to erase the information in a memory cell with a voltage less than or equal to the substrate voltage (VSUB) , so that the information about the semiconductor substrate is erased and if the memory cell is not selected, a second voltage (VL) lying between the first voltage (VH) and the substrate voltage (VSUB) is driven. 4. Semiconductor memory according to Claim 3, characterized in that the second voltage (VL) is applied to the bit line (BL) as a preparation voltage before information is read from a memory cell 5. Semiconductor memory according to one of the preceding claims, characterized in that the bit line (BL) is diffused into the semiconductor substrate (SU) , that the transfer electrode (TE) and the storage electrode (SP) consist of a common line, that above this common line and the word line (WL), which is in contact with the common line through the insulating layer, is arranged so as to be insulated from this. 6. Semiconductor memory according to claim 5, characterized in that the word line is made of metal consists 7. Semiconductor memory according to claim 5, characterized in that the common line consists of Consists of polysilicon. « 8. Semiconductor memory according to one of claims 1 to 3, characterized in that the word line (WL) simultaneously forms the storage electrodes (SP) and the transfer electrodes f7 £> that the bit line is diffused into the semiconductor substrate (SU) only in the area of the memory cell , is otherwise arranged over the word lines (WL) separated by an insulating layer (ISA) and is only in contact with the bit line (BL) diffused into the semiconductor substrate (SU) through the insulating layer in the area of the memory cell 9. Semiconductor memory according to claims, characterized in that the part of the bit line (BLM) which is not diffused into the semiconductor substrate consists of metal 10. Semiconductor memory according to claim 7, characterized characterized in that the word line consists of polysilicon