GB1565460A - Fibonacci code adders - Google Patents

Fibonacci code adders Download PDF

Info

Publication number
GB1565460A
GB1565460A GB53430/77A GB5343077A GB1565460A GB 1565460 A GB1565460 A GB 1565460A GB 53430/77 A GB53430/77 A GB 53430/77A GB 5343077 A GB5343077 A GB 5343077A GB 1565460 A GB1565460 A GB 1565460A
Authority
GB
United Kingdom
Prior art keywords
input
gate
output
coupled
carry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB53430/77A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TAGANROG RADIOTECKN INST IM V
Original Assignee
TAGANROG RADIOTECKN INST IM V
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TAGANROG RADIOTECKN INST IM V filed Critical TAGANROG RADIOTECKN INST IM V
Publication of GB1565460A publication Critical patent/GB1565460A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Complex Calculations (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Logic Circuits (AREA)
GB53430/77A 1976-12-22 1977-12-22 Fibonacci code adders Expired GB1565460A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU762432391A SU732864A1 (ru) 1976-12-22 1976-12-22 Сумматор кодов фибоначчи

Publications (1)

Publication Number Publication Date
GB1565460A true GB1565460A (en) 1980-04-23

Family

ID=20687540

Family Applications (1)

Application Number Title Priority Date Filing Date
GB53430/77A Expired GB1565460A (en) 1976-12-22 1977-12-22 Fibonacci code adders

Country Status (9)

Country Link
US (1) US4159529A (enExample)
JP (1) JPS53101242A (enExample)
CA (1) CA1103807A (enExample)
DD (1) DD136317A1 (enExample)
DE (1) DE2756832A1 (enExample)
FR (1) FR2375655A1 (enExample)
GB (1) GB1565460A (enExample)
PL (1) PL109971B1 (enExample)
SU (1) SU732864A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU840891A1 (ru) * 1978-05-15 1981-06-23 Винницкийполитехнический Институт Параллельный сумматор кодов фибоначчи
EP0754373B1 (en) * 1995-02-03 2001-06-06 Koninklijke Philips Electronics N.V. Encoding arrangement for encoding a sequence of (n-1)-bit information words into a sequence of n-bit channel words, and a decoding arrangement for decoding a sequence of n-bit channel words into a sequence of (n-1) bit information words
US6934733B1 (en) * 2001-12-12 2005-08-23 Lsi Logic Corporation Optimization of adder based circuit architecture
CN112787658B (zh) * 2020-12-31 2022-12-13 卓尔智联(武汉)研究院有限公司 基于斐波那契进制的逻辑运算电路
US12511123B2 (en) * 2022-10-28 2025-12-30 Jun Zhou Fast carry-calculation oriented redundancy-tolerated fixed-point number coding for massive parallel ALU circuitry design in GPU, TPU, NPU, AI infer chip, CPU, and other computing devices

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1547633A (fr) * 1967-10-16 1968-11-29 Labo Cent Telecommunicat Circuit d'addition de nombres binaires provenant du codage non linéaire de signaux

Also Published As

Publication number Publication date
US4159529A (en) 1979-06-26
PL203158A1 (pl) 1978-12-18
SU732864A1 (ru) 1980-05-05
FR2375655A1 (fr) 1978-07-21
JPS53101242A (en) 1978-09-04
JPS573100B2 (enExample) 1982-01-20
CA1103807A (en) 1981-06-23
PL109971B1 (en) 1980-06-30
FR2375655B1 (enExample) 1980-08-22
DD136317A1 (de) 1979-06-27
DE2756832A1 (de) 1978-07-06

Similar Documents

Publication Publication Date Title
Avizienis Arithmetic algorithms for error-coded operands
JPS6132437Y2 (enExample)
US5253195A (en) High speed multiplier
US3699326A (en) Rounding numbers expressed in 2{40 s complement notation
US3098994A (en) Self checking digital computer system
GB815751A (en) Improvements in electric calculators and accumulators therefor
US5144576A (en) Signed digit multiplier
US3596074A (en) Serial by character multifunctional modular unit
US4187500A (en) Method and device for reduction of Fibonacci p-codes to minimal form
GB1565460A (en) Fibonacci code adders
GB1579100A (en) Digital arithmetic method and means
US3001708A (en) Central control circuit for computers
US3937941A (en) Method and apparatus for packed BCD sign arithmetic employing a two's complement binary adder
US3564225A (en) Serial binary coded decimal converter
KR102863363B1 (ko) 데이터 계산 회로 및 방법
US4276608A (en) Fibonacci p-code parallel adder
US3582634A (en) Electrical circuit for multiplying serial binary numbers by a parallel number
Fenwick Introduction to computer data representation
US3056550A (en) Variable-exponent computers
US3489888A (en) Floating point look-ahead binary multiplication system utilizing two's complement notation for representing negative numbers
US3604909A (en) Modular unit for digital arithmetic systems
US3113204A (en) Parity checked shift register counting circuits
US3500027A (en) Computer having sum of products instruction capability
EP0534760A2 (en) High speed multiplier device
US3509330A (en) Binary accumulator with roundoff

Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee