GB1529859A - Arrangement for generating timing signals - Google Patents

Abstract

1529859 Frequency dividers INTERNATIONAL STANDARD ELECTRIC CORP 18 Dec 1975 [21 Dec 1974] 51875/75 Heading G4D A system for producing a plurality of different clock pulse trains comprises a first store Spl which stores values representing the periods of the clock pulse trains; a second store Sp2 which stores a value representing the length of the pulses; a counting device which is advanced at fixed intervals by a reference clock Gen; and a comparator Vg1 which detects when the count in Sp3 is equal to the value in Sp1 to start a new pulse (and reset the counter to zero) and when the count is equal to the value in Sp2 to end the pulse.. As described, Fig. 1 provides 180 ms. pulses at various intervals up to 15 sees. for timing and pricing calls on a telephone system. The reference clock Gen. sweeps three switching devices W1-W2-W3 through all positions once every 10 ms. At each new sweep all the storage locations in Sp3 are advanced by one. At each step the comparator Vg1 compares the count in the respective storage location in Sp3 with the value in Sp2 which is fixed equal to 18 and with the corresponding location in Sp1. When the corresponding locations in Sp1, Sp3 agree a corresponding flip-flop FF is set and the value in that location in Sp3 is reset to zero. When a value in Sp3 is equal to Sp2 the corresponding flip-flop is reset. The outputs of the flip-flops are the set of clock pulse trains. Where periods are related Sp1 may have only half the number of locations as Sp3 and a divider (D) is introduced between Sp1 and the comparator on alternate steps of the switching device (Fig. 2, not shown). The various functions of Fig. I may be carried out by a microprocessor (Fig. 3, not shown); Sp3 is then a RAM and Spl a ROM or PROM. The store Sp1 may have several different values in each location, the required one being selected according to time of day to cope with varying tariffs.