GB1523218A - Parity checking arrangements - Google Patents

Parity checking arrangements

Info

Publication number
GB1523218A
GB1523218A GB3990476A GB3990476A GB1523218A GB 1523218 A GB1523218 A GB 1523218A GB 3990476 A GB3990476 A GB 3990476A GB 3990476 A GB3990476 A GB 3990476A GB 1523218 A GB1523218 A GB 1523218A
Authority
GB
United Kingdom
Prior art keywords
parity
fields
message
check
field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3990476A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Co Ltd
Original Assignee
Plessey Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Co Ltd filed Critical Plessey Co Ltd
Priority to GB3990476A priority Critical patent/GB1523218A/en
Publication of GB1523218A publication Critical patent/GB1523218A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H04L1/0063—Single parity check

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

1523218 Parity checking PLESSEY CO Ltd 3 Feb 1977 [25 Sept 1976] 39904/76 Heading H4P A message comprising a plurality F 1, F2, F3 of data fields and a parity bit PO is enabled by signal POK to pass to field storage elements S1, S2, S3 only provided that the parity check for the message as a whole, performed by checker PC 1 as well as a parity check involving the parity bit PO, and field parity bits P1-P3 generated and PG1-3 from the respective fields, are both successful. Before a message of fields FA, FB, FC, can be read out, their parity is determined by generator PG4, whose output POR is checked at PC3 with the field parity bits PA-PC. Should the check be successful register RO is enabled to store the fields and the generated parity bit POR.
GB3990476A 1977-02-03 1977-02-03 Parity checking arrangements Expired GB1523218A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB3990476A GB1523218A (en) 1977-02-03 1977-02-03 Parity checking arrangements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB3990476A GB1523218A (en) 1977-02-03 1977-02-03 Parity checking arrangements

Publications (1)

Publication Number Publication Date
GB1523218A true GB1523218A (en) 1978-08-31

Family

ID=10412117

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3990476A Expired GB1523218A (en) 1977-02-03 1977-02-03 Parity checking arrangements

Country Status (1)

Country Link
GB (1) GB1523218A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0013885A2 (en) * 1979-01-26 1980-08-06 International Business Machines Corporation Method of avoiding undesirable parity error signals during the parity check of a register array and parity check device for carrying out the method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0013885A2 (en) * 1979-01-26 1980-08-06 International Business Machines Corporation Method of avoiding undesirable parity error signals during the parity check of a register array and parity check device for carrying out the method
EP0013885A3 (en) * 1979-01-26 1981-04-01 International Business Machines Corporation Parity check device for a register array

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Legal Events

Date Code Title Description
PS Patent sealed
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee