GB1518166A - Monolithically integrable delay line circuit - Google Patents
Monolithically integrable delay line circuitInfo
- Publication number
- GB1518166A GB1518166A GB38431/75A GB3843175A GB1518166A GB 1518166 A GB1518166 A GB 1518166A GB 38431/75 A GB38431/75 A GB 38431/75A GB 3843175 A GB3843175 A GB 3843175A GB 1518166 A GB1518166 A GB 1518166A
- Authority
- GB
- United Kingdom
- Prior art keywords
- delay
- delay line
- line circuit
- sept
- chain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
1518166 Active filters ITT INDUSTRIES Inc 18 Sept 1975 [18 Sept 1974] 38431/75 Heading H3U In a delay circuit, analogue signals S to be delayed phase modulate a pulse train from generator I, the resulting modulated signal being fed via a delay L comprising a chain of semiconductor stages to a demodulator D. The overall delay is maintained constant by comparing the phases of the input and output signals in comparator P to produce a signal which controls the delay of line L. The pulse generator and delay Fig. 1 (not shown) may comprise a chain of transistors and may employ I<SP>2</SP>L (not shown).
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19742444486 DE2444486A1 (en) | 1974-09-18 | 1974-09-18 | MONOLITHICALLY INTEGRATED DELAY CIRCUIT |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1518166A true GB1518166A (en) | 1978-07-19 |
Family
ID=5926026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB38431/75A Expired GB1518166A (en) | 1974-09-18 | 1975-09-18 | Monolithically integrable delay line circuit |
Country Status (4)
| Country | Link |
|---|---|
| DE (1) | DE2444486A1 (en) |
| FR (1) | FR2285750A1 (en) |
| GB (1) | GB1518166A (en) |
| IT (1) | IT1042571B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2071943B (en) * | 1980-03-10 | 1984-06-27 | Control Data Corp | Delay lock loop |
| DE3217050A1 (en) * | 1982-05-06 | 1983-11-10 | Siemens AG, 1000 Berlin und 8000 München | Delay circuit for digital signals |
| JPS5972814A (en) * | 1982-10-20 | 1984-04-24 | Sanyo Electric Co Ltd | Delay circuit |
| DE3585706D1 (en) * | 1984-07-05 | 1992-04-30 | Hewlett Packard Co | DELAY CIRCUIT. |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1178460B (en) * | 1962-05-29 | 1964-09-24 | Siemens Ag | Circuit for devices of the electrical communication technology for the delay of a continuous signal voltage |
-
1974
- 1974-09-18 DE DE19742444486 patent/DE2444486A1/en not_active Withdrawn
-
1975
- 1975-09-16 IT IT27262/75A patent/IT1042571B/en active
- 1975-09-17 FR FR7528460A patent/FR2285750A1/en not_active Withdrawn
- 1975-09-18 GB GB38431/75A patent/GB1518166A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2285750A1 (en) | 1976-04-16 |
| IT1042571B (en) | 1980-01-30 |
| DE2444486A1 (en) | 1976-04-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PCNP | Patent ceased through non-payment of renewal fee |