GB1514956A - Computer system - Google Patents

Abstract

1514956 Control of peripheral apparatus PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES LTD 5 Sept 1975 [7 Sept 1974] 36622/75 Heading G4A Peripheral apparatus PG1, PG2 (Fig. 1) are linked to a central control unit CPU by a common bidirectional data bus DD, a common unidirectional control line DC1, the signal state of which indicates the type of information on the bus, a common unidirectional signal line DSL the signal state of which indicates whether an addressed peripheral is able to send or receive data, an individual selection line DSE1, DSE2 on which the CPU selects the peripheral (as described by closing a switch SSE) and an individual request line DRE1, DRE2 on which the peripheral sends a request for data transfer As described a second control line (DD2, Fig. 2, not shown) indicate the direction of transfer and a third control line (DC3) indicates whether control commands or a status information is to be transferred. When lines DC1, DC2, DC3 carry no signal, information from the CPU on the data bus DD is applied to a primary control command (PC) via switch (SD1). When DC1 carries a signal the information is applied to a store (DSP). When line DC2 carries a signal a primary status signal (PS) or data from a store (SPA) is transmitted in dependence on the signal on line DC1. When line DC3 carries a signal if line DC2 carries no signal one of two secondary control commands (SC1, SC2) are supplied from the CPU in dependance on the signal on line DC1. If line DC2 carries a signal one of two status signal (SS1, SS2) are fed to the CPU. Data on the bus is parity checked in a unit (PP), a signal on line DFL being transmitted if an error is detected. Each peripheral includes status indicators (B1, AT, UX, CR, Fig. 3, not shown), a modification in a predetermined status indicator (CR) resulting in a command request being generated (and erasing any possible data requests). Several peripherals UG1, UG2 ... UGn (Fig. 4) may be connected to a single connection unit PA linked to the CPU by the lines DD, DSE1, DRE1. In the absence of a signal from the CPU on selection line DSE1, a signal is repeatedly sent on line DPX connected serially to all the peripheral units in order of priority to close switch SRE in the highest priority unit having a request signal DR1 (as shown peripheral UG1). If a request signal exists a signal is fed via line DPRE to line DRE1 and a switch SPY is then opened to prevent switches SRE in units of lower priority being operated. If no request is present a return signal is received on line DPY. The signal on line DRE1 results in a signal on line DSE1 closing switches SSE so that unit AV actuated by the signal DR1 sends its address on the data bus to the central control unit. The control unit then sends an address representing the peripheral UG1 which is recognized by the unit AV and results in switch SDD being closed to prevent data transfer.