GB1445897A - System for transfer of data between central units and controlled units - Google Patents
System for transfer of data between central units and controlled unitsInfo
- Publication number
- GB1445897A GB1445897A GB1373174A GB1373174A GB1445897A GB 1445897 A GB1445897 A GB 1445897A GB 1373174 A GB1373174 A GB 1373174A GB 1373174 A GB1373174 A GB 1373174A GB 1445897 A GB1445897 A GB 1445897A
- Authority
- GB
- United Kingdom
- Prior art keywords
- central unit
- sent
- order
- instruction
- bpe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54508—Configuration, initialisation
- H04Q3/54516—Initialization, software or data downloading
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/1305—Software aspects
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13109—Initializing, personal profile
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13376—Information service, downloading of information, 0800/0900 services
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Computer And Data Communications (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Exchange Systems With Centralized Control (AREA)
Abstract
1445897 Data handling system INTERNATIONAL STANDARD ELECTRIC CORP 28 March 1974 [5 April 1973] 13731/74 Heading G4A A data handling system includes two central units UCA, UCB, and a plurality of groups of controlled units, e.g. OG1-OGn, each group being connected to each of the central units via respective interfaces, DR1A, DR1B &c., which transmit orders from the central units to the controlled units, and is arranged such that a central unit wishing to transmit an order does so directly via the appropriate interface if that interface is available, but if it is not available, transmits the order to the other central unit via a transmission link IPL for transmission by that other unit. The controlled units may be telephone or telegraph installation remotely controlled by central processing units. Each central unit includes a memory ME addressed by a normally incremented program counter CP, an instruction op code decoder DEC, and a register M for the address part of an instruction. The memory contains a series of instructions 1NS1-1NSn with op code, Cl, and address, AR, parts and a series of transmission control registers. These last registers include a register BPE# for each associated interface in which bit 0 indicates whether the unit has previously transmitted an order, bit 1 indicates whether the memory contains an order, in a register BPE3 one of which is provided for each interface, originating from the other central unit, bit 2 indicates when an order from the other central unit has been sent by the central unit via one of its own interfaces, and bit 4 indicates when the central unit has transmitted an order to the other central unit for transmission by that unit. Registers BT1A and BT1B respectively indicate at each bit position whether a corresponding one of the interfaces associated with the central unit and the other central unit is available. Register HL#, one of which is provided for each interface, points to one of the registers following, HL#A &c., which contains the next order to be sent by the central unit to the interface, the contents of HL# being decremented as each order is sent until the contents are zero which is interpreted as meaning that the unit has no more orders to send. Operation follows the flow charts of Figs. 3-5 (not shown) in which an interrupt from an interface to a central unit, say UCA, causes BPE# to be examined to see if the central unit had previously sent an order. If it had further examination of BPE# indicates whether it was sent on its own behalf or for the other central unit. In the latter case the appropriate data is sent to that other unit, BPE# is reset to zero, and the next order pointed to by HL# located. If this order exists the appropriate bit position of BT1A is examined to determine whether the appropriate interface is available. If so the order is sent and bit 0 of BPE# set to reflect the fact. If the previous order was sent by the central unit on its own behalf bit 1 of BPE# is examined to determine whether an instruction from the other central unit is stored in BPE3. If so and the appropriate interface is available bits 0 and 2 of BPE# are set and the instruction sent. If the unit had not sent an instruction when the interrupt occurs HL# is examined to locate the next instruction if it exists. If it does the order is sent as above. If not bit 1 of BPE# is examined to determine whether an instruction from the other central unit is stored in BPE3. If so the instruction is sent as above. If when UCA is to send an instruction, BT1A is examined and the appropriate interface is not available, BT1B is examined to determine whether the other central unit has access to the appropriate one of its interfaces. If it has bits 0 and 4 of BPE# are set and the instruction and the identity of the appropriate interface are sent to UCB where the instruction is stored in register BPE3 and bit 1 of BPE# is set.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7312241A FR2224959B1 (en) | 1973-04-05 | 1973-04-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1445897A true GB1445897A (en) | 1976-08-11 |
Family
ID=9117447
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1373174A Expired GB1445897A (en) | 1973-04-05 | 1974-03-28 | System for transfer of data between central units and controlled units |
Country Status (8)
Country | Link |
---|---|
BE (1) | BE813270A (en) |
CH (1) | CH588199A5 (en) |
DE (1) | DE2416268C3 (en) |
ES (1) | ES424940A1 (en) |
FR (1) | FR2224959B1 (en) |
GB (1) | GB1445897A (en) |
IT (1) | IT1009708B (en) |
NL (1) | NL7404434A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2204432A (en) * | 1987-05-01 | 1988-11-09 | Atomic Energy Authority Uk | Multiple processor networks |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1036311B (en) * | 1975-06-17 | 1979-10-30 | Cselt Centro Studi Lab Telecom | DUPLICATE SYSTEM FOR SUPERVISION AND CONTROL OF DUPLICATED TELECOMMUNICATION SYSTEMS |
DE2718277A1 (en) * | 1977-04-25 | 1978-11-02 | Gen Electric Co Ltd | Digital switching system in computer controlled exchange - has input and output queuing facilities, and identification of input and output lines and channels |
DE2743923C3 (en) * | 1977-09-29 | 1985-02-21 | Siemens AG, 1000 Berlin und 8000 München | Circuit arrangement for telecommunications switching systems, in particular telephone switching systems, with connection-specific switching devices and sub-central control devices assigned to them |
JPS6061850A (en) * | 1983-09-12 | 1985-04-09 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Computer system |
-
1973
- 1973-04-05 FR FR7312241A patent/FR2224959B1/fr not_active Expired
-
1974
- 1974-03-28 GB GB1373174A patent/GB1445897A/en not_active Expired
- 1974-04-02 NL NL7404434A patent/NL7404434A/xx unknown
- 1974-04-03 DE DE19742416268 patent/DE2416268C3/en not_active Expired
- 1974-04-04 CH CH474874A patent/CH588199A5/xx not_active IP Right Cessation
- 1974-04-04 ES ES424940A patent/ES424940A1/en not_active Expired
- 1974-04-04 BE BE2053529A patent/BE813270A/en unknown
- 1974-04-08 IT IT2099474A patent/IT1009708B/en active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2204432A (en) * | 1987-05-01 | 1988-11-09 | Atomic Energy Authority Uk | Multiple processor networks |
Also Published As
Publication number | Publication date |
---|---|
FR2224959B1 (en) | 1976-09-10 |
FR2224959A1 (en) | 1974-10-31 |
BE813270A (en) | 1974-10-04 |
AU6745674A (en) | 1975-10-02 |
CH588199A5 (en) | 1977-05-31 |
DE2416268C3 (en) | 1982-12-16 |
DE2416268A1 (en) | 1974-10-24 |
IT1009708B (en) | 1976-12-20 |
NL7404434A (en) | 1974-10-08 |
ES424940A1 (en) | 1976-06-01 |
DE2416268B2 (en) | 1977-12-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
746 | Register noted 'licences of right' (sect. 46/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |