GB1503321A - Digital data processors and methods of operating such processors - Google Patents

Abstract

1503321 Data processing BURROUGHS CORP 27 Jan 1975 [28 Feb 1974 (5) 13 Sept 1974 (5)] 3416/75 Heading G4A A data-driven data processor includes a store holding a plurality of operators each designating an operation to be performed on data supplied to the processor, and as soon as all the data required for the performance of any one of the operators currently in the store has been supplied to the processor, the operation designated by that operator is performed. The data may be in the form of structures which include an operand and an address identifying the appertaining operator in the store, e.g. by program file and by position within that file. All data may be represented by four characters, 1, 0, (,), each represented by a two-bit code. A program file stored in a store 25 may then be of the form ((A) (B) (C) . . . (D) (E)), A being a description field (for a program A is P) identifying the types of the following fields, E is a terminating field, and B, C and D are fields which may contain operands or operators; for a program file B specifies the operator and C and D being initially empty until the required operands are received by the input queue 21. The program file also includes a destination address field. Operand fields C and D may themselves be one or more program files of the same format (the description field A for each being V); for example each operand file C, D may specify an addition the results of which are subtracted. Each operand file received by an input queue 21 is of the same format, the description field A being L (literal) and being followed by address fields and an operand field. Each step of the program specified by the program file is executed when the required operands have been received by input queue 21. In an alternative arrangement store 25 stores operand files and input queue 21 receives program files while other program files are in storage. To detect errors in the data received by the input queue 21 the left and right brackets in each file are counted, detection of a left bracket, (, causing incrementation of a counter (65, Figs. 2, 6, not shown) and detection of a right bracket, ), causing decrementation of the counter, a non-zero count from the counter after a complete file has been received indicating an error and causing the file to be re-transmitted from an input/output exchange 13. The logic unit 27 includes respective read only memories (125, 129, Fig. 3, not shown) for two-operand and single-operand operations. The control unit 23 includes an analyser (146, Fig. 4, not shown) formed by a read only memory which receives respective data files from the store 25 and input queue 21. The analyser (146) controls three demultiplexors in dependence on the received data file, a received operand file being supplied via one of these demultiplexors to units 25, 27 and 29. On receipt of a program file the analyser supplies signals to three micro-program read-only memories which supply micro-instructions to control the logic unit 27.