GB1501748A - Pulse generator circuits - Google Patents

Abstract

1501748 Semi-conductor pulse oscillator HITACHI Ltd 27 Oct 1975 [30 Oct 1974] 44205/75 Heading H3T A pulse oscillator comprises a ring of three FET inverter stages, each having a load and two having a coupling resistance means to the gate of the next stage, each gate being shunted by a capacitor which may be the gate capacitance of the FET. In an integrated circuit the loads and resistance means are all FET's and the capacitances added if necessary small enough to be integrated. Since all FET's on the IC tend to have consistent characteristics, the FET Tl of bias circuit BC will pass a large current producing a high bias across R3 if all the FET's in the circuit require a high bias to limit their currents; and similarly if low bias is required, stabilizing frequency against FET tolerances, supply voltage and temperature. All FET's Td- and Tztogether with T1 in the Figure are P- channel enhancement types, while TR1 and TR2 may be P-channel enhancement or depletion types. In an alternative embodiment (Fig. 4, not shown) the Tz- FET's are P-channel depletion types with the gates of Tzl and Tz2 taken to the bias line but with Tz3 gate connected to its own source (the Vout terminal). The T1 P-channel enhancement FET is shunted by a P-channel depletion type FET with its gate shorted to its source (ground). TR1 and TR2 are of P-channel depletion types. These modifications enable the inverter stages to be run at higher potentials, and provide a bias circuit BC compensating for variation in both enhancement and depletion types of FET.