GB1500996A - Analogue/digital or digital/analogue converters - Google Patents

Abstract

1500996 Delta modulation L M ERICSSON PTY Ltd 14 April 1975 15301/75 Heading H3H In a companded delta codec, the step size is adjusted in dependence on the average of the high slope regions. In an encoder, Fig. 1, logic 27 controls a current pulse generator 28 to generate a positive current if the last four delta bits are 1111 or 0000 and a much smaller negative current otherwise. The resulting voltage on capacitor 30 is fed via an antilog converter 31 to a current pulse amplitude modulator 33 which receives polarity signals from the input stage of the register 24. Integrator 34 forms the feedback signal 22 to comparator 20. The effect is that the step size can increase at an attack rate of À7dB/clock pulse (e.g. 64 kHz) or otherwise between À25 and 3dB/clock pulse, but the decay rate is between <SP>1</SP>/ 3 and <SP>1</SP>/ 500 of the attack rate, preferably about <SP>1</SP>/ 100 . A corresponding decoder (Fig. 2, not shown) has a filter (36) instead of comparator 20. Some theory and figures are given.