GB1469751A - Memory arrangement for a page printer - Google Patents

Abstract

1469751 Printers; data storage MULLARD Ltd 16 April 1974 [14 Feb 1973] 7303/73 Addition to 1469231 Headings G4H and G4C The invention is a memory (for a page printer) having addressing counters which can be connected in different arrangements by switches. In Fig. 2, 17 lines of 64 characters (each of 8 bits) per line, are received serially by line, character and bit, at I/P and stored in nine 1024-bit memory units Mc1-Mc9, two lines per unit (except unit Mc9, the second half of which is unused) under control of a chain of counters C1, C2, C3, C4, C5 of 3, 2, 4, 1, 4 bits respectively, the chain being driven by clock pulses CP, and switches S1, S2 being in the positions shown so each counter (except C5) drives the next in the chain. Counter C1 selects bits within a character, and counter C5, via a decoder D1, selects the memory units Mc1-Mc9, C4 and C5 in combination selecting the line. For read-out to a read only memory controlling a matrix page printer, the switches S1, S2 are reversed so that the first character of each line is read out, serially by character and bit, then the second character of each line, and so on. For this, pulses CP drive C1 which drives C4 which drives C5, to read out a given character in each line, this being done 42 times viz. 7 x 5 times for the matrix build-up of each character plus 7 Î 1 times for a space between characters. Then an end-of-character signal EOCHC drives C2 which drives C3, to select the next character position, which is read out for all the lines in turn, 42 times, as before, and so on. Each memory unit Mc1- Mc9 is a MOS memory on a semi-conductor chip, or uses magnetic cores.