GB1469231A - Memory arrangement for a page printer - Google Patents

Abstract

1469231 Printers; data storage MULLARD Ltd 16 April 1974 [14 Feb 1973] 7302/73 Headings G4H and G4C The invention is a memory (for a page printer) having addressing counters which can be connected in different arrangements by switches. In Fig. 2, 25 lines of 80 characters (each of 8 bits) per line, are received serially by line, character and bit, at I/P, and stored in sixteen 1024-bit memory units Mc1-Mc16, the 1st- 8th lines each being split between units Mc1- Mc5 on the basis of 16 characters per unit per line, the 9th-16th and 17th-24th being similarly placed in Mc6-Mc10, Mc11-Mc15, and the 25th in Mc16. For this purpose clock pulses CP drive a chain of counters C1, C2, C3, C4, C5 of 3, 4, 3, 3, 2 bits respectively, with decoders D1, D2, D3, as shown, the switches S1, S2 being being in the positions shown, counter C1 selecting bits within character, the memory units Mc1-Mc15 being selected by decoder D2 and unit Mc16 being selected by the last output of decoder D3. For read-out to a read-only memory control a matrix page printer, the switches S1, S2 are reversed so that the first character of each line is read out, serially by character and bit, pulses CP driving C1 which drives C4 which drives C5, for this purpose, this being done 42 times viz. 7 x 5 times for the matrix build-up of each character plus 7 x 1 times for a space between characters. Then an end-of-character signal EOCHC drives C2 which drives C3, to select the second character position, which is read out for all the lines in turn, 42 times, as before, and so on. Variations in the numbers of lines, characters per line, and memory units, are mentioned.