GB1448180A - Arrangement for transferring information from a central unit to peripheral units particularly for use in telecommunications - Google Patents

Abstract

1448180 Data transmission; exchange arrangements INTERNATIONAL STANDARD ELECTRIC CORP 6 Aug 1974 [16 Aug 1973] 34552/74 Heading H4P An arrangement for transferring from a central unit of a data processor, e.g. telecommunications exchange, through a sender (i.e. transmitting unit) to peripheral units having data stores, successive sending operations are controlled by a first clock pulse sequence with a mutually phase shifted equal frequency second clock pulse sequence used to receive at the central unit and evaluate results of operations specified by sent data. Dependent on evaluation results, a write instruction is sent to a group or all of the stores, which instruction is only effective in the store(s) marked by a signal sent from a sequence control circuit controlled by a third clock pulse sequence sent between pulses of second and first sequences. Advancement of the sequential circuit to next position is effected in some positions directly by third sequence pulses and in other positions only in response to simultaneous occurrence of third sequence pulses and a determined reply signal from a peripheral unit. In one embodiment a write wire energized by the sequence circuit enables each store in turn but in another embodiment two write wires are provided to transfer instructions alternately in response to position of sequence control and reply signal, the write wires being alternately connected to storage means with the sequence control circuit controlling two successive information stores at a time. The arrangement is stated to have the advantage that transfer of data takes place while evaluation is still under way and immediately on completion, the data having been "stabilized" can be written. An idle path for a call to be set up is sought in each of the stages in a switching network KM. In quiescent state sequence controller SS rests in the position s0. A start instruction St through AND gate U7 primes through OR gate 05, AND gate U6, hence next clock pulse Tst causes SS to switch to state s1, this setting flip-flop FF which in turn primes AND gate U4. The next clock pulse T1 starts address chain arrangement AK which transmits its first address over line WA to stores ASp1-ASp3. The next clock pulse T2 via AND gate U5 and OR-O1 controls transmission of a write instruction over line ES. The interval between pulses T1 and T2 allows the address over line WA to become stable so that it can be evaluated. Since only AND gate U1 is enabled, address over line WA is written into store SAp1 only. In KN a test is now performed to ascertain whether the cross point specified by the address is idle. Meanwhile, the clock pulse generator provides another pulse Tst (in the sequence Tst, T1, T2) and SS switches to s2 due to U6 being enabled via s1; U1 is maintained open via OR gate 02. Next pulse T1 bounces address chain AK one position and next address is sent over WA followed by another pulse T2 which is ineffective as U5 is not enabled from s2; T2 enables evaluating circuit AA and dependent on the signal from the switching network over AN either AND gate U11 or U12 is enabled. If no path is found through KN, U12 provides a write instruction through lines NM, ES so that the next address is written into ASp1 store hence successive addresses are written into this store until an idle line is found. When this is so, AND gate U11 is opened by T2 pulse and U6 enabled over line M and AND gate U8 (rpimed by s2) which signal remains until next clock pulse Tst when SS switches to s3. Addresses are now written from AK into ASp2. While SS is being switched to s3, an address from AK is not written. If an idle path is found in the second stage SS switches successively to s5, s6 and searching proceeds in ASp3 and if search succeeds here SS switches via s7 to s0. While in state s7 flip-flop FF is reset and an end signal sent over line E. As addresses of selected idle paths are stored, connections can now be set up. AK may be a circulating binary counting chain which can count to a number of matrixes in a stage and when it reaches the last binary number returns to the start. It is usually necessary to test several addresses per stage during normal operation. If storage time is to be made shorter, the arrangement of Fig. 2 (not shown) utilizing two write wires alternately may be employed.